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authorPeter Griffin <peter.griffin@linaro.org>2015-01-16 10:04:11 -0500
committerKishon Vijay Abraham I <kishon@ti.com>2015-01-21 04:53:06 -0500
commit5402d927ae96bd1413ecc6bac966fd8b6d3b8159 (patch)
tree499b3ce01207348e6d8f41afd5a9eb72aebf62ba
parentde6e0f84bebc0daadca46e735f4b2be3e006d05d (diff)
phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg property.
Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161, update the phy driver to not use the reg property to access the sysconfig register offsets. This is because other phy's (miphy28, miphy365) have a combination of memory mapped registers and sysconfig control regs, and we shouldn't be mixing address spaces in the reg property. In addition we would ideally like the sysconfig offsets to be passed via DT in a uniform way. This new method will also allow us to support devices which have sysconfig registers in different banks more easily and it is also analagous to how keystone and bcm7745 platforms pass there syscon offsets in DT. This breaks DT compatibility, but this platform is considered WIP, and is only used by a few developers who are upstreaming support for it. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r--Documentation/devicetree/bindings/phy/phy-stih407-usb.txt10
-rw-r--r--drivers/phy/phy-stih407-usb.c25
2 files changed, 16 insertions, 19 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
index 1ef8228db73b..de6a706abcdb 100644
--- a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa
5 5
6Required properties: 6Required properties:
7- compatible : should be "st,stih407-usb2-phy" 7- compatible : should be "st,stih407-usb2-phy"
8- reg : contain the offset and length of the system configuration registers 8- st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
9 used as glue logic to control & parameter phy
10- reg-names : the names of the system configuration registers in "reg", should be "param" and "reg"
11- st,syscfg : sysconfig register to manage phy parameter at driver level
12- resets : list of phandle and reset specifier pairs. There should be two entries, one 9- resets : list of phandle and reset specifier pairs. There should be two entries, one
13 for the whole phy and one for the port 10 for the whole phy and one for the port
14- reset-names : list of reset signal names. Should be "global" and "port" 11- reset-names : list of reset signal names. Should be "global" and "port"
@@ -19,11 +16,8 @@ Example:
19 16
20usb2_picophy0: usbpicophy@f8 { 17usb2_picophy0: usbpicophy@f8 {
21 compatible = "st,stih407-usb2-phy"; 18 compatible = "st,stih407-usb2-phy";
22 reg = <0xf8 0x04>, /* syscfg 5062 */
23 <0xf4 0x04>; /* syscfg 5061 */
24 reg-names = "param", "ctrl";
25 #phy-cells = <0>; 19 #phy-cells = <0>;
26 st,syscfg = <&syscfg_core>; 20 st,syscfg = <&syscfg_core 0x100 0xf4>;
27 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 21 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
28 <&picophyreset STIH407_PICOPHY0_RESET>; 22 <&picophyreset STIH407_PICOPHY0_RESET>;
29 reset-names = "global", "port"; 23 reset-names = "global", "port";
diff --git a/drivers/phy/phy-stih407-usb.c b/drivers/phy/phy-stih407-usb.c
index 74f0fab3cd8a..1d5ae5f8ef69 100644
--- a/drivers/phy/phy-stih407-usb.c
+++ b/drivers/phy/phy-stih407-usb.c
@@ -22,6 +22,9 @@
22#include <linux/mfd/syscon.h> 22#include <linux/mfd/syscon.h>
23#include <linux/phy/phy.h> 23#include <linux/phy/phy.h>
24 24
25#define PHYPARAM_REG 1
26#define PHYCTRL_REG 2
27
25/* Default PHY_SEL and REFCLKSEL configuration */ 28/* Default PHY_SEL and REFCLKSEL configuration */
26#define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6 29#define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6
27#define STIH407_USB_PICOPHY_CTRL_PORT_MASK 0x1f 30#define STIH407_USB_PICOPHY_CTRL_PORT_MASK 0x1f
@@ -93,7 +96,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
93 struct device_node *np = dev->of_node; 96 struct device_node *np = dev->of_node;
94 struct phy_provider *phy_provider; 97 struct phy_provider *phy_provider;
95 struct phy *phy; 98 struct phy *phy;
96 struct resource *res; 99 int ret;
97 100
98 phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL); 101 phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
99 if (!phy_dev) 102 if (!phy_dev)
@@ -123,19 +126,19 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
123 return PTR_ERR(phy_dev->regmap); 126 return PTR_ERR(phy_dev->regmap);
124 } 127 }
125 128
126 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 129 ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG,
127 if (!res) { 130 &phy_dev->param);
128 dev_err(dev, "No ctrl reg found\n"); 131 if (ret) {
129 return -ENXIO; 132 dev_err(dev, "can't get phyparam offset (%d)\n", ret);
133 return ret;
130 } 134 }
131 phy_dev->ctrl = res->start;
132 135
133 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "param"); 136 ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG,
134 if (!res) { 137 &phy_dev->ctrl);
135 dev_err(dev, "No param reg found\n"); 138 if (ret) {
136 return -ENXIO; 139 dev_err(dev, "can't get phyctrl offset (%d)\n", ret);
140 return ret;
137 } 141 }
138 phy_dev->param = res->start;
139 142
140 phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data); 143 phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
141 if (IS_ERR(phy)) { 144 if (IS_ERR(phy)) {