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authorKumar Gala <galak@kernel.crashing.org>2011-11-04 01:26:10 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:36 -0500
commit53e23dcb1894604ac8377fd4293d29116b9ae904 (patch)
tree183bffb4703b662234606f6f76671eeca7c3cd0f
parentb7f817547d7e1b56c1afbf4411df6fd73a0d78e9 (diff)
powerpc/85xx: Rework MPC8548CDS device trees
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi143
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi62
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts505
3 files changed, 327 insertions, 383 deletions
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
new file mode 100644
index 000000000000..9d8023a69d7d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -0,0 +1,143 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8540-pci";
56 device_type = "pci";
57 interrupts = <25 0x2 0 0>;
58 bus-range = <0 0xff>;
59 #interrupt-cells = <1>;
60 #size-cells = <2>;
61 #address-cells = <3>;
62};
63
64/* controller at 0xa000 */
65&pci2 {
66 compatible = "fsl,mpc8548-pcie";
67 device_type = "pci";
68 #size-cells = <2>;
69 #address-cells = <3>;
70 bus-range = <0 255>;
71 clock-frequency = <33333333>;
72 interrupts = <26 2 0 0>;
73
74 pcie@0 {
75 reg = <0 0 0 0 0>;
76 #interrupt-cells = <1>;
77 #size-cells = <2>;
78 #address-cells = <3>;
79 device_type = "pci";
80 interrupts = <26 2 0 0>;
81 interrupt-map-mask = <0xf800 0 0 7>;
82 interrupt-map = <
83 /* IDSEL 0x0 */
84 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
85 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
86 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
87 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
88 >;
89 };
90};
91
92&soc {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 device_type = "soc";
96 compatible = "fsl,mpc8548-immr", "simple-bus";
97 bus-frequency = <0>; // Filled out by uboot.
98
99 ecm-law@0 {
100 compatible = "fsl,ecm-law";
101 reg = <0x0 0x1000>;
102 fsl,num-laws = <10>;
103 };
104
105 ecm@1000 {
106 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
107 reg = <0x1000 0x1000>;
108 interrupts = <17 2 0 0>;
109 };
110
111 memory-controller@2000 {
112 compatible = "fsl,mpc8548-memory-controller";
113 reg = <0x2000 0x1000>;
114 interrupts = <18 2 0 0>;
115 };
116
117/include/ "pq3-i2c-0.dtsi"
118/include/ "pq3-i2c-1.dtsi"
119/include/ "pq3-duart-0.dtsi"
120
121 L2: l2-cache-controller@20000 {
122 compatible = "fsl,mpc8548-l2-cache-controller";
123 reg = <0x20000 0x1000>;
124 cache-line-size = <32>; // 32 bytes
125 cache-size = <0x80000>; // L2, 512K
126 interrupts = <16 2 0 0>;
127 };
128
129/include/ "pq3-dma-0.dtsi"
130/include/ "pq3-etsec1-0.dtsi"
131/include/ "pq3-etsec1-1.dtsi"
132/include/ "pq3-etsec1-2.dtsi"
133/include/ "pq3-etsec1-3.dtsi"
134
135/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi"
137
138 global-utilities@e0000 {
139 compatible = "fsl,mpc8548-guts";
140 reg = <0xe0000 0x1000>;
141 fsl,has-rstcr;
142 };
143};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
new file mode 100644
index 000000000000..289f1218d755
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -0,0 +1,62 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8548";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8548@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61 };
62};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index a17a5572fb73..07b8dae0f46e 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -9,13 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8548si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS"; 16 compatible = "MPC8548CDS", "MPC85xxCDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -29,76 +27,19 @@
29 pci2 = &pci2; 27 pci2 = &pci2;
30 }; 28 };
31 29
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8548@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // 33 MHz, from uboot
44 bus-frequency = <0>; // 166 MHz
45 clock-frequency = <0>; // 825 MHz, from uboot
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory { 30 memory {
51 device_type = "memory"; 31 device_type = "memory";
52 reg = <0x0 0x8000000>; // 128M at 0x0 32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
53 }; 33 };
54 34
55 soc8548@e0000000 { 35 lbc: localbus@e0005000 {
56 #address-cells = <1>; 36 reg = <0 0xe0005000 0 0x1000>;
57 #size-cells = <1>; 37 };
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xe0000000 0x100000>;
61 bus-frequency = <0>;
62
63 ecm-law@0 {
64 compatible = "fsl,ecm-law";
65 reg = <0x0 0x1000>;
66 fsl,num-laws = <10>;
67 };
68
69 ecm@1000 {
70 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
71 reg = <0x1000 0x1000>;
72 interrupts = <17 2>;
73 interrupt-parent = <&mpic>;
74 };
75
76 memory-controller@2000 {
77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>;
81 };
82 38
83 L2: l2-cache-controller@20000 { 39 soc: soc8548@e0000000 {
84 compatible = "fsl,mpc8548-l2-cache-controller"; 40 ranges = <0 0x0 0xe0000000 0x100000>;
85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K
88 interrupt-parent = <&mpic>;
89 interrupts = <16 2>;
90 };
91 41
92 i2c@3000 { 42 i2c@3000 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <0>;
96 compatible = "fsl-i2c";
97 reg = <0x3000 0x100>;
98 interrupts = <43 2>;
99 interrupt-parent = <&mpic>;
100 dfsrr;
101
102 eeprom@50 { 43 eeprom@50 {
103 compatible = "atmel,24c64"; 44 compatible = "atmel,24c64";
104 reg = <0x50>; 45 reg = <0x50>;
@@ -116,351 +57,178 @@
116 }; 57 };
117 58
118 i2c@3100 { 59 i2c@3100 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 cell-index = <1>;
122 compatible = "fsl-i2c";
123 reg = <0x3100 0x100>;
124 interrupts = <43 2>;
125 interrupt-parent = <&mpic>;
126 dfsrr;
127
128 eeprom@50 { 60 eeprom@50 {
129 compatible = "atmel,24c64"; 61 compatible = "atmel,24c64";
130 reg = <0x50>; 62 reg = <0x50>;
131 }; 63 };
132 }; 64 };
133 65
134 dma@21300 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
138 reg = <0x21300 0x4>;
139 ranges = <0x0 0x21100 0x200>;
140 cell-index = <0>;
141 dma-channel@0 {
142 compatible = "fsl,mpc8548-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x0 0x80>;
145 cell-index = <0>;
146 interrupt-parent = <&mpic>;
147 interrupts = <20 2>;
148 };
149 dma-channel@80 {
150 compatible = "fsl,mpc8548-dma-channel",
151 "fsl,eloplus-dma-channel";
152 reg = <0x80 0x80>;
153 cell-index = <1>;
154 interrupt-parent = <&mpic>;
155 interrupts = <21 2>;
156 };
157 dma-channel@100 {
158 compatible = "fsl,mpc8548-dma-channel",
159 "fsl,eloplus-dma-channel";
160 reg = <0x100 0x80>;
161 cell-index = <2>;
162 interrupt-parent = <&mpic>;
163 interrupts = <22 2>;
164 };
165 dma-channel@180 {
166 compatible = "fsl,mpc8548-dma-channel",
167 "fsl,eloplus-dma-channel";
168 reg = <0x180 0x80>;
169 cell-index = <3>;
170 interrupt-parent = <&mpic>;
171 interrupts = <23 2>;
172 };
173 };
174
175 enet0: ethernet@24000 { 66 enet0: ethernet@24000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 cell-index = <0>;
179 device_type = "network";
180 model = "eTSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 ranges = <0x0 0x24000 0x1000>;
184 local-mac-address = [ 00 00 00 00 00 00 ];
185 interrupts = <29 2 30 2 34 2>;
186 interrupt-parent = <&mpic>;
187 tbi-handle = <&tbi0>; 67 tbi-handle = <&tbi0>;
188 phy-handle = <&phy0>; 68 phy-handle = <&phy0>;
69 };
189 70
190 mdio@520 { 71 mdio@24520 {
191 #address-cells = <1>; 72 phy0: ethernet-phy@0 {
192 #size-cells = <0>; 73 interrupts = <5 1 0 0>;
193 compatible = "fsl,gianfar-mdio"; 74 reg = <0x0>;
194 reg = <0x520 0x20>; 75 device_type = "ethernet-phy";
195 76 };
196 phy0: ethernet-phy@0 { 77 phy1: ethernet-phy@1 {
197 interrupt-parent = <&mpic>; 78 interrupts = <5 1 0 0>;
198 interrupts = <5 1>; 79 reg = <0x1>;
199 reg = <0x0>; 80 device_type = "ethernet-phy";
200 device_type = "ethernet-phy"; 81 };
201 }; 82 phy2: ethernet-phy@2 {
202 phy1: ethernet-phy@1 { 83 interrupts = <5 1 0 0>;
203 interrupt-parent = <&mpic>; 84 reg = <0x2>;
204 interrupts = <5 1>; 85 device_type = "ethernet-phy";
205 reg = <0x1>; 86 };
206 device_type = "ethernet-phy"; 87 phy3: ethernet-phy@3 {
207 }; 88 interrupts = <5 1 0 0>;
208 phy2: ethernet-phy@2 { 89 reg = <0x3>;
209 interrupt-parent = <&mpic>; 90 device_type = "ethernet-phy";
210 interrupts = <5 1>; 91 };
211 reg = <0x2>; 92 tbi0: tbi-phy@11 {
212 device_type = "ethernet-phy"; 93 reg = <0x11>;
213 }; 94 device_type = "tbi-phy";
214 phy3: ethernet-phy@3 {
215 interrupt-parent = <&mpic>;
216 interrupts = <5 1>;
217 reg = <0x3>;
218 device_type = "ethernet-phy";
219 };
220 tbi0: tbi-phy@11 {
221 reg = <0x11>;
222 device_type = "tbi-phy";
223 };
224 }; 95 };
225 }; 96 };
226 97
227 enet1: ethernet@25000 { 98 enet1: ethernet@25000 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 cell-index = <1>;
231 device_type = "network";
232 model = "eTSEC";
233 compatible = "gianfar";
234 reg = <0x25000 0x1000>;
235 ranges = <0x0 0x25000 0x1000>;
236 local-mac-address = [ 00 00 00 00 00 00 ];
237 interrupts = <35 2 36 2 40 2>;
238 interrupt-parent = <&mpic>;
239 tbi-handle = <&tbi1>; 99 tbi-handle = <&tbi1>;
240 phy-handle = <&phy1>; 100 phy-handle = <&phy1>;
101 };
241 102
242 mdio@520 { 103 mdio@25520 {
243 #address-cells = <1>; 104 tbi1: tbi-phy@11 {
244 #size-cells = <0>; 105 reg = <0x11>;
245 compatible = "fsl,gianfar-tbi"; 106 device_type = "tbi-phy";
246 reg = <0x520 0x20>;
247
248 tbi1: tbi-phy@11 {
249 reg = <0x11>;
250 device_type = "tbi-phy";
251 };
252 }; 107 };
253 }; 108 };
254 109
255 enet2: ethernet@26000 { 110 enet2: ethernet@26000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 cell-index = <2>;
259 device_type = "network";
260 model = "eTSEC";
261 compatible = "gianfar";
262 reg = <0x26000 0x1000>;
263 ranges = <0x0 0x26000 0x1000>;
264 local-mac-address = [ 00 00 00 00 00 00 ];
265 interrupts = <31 2 32 2 33 2>;
266 interrupt-parent = <&mpic>;
267 tbi-handle = <&tbi2>; 111 tbi-handle = <&tbi2>;
268 phy-handle = <&phy2>; 112 phy-handle = <&phy2>;
113 };
269 114
270 mdio@520 { 115 mdio@26520 {
271 #address-cells = <1>; 116 tbi2: tbi-phy@11 {
272 #size-cells = <0>; 117 reg = <0x11>;
273 compatible = "fsl,gianfar-tbi"; 118 device_type = "tbi-phy";
274 reg = <0x520 0x20>;
275
276 tbi2: tbi-phy@11 {
277 reg = <0x11>;
278 device_type = "tbi-phy";
279 };
280 }; 119 };
281 }; 120 };
282 121
283 enet3: ethernet@27000 { 122 enet3: ethernet@27000 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 cell-index = <3>;
287 device_type = "network";
288 model = "eTSEC";
289 compatible = "gianfar";
290 reg = <0x27000 0x1000>;
291 ranges = <0x0 0x27000 0x1000>;
292 local-mac-address = [ 00 00 00 00 00 00 ];
293 interrupts = <37 2 38 2 39 2>;
294 interrupt-parent = <&mpic>;
295 tbi-handle = <&tbi3>; 123 tbi-handle = <&tbi3>;
296 phy-handle = <&phy3>; 124 phy-handle = <&phy3>;
297
298 mdio@520 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "fsl,gianfar-tbi";
302 reg = <0x520 0x20>;
303
304 tbi3: tbi-phy@11 {
305 reg = <0x11>;
306 device_type = "tbi-phy";
307 };
308 };
309 };
310
311 serial0: serial@4500 {
312 cell-index = <0>;
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>; // reg base, size
316 clock-frequency = <0>; // should we fill in in uboot?
317 interrupts = <42 2>;
318 interrupt-parent = <&mpic>;
319 };
320
321 serial1: serial@4600 {
322 cell-index = <1>;
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>; // reg base, size
326 clock-frequency = <0>; // should we fill in in uboot?
327 interrupts = <42 2>;
328 interrupt-parent = <&mpic>;
329 }; 125 };
330 126
331 global-utilities@e0000 { //global utilities reg 127 mdio@27520 {
332 compatible = "fsl,mpc8548-guts"; 128 tbi3: tbi-phy@11 {
333 reg = <0xe0000 0x1000>; 129 reg = <0x11>;
334 fsl,has-rstcr; 130 device_type = "tbi-phy";
335 }; 131 };
336
337 crypto@30000 {
338 compatible = "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000>;
340 interrupts = <45 2>;
341 interrupt-parent = <&mpic>;
342 fsl,num-channels = <4>;
343 fsl,channel-fifo-len = <24>;
344 fsl,exec-units-mask = <0xfe>;
345 fsl,descriptor-types-mask = <0x12b0ebf>;
346 };
347
348 mpic: pic@40000 {
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <0x40000 0x40000>;
353 compatible = "chrp,open-pic";
354 device_type = "open-pic";
355 }; 132 };
356 }; 133 };
357 134
358 pci0: pci@e0008000 { 135 pci0: pci@e0008000 {
136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
359 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 interrupt-map = < 141 interrupt-map = <
361 /* IDSEL 0x4 (PCIX Slot 2) */ 142 /* IDSEL 0x4 (PCIX Slot 2) */
362 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
363 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
364 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
365 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
366 147
367 /* IDSEL 0x5 (PCIX Slot 3) */ 148 /* IDSEL 0x5 (PCIX Slot 3) */
368 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
369 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
370 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
371 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
372 153
373 /* IDSEL 0x6 (PCIX Slot 4) */ 154 /* IDSEL 0x6 (PCIX Slot 4) */
374 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
375 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
376 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
377 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
378 159
379 /* IDSEL 0x8 (PCIX Slot 5) */ 160 /* IDSEL 0x8 (PCIX Slot 5) */
380 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
381 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
382 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
383 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
384 165
385 /* IDSEL 0xC (Tsi310 bridge) */ 166 /* IDSEL 0xC (Tsi310 bridge) */
386 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
387 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
388 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
389 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
390 171
391 /* IDSEL 0x14 (Slot 2) */ 172 /* IDSEL 0x14 (Slot 2) */
392 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
393 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
394 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
395 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
396 177
397 /* IDSEL 0x15 (Slot 3) */ 178 /* IDSEL 0x15 (Slot 3) */
398 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
399 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
400 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
401 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
402 183
403 /* IDSEL 0x16 (Slot 4) */ 184 /* IDSEL 0x16 (Slot 4) */
404 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
405 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
406 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
407 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
408 189
409 /* IDSEL 0x18 (Slot 5) */ 190 /* IDSEL 0x18 (Slot 5) */
410 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
411 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
412 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
413 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
414 195
415 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
416 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
417 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
418 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
419 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>; 200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
420
421 interrupt-parent = <&mpic>;
422 interrupts = <24 2>;
423 bus-range = <0 0>;
424 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
425 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <66666666>;
427 #interrupt-cells = <1>;
428 #size-cells = <2>;
429 #address-cells = <3>;
430 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
432 device_type = "pci";
433 201
434 pci_bridge@1c { 202 pci_bridge@1c {
435 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
436 interrupt-map = < 204 interrupt-map = <
437 205
438 /* IDSEL 0x00 (PrPMC Site) */ 206 /* IDSEL 0x00 (PrPMC Site) */
439 0000 0x0 0x0 0x1 &mpic 0x0 0x1 207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
440 0000 0x0 0x0 0x2 &mpic 0x1 0x1 208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
441 0000 0x0 0x0 0x3 &mpic 0x2 0x1 209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
442 0000 0x0 0x0 0x4 &mpic 0x3 0x1 210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
443 211
444 /* IDSEL 0x04 (VIA chip) */ 212 /* IDSEL 0x04 (VIA chip) */
445 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
446 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
447 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
448 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
449 217
450 /* IDSEL 0x05 (8139) */ 218 /* IDSEL 0x05 (8139) */
451 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
452 220
453 /* IDSEL 0x06 (Slot 6) */ 221 /* IDSEL 0x06 (Slot 6) */
454 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
455 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
456 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
457 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
458 226
459 /* IDESL 0x07 (Slot 7) */ 227 /* IDESL 0x07 (Slot 7) */
460 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
461 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
462 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
463 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>; 231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
464 232
465 reg = <0xe000 0x0 0x0 0x0 0x0>; 233 reg = <0xe000 0x0 0x0 0x0 0x0>;
466 #interrupt-cells = <1>; 234 #interrupt-cells = <1>;
@@ -492,7 +260,7 @@
492 #address-cells = <0>; 260 #address-cells = <0>;
493 #interrupt-cells = <2>; 261 #interrupt-cells = <2>;
494 compatible = "chrp,iic"; 262 compatible = "chrp,iic";
495 interrupts = <0 1>; 263 interrupts = <0 1 0 0>;
496 interrupt-parent = <&mpic>; 264 interrupt-parent = <&mpic>;
497 }; 265 };
498 266
@@ -505,56 +273,25 @@
505 }; 273 };
506 274
507 pci1: pci@e0009000 { 275 pci1: pci@e0009000 {
276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
508 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
509 interrupt-map = < 281 interrupt-map = <
510 282
511 /* IDSEL 0x15 */ 283 /* IDSEL 0x15 */
512 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
513 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
514 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
515 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>; 287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
516
517 interrupt-parent = <&mpic>;
518 interrupts = <25 2>;
519 bus-range = <0 0>;
520 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
521 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
522 clock-frequency = <66666666>;
523 #interrupt-cells = <1>;
524 #size-cells = <2>;
525 #address-cells = <3>;
526 reg = <0xe0009000 0x1000>;
527 compatible = "fsl,mpc8540-pci";
528 device_type = "pci";
529 }; 288 };
530 289
531 pci2: pcie@e000a000 { 290 pci2: pcie@e000a000 {
532 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 291 reg = <0 0xe000a000 0 0x1000>;
533 interrupt-map = < 292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
534 293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
535 /* IDSEL 0x0 (PEX) */
536 00000 0x0 0x0 0x1 &mpic 0x0 0x1
537 00000 0x0 0x0 0x2 &mpic 0x1 0x1
538 00000 0x0 0x0 0x3 &mpic 0x2 0x1
539 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
540
541 interrupt-parent = <&mpic>;
542 interrupts = <26 2>;
543 bus-range = <0 255>;
544 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
545 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
546 clock-frequency = <33333333>;
547 #interrupt-cells = <1>;
548 #size-cells = <2>;
549 #address-cells = <3>;
550 reg = <0xe000a000 0x1000>;
551 compatible = "fsl,mpc8548-pcie";
552 device_type = "pci";
553 pcie@0 { 294 pcie@0 {
554 reg = <0x0 0x0 0x0 0x0 0x0>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 ranges = <0x2000000 0x0 0xa0000000 295 ranges = <0x2000000 0x0 0xa0000000
559 0x2000000 0x0 0xa0000000 296 0x2000000 0x0 0xa0000000
560 0x0 0x20000000 297 0x0 0x20000000
@@ -565,3 +302,5 @@
565 }; 302 };
566 }; 303 };
567}; 304};
305
306/include/ "fsl/mpc8548si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 10:32:40 -0400