diff options
author | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2014-10-28 10:35:18 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-03-03 08:34:15 -0500 |
commit | 534f4364f9baa14c8c1431c0584cf5a291d09d3c (patch) | |
tree | afffa1fdf9ee2b784bfc91ccf6ead796a197831e | |
parent | 9369fe012d06c4a8775984609bc068e85bfeec8f (diff) |
[media] lgdt3306a: Break long lines
Fix most of checkpatch warnings like:
WARNING: line over 80 characters
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
-rw-r--r-- | drivers/media/dvb-frontends/lgdt3306a.c | 134 |
1 files changed, 91 insertions, 43 deletions
diff --git a/drivers/media/dvb-frontends/lgdt3306a.c b/drivers/media/dvb-frontends/lgdt3306a.c index ad483be1b64e..4e0cf443b9ff 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.c +++ b/drivers/media/dvb-frontends/lgdt3306a.c | |||
@@ -220,13 +220,17 @@ static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state, | |||
220 | int ret; | 220 | int ret; |
221 | 221 | ||
222 | dbg_info("(%d)\n", mode); | 222 | dbg_info("(%d)\n", mode); |
223 | /* transport packet format */ | 223 | /* transport packet format - TPSENB=0x80 */ |
224 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */ | 224 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, |
225 | mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0); | ||
225 | if (lg_chkerr(ret)) | 226 | if (lg_chkerr(ret)) |
226 | goto fail; | 227 | goto fail; |
227 | 228 | ||
228 | /* start of packet signal duration */ | 229 | /* |
229 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */ | 230 | * start of packet signal duration |
231 | * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration | ||
232 | */ | ||
233 | ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); | ||
230 | if (lg_chkerr(ret)) | 234 | if (lg_chkerr(ret)) |
231 | goto fail; | 235 | goto fail; |
232 | 236 | ||
@@ -285,17 +289,23 @@ static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state, | |||
285 | ret = lgdt3306a_read_reg(state, 0x0070, &val); | 289 | ret = lgdt3306a_read_reg(state, 0x0070, &val); |
286 | if (lg_chkerr(ret)) | 290 | if (lg_chkerr(ret)) |
287 | goto fail; | 291 | goto fail; |
288 | val &= ~0xa8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */ | 292 | /* |
293 | * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, | ||
294 | * TPDATAOUTEN=0x08 | ||
295 | */ | ||
296 | val &= ~0xa8; | ||
289 | ret = lgdt3306a_write_reg(state, 0x0070, val); | 297 | ret = lgdt3306a_write_reg(state, 0x0070, val); |
290 | if (lg_chkerr(ret)) | 298 | if (lg_chkerr(ret)) |
291 | goto fail; | 299 | goto fail; |
292 | 300 | ||
293 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */ | 301 | /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */ |
302 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); | ||
294 | if (lg_chkerr(ret)) | 303 | if (lg_chkerr(ret)) |
295 | goto fail; | 304 | goto fail; |
296 | 305 | ||
297 | } else { | 306 | } else { |
298 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */ | 307 | /* enable IFAGC pin */ |
308 | ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); | ||
299 | if (lg_chkerr(ret)) | 309 | if (lg_chkerr(ret)) |
300 | goto fail; | 310 | goto fail; |
301 | 311 | ||
@@ -331,20 +341,24 @@ static int lgdt3306a_power(struct lgdt3306a_state *state, | |||
331 | dbg_info("(%d)\n", mode); | 341 | dbg_info("(%d)\n", mode); |
332 | 342 | ||
333 | if (mode == 0) { | 343 | if (mode == 0) { |
334 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */ | 344 | /* into reset */ |
345 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); | ||
335 | if (lg_chkerr(ret)) | 346 | if (lg_chkerr(ret)) |
336 | goto fail; | 347 | goto fail; |
337 | 348 | ||
338 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */ | 349 | /* power down */ |
350 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); | ||
339 | if (lg_chkerr(ret)) | 351 | if (lg_chkerr(ret)) |
340 | goto fail; | 352 | goto fail; |
341 | 353 | ||
342 | } else { | 354 | } else { |
343 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */ | 355 | /* out of reset */ |
356 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); | ||
344 | if (lg_chkerr(ret)) | 357 | if (lg_chkerr(ret)) |
345 | goto fail; | 358 | goto fail; |
346 | 359 | ||
347 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */ | 360 | /* power up */ |
361 | ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); | ||
348 | if (lg_chkerr(ret)) | 362 | if (lg_chkerr(ret)) |
349 | goto fail; | 363 | goto fail; |
350 | } | 364 | } |
@@ -658,8 +672,8 @@ static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state, | |||
658 | 672 | ||
659 | dbg_info("(%d)\n", enabled); | 673 | dbg_info("(%d)\n", enabled); |
660 | 674 | ||
661 | /* 0=Manual 1=Auto(QAM only) */ | 675 | /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */ |
662 | ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */ | 676 | ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled); |
663 | return ret; | 677 | return ret; |
664 | } | 678 | } |
665 | 679 | ||
@@ -671,17 +685,22 @@ static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state, | |||
671 | 685 | ||
672 | dbg_info("(%d)\n", inversion); | 686 | dbg_info("(%d)\n", inversion); |
673 | #if 0 | 687 | #if 0 |
674 | /* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */ | 688 | /* |
689 | * FGR - spectral_inversion defaults already set for VSB and QAM; | ||
690 | * can enable later if desired | ||
691 | */ | ||
675 | 692 | ||
676 | ret = lgdt3306a_set_inversion(state, inversion); | 693 | ret = lgdt3306a_set_inversion(state, inversion); |
677 | 694 | ||
678 | switch (p->modulation) { | 695 | switch (p->modulation) { |
679 | case VSB_8: | 696 | case VSB_8: |
680 | ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */ | 697 | /* Manual only for VSB */ |
698 | ret = lgdt3306a_set_inversion_auto(state, 0); | ||
681 | break; | 699 | break; |
682 | case QAM_64: | 700 | case QAM_64: |
683 | case QAM_256: | 701 | case QAM_256: |
684 | ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */ | 702 | /* Auto ok for QAM */ |
703 | ret = lgdt3306a_set_inversion_auto(state, 1); | ||
685 | break; | 704 | break; |
686 | default: | 705 | default: |
687 | ret = -EINVAL; | 706 | ret = -EINVAL; |
@@ -711,7 +730,8 @@ static int lgdt3306a_set_if(struct lgdt3306a_state *state, | |||
711 | 730 | ||
712 | switch (if_freq_khz) { | 731 | switch (if_freq_khz) { |
713 | default: | 732 | default: |
714 | pr_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz); | 733 | pr_warn("IF=%d KHz is not supportted, 3250 assumed\n", |
734 | if_freq_khz); | ||
715 | /* fallthrough */ | 735 | /* fallthrough */ |
716 | case 3250: /* 3.25Mhz */ | 736 | case 3250: /* 3.25Mhz */ |
717 | nco1 = 0x34; | 737 | nco1 = 0x34; |
@@ -758,7 +778,8 @@ static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | |||
758 | } | 778 | } |
759 | dbg_info("(%d)\n", enable); | 779 | dbg_info("(%d)\n", enable); |
760 | 780 | ||
761 | return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */ | 781 | /* NI2CRPTEN=0x80 */ |
782 | return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); | ||
762 | } | 783 | } |
763 | 784 | ||
764 | static int lgdt3306a_sleep(struct lgdt3306a_state *state) | 785 | static int lgdt3306a_sleep(struct lgdt3306a_state *state) |
@@ -810,22 +831,30 @@ static int lgdt3306a_init(struct dvb_frontend *fe) | |||
810 | goto fail; | 831 | goto fail; |
811 | 832 | ||
812 | /* 4. Peak-to-peak voltage of ADC input signal */ | 833 | /* 4. Peak-to-peak voltage of ADC input signal */ |
813 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */ | 834 | |
835 | /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */ | ||
836 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); | ||
814 | if (lg_chkerr(ret)) | 837 | if (lg_chkerr(ret)) |
815 | goto fail; | 838 | goto fail; |
816 | 839 | ||
817 | /* 5. ADC output data capture clock phase */ | 840 | /* 5. ADC output data capture clock phase */ |
818 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */ | 841 | |
842 | /* 0=same phase as ADC clock */ | ||
843 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); | ||
819 | if (lg_chkerr(ret)) | 844 | if (lg_chkerr(ret)) |
820 | goto fail; | 845 | goto fail; |
821 | 846 | ||
822 | /* 5a. ADC sampling clock source */ | 847 | /* 5a. ADC sampling clock source */ |
823 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */ | 848 | |
849 | /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */ | ||
850 | ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); | ||
824 | if (lg_chkerr(ret)) | 851 | if (lg_chkerr(ret)) |
825 | goto fail; | 852 | goto fail; |
826 | 853 | ||
827 | /* 6. Automatic PLL set */ | 854 | /* 6. Automatic PLL set */ |
828 | ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */ | 855 | |
856 | /* PLLSETAUTO=0x40; 0=off */ | ||
857 | ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); | ||
829 | if (lg_chkerr(ret)) | 858 | if (lg_chkerr(ret)) |
830 | goto fail; | 859 | goto fail; |
831 | 860 | ||
@@ -980,7 +1009,7 @@ static int lgdt3306a_set_parameters(struct dvb_frontend *fe) | |||
980 | goto fail; | 1009 | goto fail; |
981 | 1010 | ||
982 | ret = lgdt3306a_spectral_inversion(state, p, | 1011 | ret = lgdt3306a_spectral_inversion(state, p, |
983 | state->cfg->spectral_inversion ? 1 : 0); | 1012 | state->cfg->spectral_inversion ? 1 : 0); |
984 | if (lg_chkerr(ret)) | 1013 | if (lg_chkerr(ret)) |
985 | goto fail; | 1014 | goto fail; |
986 | 1015 | ||
@@ -1015,7 +1044,8 @@ static int lgdt3306a_get_frontend(struct dvb_frontend *fe) | |||
1015 | struct lgdt3306a_state *state = fe->demodulator_priv; | 1044 | struct lgdt3306a_state *state = fe->demodulator_priv; |
1016 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | 1045 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1017 | 1046 | ||
1018 | dbg_info("(%u, %d)\n", state->current_frequency, state->current_modulation); | 1047 | dbg_info("(%u, %d)\n", |
1048 | state->current_frequency, state->current_modulation); | ||
1019 | 1049 | ||
1020 | p->modulation = state->current_modulation; | 1050 | p->modulation = state->current_modulation; |
1021 | p->frequency = state->current_frequency; | 1051 | p->frequency = state->current_frequency; |
@@ -1071,7 +1101,9 @@ static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state) | |||
1071 | if (ret) | 1101 | if (ret) |
1072 | return ret; | 1102 | return ret; |
1073 | val &= 0xf8; | 1103 | val &= 0xf8; |
1074 | if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) { | 1104 | if ((snrRef > 18) && (maxPowerMan > 0x68) |
1105 | && (nCombDet == 0x01) | ||
1106 | && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) { | ||
1075 | /* SNR is over 18dB and no ghosting */ | 1107 | /* SNR is over 18dB and no ghosting */ |
1076 | val |= 0x00; /* final bandwidth = 0 */ | 1108 | val |= 0x00; /* final bandwidth = 0 */ |
1077 | } else { | 1109 | } else { |
@@ -1104,7 +1136,8 @@ static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state) | |||
1104 | return ret; | 1136 | return ret; |
1105 | } | 1137 | } |
1106 | 1138 | ||
1107 | static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state) | 1139 | static enum lgdt3306a_modulation |
1140 | lgdt3306a_check_oper_mode(struct lgdt3306a_state *state) | ||
1108 | { | 1141 | { |
1109 | u8 val = 0; | 1142 | u8 val = 0; |
1110 | int ret; | 1143 | int ret; |
@@ -1134,8 +1167,9 @@ err: | |||
1134 | return LG3306_UNKNOWN_MODE; | 1167 | return LG3306_UNKNOWN_MODE; |
1135 | } | 1168 | } |
1136 | 1169 | ||
1137 | static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state, | 1170 | static enum lgdt3306a_lock_status |
1138 | enum lgdt3306a_lock_check whatLock) | 1171 | lgdt3306a_check_lock_status(struct lgdt3306a_state *state, |
1172 | enum lgdt3306a_lock_check whatLock) | ||
1139 | { | 1173 | { |
1140 | u8 val = 0; | 1174 | u8 val = 0; |
1141 | int ret; | 1175 | int ret; |
@@ -1219,7 +1253,8 @@ static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_s | |||
1219 | return lockStatus; | 1253 | return lockStatus; |
1220 | } | 1254 | } |
1221 | 1255 | ||
1222 | static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state) | 1256 | static enum lgdt3306a_neverlock_status |
1257 | lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state) | ||
1223 | { | 1258 | { |
1224 | u8 val = 0; | 1259 | u8 val = 0; |
1225 | int ret; | 1260 | int ret; |
@@ -1267,7 +1302,8 @@ static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state) | |||
1267 | snrRef, mainStrong, aiccrejStatus, currChDiffACQ); | 1302 | snrRef, mainStrong, aiccrejStatus, currChDiffACQ); |
1268 | 1303 | ||
1269 | #if 0 | 1304 | #if 0 |
1270 | if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */ | 1305 | /* Dynamic ghost exists */ |
1306 | if ((mainStrong == 0) && (currChDiffACQ > 0x70)) | ||
1271 | #endif | 1307 | #endif |
1272 | if (mainStrong == 0) { | 1308 | if (mainStrong == 0) { |
1273 | ret = lgdt3306a_read_reg(state, 0x2135, &val); | 1309 | ret = lgdt3306a_read_reg(state, 0x2135, &val); |
@@ -1317,7 +1353,8 @@ static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state) | |||
1317 | return 0; | 1353 | return 0; |
1318 | } | 1354 | } |
1319 | 1355 | ||
1320 | static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state) | 1356 | static enum lgdt3306a_lock_status |
1357 | lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state) | ||
1321 | { | 1358 | { |
1322 | enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK; | 1359 | enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK; |
1323 | int i; | 1360 | int i; |
@@ -1325,7 +1362,8 @@ static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_stat | |||
1325 | for (i = 0; i < 2; i++) { | 1362 | for (i = 0; i < 2; i++) { |
1326 | msleep(30); | 1363 | msleep(30); |
1327 | 1364 | ||
1328 | syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK); | 1365 | syncLockStatus = lgdt3306a_check_lock_status(state, |
1366 | LG3306_SYNC_LOCK); | ||
1329 | 1367 | ||
1330 | if (syncLockStatus == LG3306_LOCK) { | 1368 | if (syncLockStatus == LG3306_LOCK) { |
1331 | dbg_info("locked(%d)\n", i); | 1369 | dbg_info("locked(%d)\n", i); |
@@ -1336,7 +1374,8 @@ static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_stat | |||
1336 | return LG3306_UNLOCK; | 1374 | return LG3306_UNLOCK; |
1337 | } | 1375 | } |
1338 | 1376 | ||
1339 | static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state) | 1377 | static enum lgdt3306a_lock_status |
1378 | lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state) | ||
1340 | { | 1379 | { |
1341 | enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK; | 1380 | enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK; |
1342 | int i; | 1381 | int i; |
@@ -1344,7 +1383,8 @@ static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state | |||
1344 | for (i = 0; i < 2; i++) { | 1383 | for (i = 0; i < 2; i++) { |
1345 | msleep(30); | 1384 | msleep(30); |
1346 | 1385 | ||
1347 | FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK); | 1386 | FECLockStatus = lgdt3306a_check_lock_status(state, |
1387 | LG3306_FEC_LOCK); | ||
1348 | 1388 | ||
1349 | if (FECLockStatus == LG3306_LOCK) { | 1389 | if (FECLockStatus == LG3306_LOCK) { |
1350 | dbg_info("locked(%d)\n", i); | 1390 | dbg_info("locked(%d)\n", i); |
@@ -1355,7 +1395,8 @@ static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state | |||
1355 | return FECLockStatus; | 1395 | return FECLockStatus; |
1356 | } | 1396 | } |
1357 | 1397 | ||
1358 | static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state) | 1398 | static enum lgdt3306a_neverlock_status |
1399 | lgdt3306a_neverlock_poll(struct lgdt3306a_state *state) | ||
1359 | { | 1400 | { |
1360 | enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL; | 1401 | enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL; |
1361 | int i; | 1402 | int i; |
@@ -1458,7 +1499,8 @@ static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state) | |||
1458 | return snr_x100; | 1499 | return snr_x100; |
1459 | } | 1500 | } |
1460 | 1501 | ||
1461 | static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state) | 1502 | static enum lgdt3306a_lock_status |
1503 | lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state) | ||
1462 | { | 1504 | { |
1463 | int ret; | 1505 | int ret; |
1464 | u8 cnt = 0; | 1506 | u8 cnt = 0; |
@@ -1488,7 +1530,8 @@ static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state | |||
1488 | return LG3306_UNLOCK; | 1530 | return LG3306_UNLOCK; |
1489 | } | 1531 | } |
1490 | 1532 | ||
1491 | static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state) | 1533 | static enum lgdt3306a_lock_status |
1534 | lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state) | ||
1492 | { | 1535 | { |
1493 | u8 cnt; | 1536 | u8 cnt; |
1494 | u8 packet_error; | 1537 | u8 packet_error; |
@@ -1632,7 +1675,7 @@ static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber) | |||
1632 | 1675 | ||
1633 | *ber = 0; | 1676 | *ber = 0; |
1634 | #if 1 | 1677 | #if 1 |
1635 | /* FGR - BUGBUG - I don't know what value is expected by dvb_core | 1678 | /* FGR - FIXME - I don't know what value is expected by dvb_core |
1636 | * what is the scale of the value?? */ | 1679 | * what is the scale of the value?? */ |
1637 | tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */ | 1680 | tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */ |
1638 | tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */ | 1681 | tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */ |
@@ -1650,7 +1693,7 @@ static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |||
1650 | 1693 | ||
1651 | *ucblocks = 0; | 1694 | *ucblocks = 0; |
1652 | #if 1 | 1695 | #if 1 |
1653 | /* FGR - BUGBUG - I don't know what value is expected by dvb_core | 1696 | /* FGR - FIXME - I don't know what value is expected by dvb_core |
1654 | * what happens when value wraps? */ | 1697 | * what happens when value wraps? */ |
1655 | *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */ | 1698 | *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */ |
1656 | dbg_info("ucblocks=%u\n", *ucblocks); | 1699 | dbg_info("ucblocks=%u\n", *ucblocks); |
@@ -1659,7 +1702,9 @@ static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |||
1659 | return 0; | 1702 | return 0; |
1660 | } | 1703 | } |
1661 | 1704 | ||
1662 | static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status) | 1705 | static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, |
1706 | unsigned int mode_flags, unsigned int *delay, | ||
1707 | fe_status_t *status) | ||
1663 | { | 1708 | { |
1664 | int ret = 0; | 1709 | int ret = 0; |
1665 | struct lgdt3306a_state *state = fe->demodulator_priv; | 1710 | struct lgdt3306a_state *state = fe->demodulator_priv; |
@@ -1761,7 +1806,8 @@ struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, | |||
1761 | if ((val & 0x74) != 0x74) { | 1806 | if ((val & 0x74) != 0x74) { |
1762 | pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); | 1807 | pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); |
1763 | #if 0 | 1808 | #if 0 |
1764 | goto fail; /* BUGBUG - re-enable when we know this is right */ | 1809 | /* FIXME - re-enable when we know this is right */ |
1810 | goto fail; | ||
1765 | #endif | 1811 | #endif |
1766 | } | 1812 | } |
1767 | ret = lgdt3306a_read_reg(state, 0x0001, &val); | 1813 | ret = lgdt3306a_read_reg(state, 0x0001, &val); |
@@ -1770,7 +1816,8 @@ struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, | |||
1770 | if ((val & 0xf6) != 0xc6) { | 1816 | if ((val & 0xf6) != 0xc6) { |
1771 | pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); | 1817 | pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); |
1772 | #if 0 | 1818 | #if 0 |
1773 | goto fail; /* BUGBUG - re-enable when we know this is right */ | 1819 | /* FIXME - re-enable when we know this is right */ |
1820 | goto fail; | ||
1774 | #endif | 1821 | #endif |
1775 | } | 1822 | } |
1776 | ret = lgdt3306a_read_reg(state, 0x0002, &val); | 1823 | ret = lgdt3306a_read_reg(state, 0x0002, &val); |
@@ -1779,7 +1826,8 @@ struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, | |||
1779 | if ((val & 0x73) != 0x03) { | 1826 | if ((val & 0x73) != 0x03) { |
1780 | pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); | 1827 | pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); |
1781 | #if 0 | 1828 | #if 0 |
1782 | goto fail; /* BUGBUG - re-enable when we know this is right */ | 1829 | /* FIXME - re-enable when we know this is right */ |
1830 | goto fail; | ||
1783 | #endif | 1831 | #endif |
1784 | } | 1832 | } |
1785 | 1833 | ||