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authorJiang Liu <jiang.liu@huawei.com>2012-07-24 05:20:32 -0400
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 12:11:16 -0400
commit532c5f69e223ec846511fa4a14fa1fc8bca142a2 (patch)
treed5b48d0a43ac5ea015074ed2a6add53cfea480ac
parent5cdaaf8a11ba34fb08877bc1982d6d54b29bb8f4 (diff)
et131x: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify et131x driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/staging/et131x/et131x.c19
1 files changed, 5 insertions, 14 deletions
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 029725c89e58..49553f88c7b3 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -3995,16 +3995,14 @@ static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3995static int et131x_pci_init(struct et131x_adapter *adapter, 3995static int et131x_pci_init(struct et131x_adapter *adapter,
3996 struct pci_dev *pdev) 3996 struct pci_dev *pdev)
3997{ 3997{
3998 int cap = pci_pcie_cap(pdev);
3999 u16 max_payload; 3998 u16 max_payload;
4000 u16 ctl;
4001 int i, rc; 3999 int i, rc;
4002 4000
4003 rc = et131x_init_eeprom(adapter); 4001 rc = et131x_init_eeprom(adapter);
4004 if (rc < 0) 4002 if (rc < 0)
4005 goto out; 4003 goto out;
4006 4004
4007 if (!cap) { 4005 if (!pci_is_pcie(pdev)) {
4008 dev_err(&pdev->dev, "Missing PCIe capabilities\n"); 4006 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
4009 goto err_out; 4007 goto err_out;
4010 } 4008 }
@@ -4012,7 +4010,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
4012 /* Let's set up the PORT LOGIC Register. First we need to know what 4010 /* Let's set up the PORT LOGIC Register. First we need to know what
4013 * the max_payload_size is 4011 * the max_payload_size is
4014 */ 4012 */
4015 if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCAP, &max_payload)) { 4013 if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
4016 dev_err(&pdev->dev, 4014 dev_err(&pdev->dev,
4017 "Could not read PCI config space for Max Payload Size\n"); 4015 "Could not read PCI config space for Max Payload Size\n");
4018 goto err_out; 4016 goto err_out;
@@ -4049,17 +4047,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
4049 } 4047 }
4050 4048
4051 /* Change the max read size to 2k */ 4049 /* Change the max read size to 2k */
4052 if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl)) { 4050 if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
4051 PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
4053 dev_err(&pdev->dev, 4052 dev_err(&pdev->dev,
4054 "Could not read PCI config space for Max read size\n"); 4053 "Couldn't change PCI config space for Max read size\n");
4055 goto err_out;
4056 }
4057
4058 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | (0x04 << 12);
4059
4060 if (pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl)) {
4061 dev_err(&pdev->dev,
4062 "Could not write PCI config space for Max read size\n");
4063 goto err_out; 4054 goto err_out;
4064 } 4055 }
4065 4056