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authorDaniel Pieczko <dpieczko@solarflare.com>2014-04-01 08:10:34 -0400
committerDavid S. Miller <davem@davemloft.net>2014-04-01 16:25:51 -0400
commit52ad762b85ed7947ec9eff6b036eb985352f6874 (patch)
treeeeb702d106b39d7eea57cbd425713f2767ba319b
parente9d8b2c2968499c1f96563e6522c56958d5a1d0d (diff)
Call efx_set_channels() before efx->type->dimension_resources()
When using the "separate_tx_channels=1" module parameter, the TX queues are initially numbered starting from the first TX-only channel number (after all the RX-only channels). efx_set_channels() renumbers the queues so that they are indexed from zero. On EF10, the TX queues need to be relabelled in this way before calling the dimension_resources NIC type operation, otherwise the TX queue PIO buffers can be linked to the wrong VIs when using "separate_tx_channels=1". Added comments to explain UC/WC mappings for PIO buffers Signed-off-by: Shradha Shah <sshah@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/sfc/ef10.c7
-rw-r--r--drivers/net/ethernet/sfc/efx.c3
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/ef10.c
index 651626e133f9..21c20ea0dad0 100644
--- a/drivers/net/ethernet/sfc/ef10.c
+++ b/drivers/net/ethernet/sfc/ef10.c
@@ -565,10 +565,17 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
565 * several of each (in fact that's the only option if host 565 * several of each (in fact that's the only option if host
566 * page size is >4K). So we may allocate some extra VIs just 566 * page size is >4K). So we may allocate some extra VIs just
567 * for writing PIO buffers through. 567 * for writing PIO buffers through.
568 *
569 * The UC mapping contains (min_vis - 1) complete VIs and the
570 * first half of the next VI. Then the WC mapping begins with
571 * the second half of this last VI.
568 */ 572 */
569 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + 573 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
570 ER_DZ_TX_PIOBUF); 574 ER_DZ_TX_PIOBUF);
571 if (nic_data->n_piobufs) { 575 if (nic_data->n_piobufs) {
576 /* pio_write_vi_base rounds down to give the number of complete
577 * VIs inside the UC mapping.
578 */
572 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 579 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
573 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 580 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
574 nic_data->n_piobufs) * 581 nic_data->n_piobufs) *
diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c
index 52589f6a8beb..57b971e5e6b2 100644
--- a/drivers/net/ethernet/sfc/efx.c
+++ b/drivers/net/ethernet/sfc/efx.c
@@ -1599,6 +1599,8 @@ static int efx_probe_nic(struct efx_nic *efx)
1599 if (rc) 1599 if (rc)
1600 goto fail1; 1600 goto fail1;
1601 1601
1602 efx_set_channels(efx);
1603
1602 rc = efx->type->dimension_resources(efx); 1604 rc = efx->type->dimension_resources(efx);
1603 if (rc) 1605 if (rc)
1604 goto fail2; 1606 goto fail2;
@@ -1609,7 +1611,6 @@ static int efx_probe_nic(struct efx_nic *efx)
1609 efx->rx_indir_table[i] = 1611 efx->rx_indir_table[i] =
1610 ethtool_rxfh_indir_default(i, efx->rss_spread); 1612 ethtool_rxfh_indir_default(i, efx->rss_spread);
1611 1613
1612 efx_set_channels(efx);
1613 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1614 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1614 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1615 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1615 1616