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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 02:59:17 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 02:59:17 -0400
commit5283ecb5ccbdb90d49fce6488d3944bba63a591c (patch)
treea58e20bd532fa5f933d099bb7b5dd0637b581d33
parentd7c30c682a278abe1a52db83f69efec1a9d8f8c2 (diff)
sh: Add support for R7780RP and R7780MP boards.
This adds support for the Renesas SH7780 development boards, R7780RP and R7780MP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/Kconfig2
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/renesas/r7780rp/Kconfig14
-rw-r--r--arch/sh/boards/renesas/r7780rp/Makefile6
-rw-r--r--arch/sh/boards/renesas/r7780rp/io.c338
-rw-r--r--arch/sh/boards/renesas/r7780rp/irq.c123
-rw-r--r--arch/sh/boards/renesas/r7780rp/led.c45
-rw-r--r--arch/sh/boards/renesas/r7780rp/setup.c164
-rw-r--r--arch/sh/configs/r7780rp_defconfig1099
-rw-r--r--arch/sh/drivers/dma/Kconfig3
-rw-r--r--arch/sh/drivers/dma/dma-sh.c4
-rw-r--r--arch/sh/drivers/pci/Makefile2
-rw-r--r--arch/sh/drivers/pci/fixups-r7780rp.c39
-rw-r--r--arch/sh/drivers/pci/ops-r7780rp.c77
-rw-r--r--arch/sh/drivers/pci/pci-auto.c44
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c4
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c341
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h168
-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c6
-rw-r--r--arch/sh/tools/mach-types2
-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h3
-rw-r--r--include/asm-sh/cpu-sh4/dma-sh7780.h39
-rw-r--r--include/asm-sh/cpu-sh4/dma.h11
-rw-r--r--include/asm-sh/hs7751rvoip/hs7751rvoip.h2
-rw-r--r--include/asm-sh/irq-sh7780.h5
-rw-r--r--include/asm-sh/irq.h2
-rw-r--r--include/asm-sh/landisk/iodata_landisk.h2
-rw-r--r--include/asm-sh/r7780rp/ide.h8
-rw-r--r--include/asm-sh/r7780rp/r7780rp.h177
-rw-r--r--include/asm-sh/rts7751r2d/rts7751r2d.h2
30 files changed, 2684 insertions, 49 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index a66b9c44075f..fe982f0eba23 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -404,6 +404,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
404 404
405source "arch/sh/boards/renesas/rts7751r2d/Kconfig" 405source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
406 406
407source "arch/sh/boards/renesas/r7780rp/Kconfig"
408
407config SH_PCLK_FREQ 409config SH_PCLK_FREQ
408 int "Peripheral clock frequency (in Hz)" 410 int "Peripheral clock frequency (in Hz)"
409 default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 411 default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 65676c33822e..c143510d71fc 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -104,6 +104,7 @@ machdir-$(CONFIG_SH_HS7751RVOIP) := renesas/hs7751rvoip
104machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d 104machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d
105machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh 105machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh
106machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705 106machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705
107machdir-$(CONFIG_SH_R7780RP) := renesas/r7780rp
107machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev 108machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev
108machdir-$(CONFIG_SH_LANDISK) := landisk 109machdir-$(CONFIG_SH_LANDISK) := landisk
109machdir-$(CONFIG_SH_TITAN) := titan 110machdir-$(CONFIG_SH_TITAN) := titan
diff --git a/arch/sh/boards/renesas/r7780rp/Kconfig b/arch/sh/boards/renesas/r7780rp/Kconfig
new file mode 100644
index 000000000000..c26d9813d239
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/Kconfig
@@ -0,0 +1,14 @@
1if SH_R7780RP
2
3menu "R7780RP options"
4
5config SH_R7780MP
6 bool "R7780MP board support"
7 default y
8 help
9 Selecting this option will enable support for the mass-production
10 version of the R7780RP. If in doubt, say Y.
11
12endmenu
13
14endif
diff --git a/arch/sh/boards/renesas/r7780rp/Makefile b/arch/sh/boards/renesas/r7780rp/Makefile
new file mode 100644
index 000000000000..f1776d027978
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the R7780RP-1 specific parts of the kernel
3#
4
5obj-y := setup.o io.o irq.o
6obj-$(CONFIG_HEARTBEAT) += led.o
diff --git a/arch/sh/boards/renesas/r7780rp/io.c b/arch/sh/boards/renesas/r7780rp/io.c
new file mode 100644
index 000000000000..f73ca3f0f5a1
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/io.c
@@ -0,0 +1,338 @@
1/*
2 * linux/arch/sh/kernel/io_r7780rp.c
3 *
4 * Copyright (C) 2001 Ian da Silva, Jeremy Siegel
5 * Based largely on io_se.c.
6 *
7 * I/O routine for Renesas Solutions Highlander R7780RP-1
8 *
9 * Initial version only to support LAN access; some
10 * placeholder code from io_r7780rp.c left in with the
11 * expectation of later SuperIO and PCMCIA access.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <asm/r7780rp/r7780rp.h>
17#include <asm/addrspace.h>
18#include <asm/io.h>
19
20#include <linux/module.h>
21#include <linux/pci.h>
22#include "../../../drivers/pci/pci-sh7780.h"
23
24/*
25 * The 7780 R7780RP-1 uses the built-in PCI controller (PCIC)
26 * of the 7780 processor, and has a SuperIO accessible via the PCI.
27 * The board also includes a PCMCIA controller on its memory bus,
28 * like the other Solution Engine boards.
29 */
30
31#define SH7780_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
32#define PCIIOBR (volatile long *)PCI_REG(SH7780_PCIIOBR)
33#define PCIMBR (volatile long *)PCI_REG(SH7780_PCIMBR)
34#define PCI_IO_AREA SH7780_PCI_IO_BASE
35#define PCI_MEM_AREA SH7780_PCI_CONFIG_BASE
36
37#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7780_PCIIOBR_MASK))
38
39static inline void delay(void)
40{
41 ctrl_inw(0xa0000000);
42}
43
44static inline unsigned long port2adr(unsigned int port)
45{
46 if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
47 if (port == 0x3f6)
48 return (PA_AREA5_IO + 0x80c);
49 else
50 return (PA_AREA5_IO + 0x1000 + ((port-0x1f0) << 1));
51 else
52 maybebadio((unsigned long)port);
53
54 return port;
55}
56
57static inline unsigned long port88796l(unsigned int port, int flag)
58{
59 unsigned long addr;
60
61 if (flag)
62 addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1);
63 else
64 addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1) + 0x1000;
65
66 return addr;
67}
68
69/* The 7780 R7780RP-1 seems to have everything hooked */
70/* up pretty normally (nothing on high-bytes only...) so this */
71/* shouldn't be needed */
72static inline int shifted_port(unsigned long port)
73{
74 /* For IDE registers, value is not shifted */
75 if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
76 return 0;
77 else
78 return 1;
79}
80
81/* In case someone configures the kernel w/o PCI support: in that */
82/* scenario, don't ever bother to check for PCI-window addresses */
83
84/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */
85#if defined(CONFIG_PCI)
86#define CHECK_SH7780_PCIIO(port) \
87 ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7780_PCI_IO_SIZE)))
88#else
89#define CHECK_SH7780_PCIIO(port) (0)
90#endif
91
92#if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE)
93#define CHECK_AX88796L_PORT(port) \
94 ((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20)))
95#else
96#define CHECK_AX88796L_PORT(port) (0)
97#endif
98
99/*
100 * General outline: remap really low stuff [eventually] to SuperIO,
101 * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
102 * is mapped through the PCI IO window. Stuff with high bits (PXSEG)
103 * should be way beyond the window, and is used w/o translation for
104 * compatibility.
105 */
106u8 r7780rp_inb(unsigned long port)
107{
108 if (CHECK_AX88796L_PORT(port))
109 return ctrl_inw(port88796l(port, 0)) & 0xff;
110 else if (PXSEG(port))
111 return ctrl_inb(port);
112 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
113 return ctrl_inb(PCI_IOMAP(port));
114
115 return ctrl_inw(port2adr(port)) & 0xff;
116}
117
118u8 r7780rp_inb_p(unsigned long port)
119{
120 u8 v;
121
122 if (CHECK_AX88796L_PORT(port))
123 v = ctrl_inw(port88796l(port, 0)) & 0xff;
124 else if (PXSEG(port))
125 v = ctrl_inb(port);
126 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
127 v = ctrl_inb(PCI_IOMAP(port));
128 else
129 v = ctrl_inw(port2adr(port)) & 0xff;
130
131 delay();
132
133 return v;
134}
135
136u16 r7780rp_inw(unsigned long port)
137{
138 if (CHECK_AX88796L_PORT(port))
139 maybebadio(port);
140 else if (PXSEG(port))
141 return ctrl_inw(port);
142 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
143 return ctrl_inw(PCI_IOMAP(port));
144 else
145 maybebadio(port);
146
147 return 0;
148}
149
150u32 r7780rp_inl(unsigned long port)
151{
152 if (CHECK_AX88796L_PORT(port))
153 maybebadio(port);
154 else if (PXSEG(port))
155 return ctrl_inl(port);
156 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
157 return ctrl_inl(PCI_IOMAP(port));
158 else
159 maybebadio(port);
160
161 return 0;
162}
163
164void r7780rp_outb(u8 value, unsigned long port)
165{
166 if (CHECK_AX88796L_PORT(port))
167 ctrl_outw(value, port88796l(port, 0));
168 else if (PXSEG(port))
169 ctrl_outb(value, port);
170 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
171 ctrl_outb(value, PCI_IOMAP(port));
172 else
173 ctrl_outw(value, port2adr(port));
174}
175
176void r7780rp_outb_p(u8 value, unsigned long port)
177{
178 if (CHECK_AX88796L_PORT(port))
179 ctrl_outw(value, port88796l(port, 0));
180 else if (PXSEG(port))
181 ctrl_outb(value, port);
182 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
183 ctrl_outb(value, PCI_IOMAP(port));
184 else
185 ctrl_outw(value, port2adr(port));
186
187 delay();
188}
189
190void r7780rp_outw(u16 value, unsigned long port)
191{
192 if (CHECK_AX88796L_PORT(port))
193 maybebadio(port);
194 else if (PXSEG(port))
195 ctrl_outw(value, port);
196 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
197 ctrl_outw(value, PCI_IOMAP(port));
198 else
199 maybebadio(port);
200}
201
202void r7780rp_outl(u32 value, unsigned long port)
203{
204 if (CHECK_AX88796L_PORT(port))
205 maybebadio(port);
206 else if (PXSEG(port))
207 ctrl_outl(value, port);
208 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
209 ctrl_outl(value, PCI_IOMAP(port));
210 else
211 maybebadio(port);
212}
213
214void r7780rp_insb(unsigned long port, void *dst, unsigned long count)
215{
216 volatile u16 *p;
217 u8 *buf = dst;
218
219 if (CHECK_AX88796L_PORT(port)) {
220 p = (volatile u16 *)port88796l(port, 0);
221 while (count--)
222 *buf++ = *p & 0xff;
223 } else if (PXSEG(port)) {
224 while (count--)
225 *buf++ = *(volatile u8 *)port;
226 } else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
227 volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
228
229 while (count--)
230 *buf++ = *bp;
231 } else {
232 p = (volatile u16 *)port2adr(port);
233 while (count--)
234 *buf++ = *p & 0xff;
235 }
236}
237
238void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
239{
240 volatile u16 *p;
241 u16 *buf = dst;
242
243 if (CHECK_AX88796L_PORT(port))
244 p = (volatile u16 *)port88796l(port, 1);
245 else if (PXSEG(port))
246 p = (volatile u16 *)port;
247 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
248 p = (volatile u16 *)PCI_IOMAP(port);
249 else
250 p = (volatile u16 *)port2adr(port);
251
252 while (count--)
253 *buf++ = *p;
254}
255
256void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
257{
258 u32 *buf = dst;
259
260 if (CHECK_AX88796L_PORT(port))
261 maybebadio(port);
262 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
263 volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
264
265 while (count--)
266 *buf++ = *p;
267 } else
268 maybebadio(port);
269}
270
271void r7780rp_outsb(unsigned long port, const void *src, unsigned long count)
272{
273 volatile u16 *p;
274 const u8 *buf = src;
275
276 if (CHECK_AX88796L_PORT(port)) {
277 p = (volatile u16 *)port88796l(port, 0);
278 while (count--)
279 *p = *buf++;
280 } else if (PXSEG(port))
281 while (count--)
282 ctrl_outb(*buf++, port);
283 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
284 volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
285
286 while (count--)
287 *bp = *buf++;
288 } else {
289 p = (volatile u16 *)port2adr(port);
290 while (count--)
291 *p = *buf++;
292 }
293}
294
295void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
296{
297 volatile u16 *p;
298 const u16 *buf = src;
299
300 if (CHECK_AX88796L_PORT(port))
301 p = (volatile u16 *)port88796l(port, 1);
302 else if (PXSEG(port))
303 p = (volatile u16 *)port;
304 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
305 p = (volatile u16 *)PCI_IOMAP(port);
306 else
307 p = (volatile u16 *)port2adr(port);
308
309 while (count--)
310 *p = *buf++;
311}
312
313void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
314{
315 const u32 *buf = src;
316
317 if (CHECK_AX88796L_PORT(port))
318 maybebadio(port);
319 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
320 volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
321
322 while (count--)
323 *p = *buf++;
324 } else
325 maybebadio(port);
326}
327
328void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size)
329{
330 if (CHECK_AX88796L_PORT(port))
331 return (void __iomem *)port88796l(port, size > 1);
332 else if (PXSEG(port))
333 return (void __iomem *)port;
334 else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
335 return (void __iomem *)PCI_IOMAP(port);
336
337 return (void __iomem *)port2adr(port);
338}
diff --git a/arch/sh/boards/renesas/r7780rp/irq.c b/arch/sh/boards/renesas/r7780rp/irq.c
new file mode 100644
index 000000000000..c7b9fe6e640d
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/irq.c
@@ -0,0 +1,123 @@
1/*
2 * linux/arch/sh/boards/renesas/r7780rp/irq.c
3 *
4 * Copyright (C) 2000 Kazumoto Kojima
5 *
6 * Renesas Solutions Highlander R7780RP-1 Support.
7 *
8 * Modified for R7780RP-1 by
9 * Atom Create Engineering Co., Ltd. 2002.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15#include <asm/io.h>
16#include <asm/irq.h>
17#include <asm/r7780rp/r7780rp.h>
18
19#ifdef CONFIG_SH_R7780MP
20static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
21#else
22static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
23#endif
24
25static void enable_r7780rp_irq(unsigned int irq);
26static void disable_r7780rp_irq(unsigned int irq);
27
28/* shutdown is same as "disable" */
29#define shutdown_r7780rp_irq disable_r7780rp_irq
30
31static void ack_r7780rp_irq(unsigned int irq);
32static void end_r7780rp_irq(unsigned int irq);
33
34static unsigned int startup_r7780rp_irq(unsigned int irq)
35{
36 enable_r7780rp_irq(irq);
37 return 0; /* never anything pending */
38}
39
40static void disable_r7780rp_irq(unsigned int irq)
41{
42 unsigned long flags;
43 unsigned short val;
44 unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
45
46 /* Set the priority in IPR to 0 */
47 local_irq_save(flags);
48 val = ctrl_inw(IRLCNTR1);
49 val &= mask;
50 ctrl_outw(val, IRLCNTR1);
51 local_irq_restore(flags);
52}
53
54static void enable_r7780rp_irq(unsigned int irq)
55{
56 unsigned long flags;
57 unsigned short val;
58 unsigned short value = (0x0001 << mask_pos[irq]);
59
60 /* Set priority in IPR back to original value */
61 local_irq_save(flags);
62 val = ctrl_inw(IRLCNTR1);
63 val |= value;
64 ctrl_outw(val, IRLCNTR1);
65 local_irq_restore(flags);
66}
67
68static void ack_r7780rp_irq(unsigned int irq)
69{
70 disable_r7780rp_irq(irq);
71}
72
73static void end_r7780rp_irq(unsigned int irq)
74{
75 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
76 enable_r7780rp_irq(irq);
77}
78
79static struct hw_interrupt_type r7780rp_irq_type = {
80 .typename = "R7780RP-IRQ",
81 .startup = startup_r7780rp_irq,
82 .shutdown = shutdown_r7780rp_irq,
83 .enable = enable_r7780rp_irq,
84 .disable = disable_r7780rp_irq,
85 .ack = ack_r7780rp_irq,
86 .end = end_r7780rp_irq,
87};
88
89static void make_r7780rp_irq(unsigned int irq)
90{
91 disable_irq_nosync(irq);
92 irq_desc[irq].handler = &r7780rp_irq_type;
93 disable_r7780rp_irq(irq);
94}
95
96/*
97 * Initialize IRQ setting
98 */
99void __init init_r7780rp_IRQ(void)
100{
101 int i;
102
103 /* IRL0=PCI Slot #A
104 * IRL1=PCI Slot #B
105 * IRL2=PCI Slot #C
106 * IRL3=PCI Slot #D
107 * IRL4=CF Card
108 * IRL5=CF Card Insert
109 * IRL6=M66596
110 * IRL7=SD Card
111 * IRL8=Touch Panel
112 * IRL9=SCI
113 * IRL10=Serial
114 * IRL11=Extention #A
115 * IRL11=Extention #B
116 * IRL12=Debug LAN
117 * IRL13=Push Switch
118 * IRL14=ZiggBee IO
119 */
120
121 for (i=0; i<15; i++)
122 make_r7780rp_irq(i);
123}
diff --git a/arch/sh/boards/renesas/r7780rp/led.c b/arch/sh/boards/renesas/r7780rp/led.c
new file mode 100644
index 000000000000..9f02766b6f53
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/led.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) Atom Create Engineering Co., Ltd.
3 *
4 * May be copied or modified under the terms of GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * This file contains Renesas Solutions HIGHLANDER R7780RP-1 specific LED code.
8 */
9
10#include <linux/config.h>
11#include <linux/sched.h>
12#include <asm/io.h>
13#include <asm/r7780rp/r7780rp.h>
14
15/* Cycle the LED's in the clasic Knightriger/Sun pattern */
16void heartbeat_r7780rp(void)
17{
18 static unsigned int cnt = 0, period = 0;
19 volatile unsigned short *p = (volatile unsigned short *)PA_OBLED;
20 static unsigned bit = 0, up = 1;
21 unsigned bit_pos[] = {2, 1, 0, 3, 6, 5, 4, 7};
22
23 cnt += 1;
24 if (cnt < period)
25 return;
26
27 cnt = 0;
28
29 /* Go through the points (roughly!):
30 * f(0)=10, f(1)=16, f(2)=20, f(5)=35, f(int)->110
31 */
32 period = 110 - ((300 << FSHIFT)/((avenrun[0]/5) + (3<<FSHIFT)));
33
34 *p = 1 << bit_pos[bit];
35 if (up)
36 if (bit == 7) {
37 bit--;
38 up = 0;
39 } else
40 bit++;
41 else if (bit == 0)
42 up = 1;
43 else
44 bit--;
45}
diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/renesas/r7780rp/setup.c
new file mode 100644
index 000000000000..0e4d5e1b541c
--- /dev/null
+++ b/arch/sh/boards/renesas/r7780rp/setup.c
@@ -0,0 +1,164 @@
1/*
2 * arch/sh/boards/renesas/r7780rp/setup.c
3 *
4 * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
5 * Copyright (C) 2005, 2006 Paul Mundt
6 *
7 * Renesas Solutions Highlander R7780RP-1 Support.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <asm/machvec.h>
16#include <asm/r7780rp/r7780rp.h>
17#include <asm/clock.h>
18#include <asm/io.h>
19
20extern void heartbeat_r7780rp(void);
21extern void init_r7780rp_IRQ(void);
22
23/*
24 * The Machine Vector
25 */
26struct sh_machine_vector mv_r7780rp __initmv = {
27 .mv_nr_irqs = 109,
28
29 .mv_inb = r7780rp_inb,
30 .mv_inw = r7780rp_inw,
31 .mv_inl = r7780rp_inl,
32 .mv_outb = r7780rp_outb,
33 .mv_outw = r7780rp_outw,
34 .mv_outl = r7780rp_outl,
35
36 .mv_inb_p = r7780rp_inb_p,
37 .mv_inw_p = r7780rp_inw,
38 .mv_inl_p = r7780rp_inl,
39 .mv_outb_p = r7780rp_outb_p,
40 .mv_outw_p = r7780rp_outw,
41 .mv_outl_p = r7780rp_outl,
42
43 .mv_insb = r7780rp_insb,
44 .mv_insw = r7780rp_insw,
45 .mv_insl = r7780rp_insl,
46 .mv_outsb = r7780rp_outsb,
47 .mv_outsw = r7780rp_outsw,
48 .mv_outsl = r7780rp_outsl,
49
50 .mv_ioport_map = r7780rp_ioport_map,
51 .mv_init_irq = init_r7780rp_IRQ,
52#ifdef CONFIG_HEARTBEAT
53 .mv_heartbeat = heartbeat_r7780rp,
54#endif
55};
56ALIAS_MV(r7780rp)
57
58static struct resource m66596_usb_host_resources[] = {
59 [0] = {
60 .start = 0xa4800000,
61 .end = 0xa4ffffff,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = 6, /* irq number */
66 .end = 6,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct platform_device m66596_usb_host_device = {
72 .name = "m66596-hcd",
73 .id = 0,
74 .dev = {
75 .dma_mask = NULL, /* don't use dma */
76 .coherent_dma_mask = 0xffffffff,
77 },
78 .num_resources = ARRAY_SIZE(m66596_usb_host_resources),
79 .resource = m66596_usb_host_resources,
80};
81
82static struct platform_device *r7780rp_devices[] __initdata = {
83 &m66596_usb_host_device,
84};
85
86static int __init r7780rp_devices_setup(void)
87{
88 return platform_add_devices(r7780rp_devices,
89 ARRAY_SIZE(r7780rp_devices));
90}
91__initcall(r7780rp_devices_setup);
92
93/*
94 * Platform specific clocks
95 */
96static void ivdr_clk_enable(struct clk *clk)
97{
98 ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << 8), PA_IVDRCTL);
99}
100
101static void ivdr_clk_disable(struct clk *clk)
102{
103 ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << 8), PA_IVDRCTL);
104}
105
106static struct clk_ops ivdr_clk_ops = {
107 .enable = ivdr_clk_enable,
108 .disable = ivdr_clk_disable,
109};
110
111static struct clk ivdr_clk = {
112 .name = "ivdr_clk",
113 .ops = &ivdr_clk_ops,
114};
115
116static struct clk *r7780rp_clocks[] = {
117 &ivdr_clk,
118};
119
120const char *get_system_type(void)
121{
122 return "Highlander R7780RP-1";
123}
124
125static void r7780rp_power_off(void)
126{
127#ifdef CONFIG_SH_R7780MP
128 ctrl_outw(0x0001, PA_POFF);
129#endif
130}
131
132/*
133 * Initialize the board
134 */
135void __init platform_setup(void)
136{
137 u16 ver = ctrl_inw(PA_VERREG);
138 int i;
139
140 printk(KERN_INFO "Renesas Solutions Highlander R7780RP-1 support.\n");
141
142 printk(KERN_INFO "Board version: %d (revision %d), "
143 "FPGA version: %d (revision %d)\n",
144 (ver >> 12) & 0xf, (ver >> 8) & 0xf,
145 (ver >> 4) & 0xf, ver & 0xf);
146
147 /*
148 * Enable the important clocks right away..
149 */
150 for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) {
151 struct clk *clk = r7780rp_clocks[i];
152
153 clk_register(clk);
154 clk_enable(clk);
155 }
156
157 ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
158#ifndef CONFIG_SH_R7780MP
159 ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
160#endif
161 ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x0100, PA_IVDRCTL); /* Si13112 */
162
163 pm_power_off = r7780rp_power_off;
164}
diff --git a/arch/sh/configs/r7780rp_defconfig b/arch/sh/configs/r7780rp_defconfig
new file mode 100644
index 000000000000..d597fc571549
--- /dev/null
+++ b/arch/sh/configs/r7780rp_defconfig
@@ -0,0 +1,1099 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.15-sh
4# Sat Jan 7 19:47:53 2006
5#
6CONFIG_SUPERH=y
7CONFIG_UID16=y
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_GENERIC_IRQ_PROBE=y
11CONFIG_GENERIC_CALIBRATE_DELAY=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19CONFIG_LOCK_KERNEL=y
20CONFIG_INIT_ENV_ARG_LIMIT=32
21
22#
23# General setup
24#
25CONFIG_LOCALVERSION=""
26CONFIG_LOCALVERSION_AUTO=y
27CONFIG_SWAP=y
28CONFIG_SYSVIPC=y
29# CONFIG_POSIX_MQUEUE is not set
30CONFIG_BSD_PROCESS_ACCT=y
31# CONFIG_BSD_PROCESS_ACCT_V3 is not set
32CONFIG_SYSCTL=y
33# CONFIG_AUDIT is not set
34CONFIG_HOTPLUG=y
35CONFIG_KOBJECT_UEVENT=y
36CONFIG_IKCONFIG=y
37CONFIG_IKCONFIG_PROC=y
38CONFIG_INITRAMFS_SOURCE=""
39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
40CONFIG_EMBEDDED=y
41CONFIG_KALLSYMS=y
42# CONFIG_KALLSYMS_ALL is not set
43# CONFIG_KALLSYMS_EXTRA_PASS is not set
44CONFIG_PRINTK=y
45CONFIG_BUG=y
46CONFIG_BASE_FULL=y
47# CONFIG_FUTEX is not set
48# CONFIG_EPOLL is not set
49CONFIG_SHMEM=y
50CONFIG_CC_ALIGN_FUNCTIONS=0
51CONFIG_CC_ALIGN_LABELS=0
52CONFIG_CC_ALIGN_LOOPS=0
53CONFIG_CC_ALIGN_JUMPS=0
54# CONFIG_TINY_SHMEM is not set
55CONFIG_BASE_SMALL=0
56
57#
58# Loadable module support
59#
60CONFIG_MODULES=y
61CONFIG_MODULE_UNLOAD=y
62# CONFIG_MODULE_FORCE_UNLOAD is not set
63CONFIG_OBSOLETE_MODPARM=y
64# CONFIG_MODVERSIONS is not set
65# CONFIG_MODULE_SRCVERSION_ALL is not set
66CONFIG_KMOD=y
67
68#
69# Block layer
70#
71# CONFIG_LBD is not set
72
73#
74# IO Schedulers
75#
76CONFIG_IOSCHED_NOOP=y
77# CONFIG_IOSCHED_AS is not set
78# CONFIG_IOSCHED_DEADLINE is not set
79# CONFIG_IOSCHED_CFQ is not set
80# CONFIG_DEFAULT_AS is not set
81# CONFIG_DEFAULT_DEADLINE is not set
82# CONFIG_DEFAULT_CFQ is not set
83CONFIG_DEFAULT_NOOP=y
84CONFIG_DEFAULT_IOSCHED="noop"
85
86#
87# System type
88#
89# CONFIG_SH_SOLUTION_ENGINE is not set
90# CONFIG_SH_7751_SOLUTION_ENGINE is not set
91# CONFIG_SH_7300_SOLUTION_ENGINE is not set
92# CONFIG_SH_73180_SOLUTION_ENGINE is not set
93# CONFIG_SH_7751_SYSTEMH is not set
94# CONFIG_SH_STB1_HARP is not set
95# CONFIG_SH_STB1_OVERDRIVE is not set
96# CONFIG_SH_HP6XX is not set
97# CONFIG_SH_CQREEK is not set
98# CONFIG_SH_DMIDA is not set
99# CONFIG_SH_EC3104 is not set
100# CONFIG_SH_SATURN is not set
101# CONFIG_SH_DREAMCAST is not set
102# CONFIG_SH_CAT68701 is not set
103# CONFIG_SH_BIGSUR is not set
104# CONFIG_SH_SH2000 is not set
105# CONFIG_SH_ADX is not set
106# CONFIG_SH_MPC1211 is not set
107# CONFIG_SH_SH03 is not set
108# CONFIG_SH_SECUREEDGE5410 is not set
109# CONFIG_SH_HS7751RVOIP is not set
110# CONFIG_SH_RTS7751R2D is not set
111# CONFIG_SH_R77703DRP is not set
112CONFIG_SH_R7780RP=y
113# CONFIG_SH_EDOSK7705 is not set
114# CONFIG_SH_SH4202_MICRODEV is not set
115# CONFIG_SH_LANDISK is not set
116# CONFIG_SH_TITAN is not set
117# CONFIG_SH_UNKNOWN is not set
118
119#
120# Processor selection
121#
122CONFIG_CPU_SH4=y
123CONFIG_CPU_SH4A=y
124
125#
126# SH-2 Processor Support
127#
128# CONFIG_CPU_SUBTYPE_SH7604 is not set
129
130#
131# SH-3 Processor Support
132#
133# CONFIG_CPU_SUBTYPE_SH7300 is not set
134# CONFIG_CPU_SUBTYPE_SH7705 is not set
135# CONFIG_CPU_SUBTYPE_SH7707 is not set
136# CONFIG_CPU_SUBTYPE_SH7708 is not set
137# CONFIG_CPU_SUBTYPE_SH7709 is not set
138
139#
140# SH-4 Processor Support
141#
142# CONFIG_CPU_SUBTYPE_SH7750 is not set
143# CONFIG_CPU_SUBTYPE_SH7091 is not set
144# CONFIG_CPU_SUBTYPE_SH7750R is not set
145# CONFIG_CPU_SUBTYPE_SH7750S is not set
146# CONFIG_CPU_SUBTYPE_SH7751 is not set
147# CONFIG_CPU_SUBTYPE_SH7751R is not set
148# CONFIG_CPU_SUBTYPE_SH7760 is not set
149# CONFIG_CPU_SUBTYPE_SH4_202 is not set
150
151#
152# ST40 Processor Support
153#
154# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
155# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
156
157#
158# SH-4A Processor Support
159#
160# CONFIG_CPU_SUBTYPE_SH73180 is not set
161# CONFIG_CPU_SUBTYPE_SH7770 is not set
162CONFIG_CPU_SUBTYPE_SH7780=y
163
164#
165# Memory management options
166#
167CONFIG_MMU=y
168CONFIG_32BIT=y
169CONFIG_HUGETLB_PAGE_SIZE_64K=y
170# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
171CONFIG_SELECT_MEMORY_MODEL=y
172CONFIG_FLATMEM_MANUAL=y
173# CONFIG_DISCONTIGMEM_MANUAL is not set
174# CONFIG_SPARSEMEM_MANUAL is not set
175CONFIG_FLATMEM=y
176CONFIG_FLAT_NODE_MEM_MAP=y
177# CONFIG_SPARSEMEM_STATIC is not set
178CONFIG_SPLIT_PTLOCK_CPUS=4
179
180#
181# Cache configuration
182#
183# CONFIG_SH_DIRECT_MAPPED is not set
184# CONFIG_SH_WRITETHROUGH is not set
185# CONFIG_SH_OCRAM is not set
186CONFIG_MEMORY_START=0x08000000
187CONFIG_MEMORY_SIZE=0x08000000
188
189#
190# Processor features
191#
192CONFIG_CPU_LITTLE_ENDIAN=y
193CONFIG_SH_FPU=y
194CONFIG_SH_STORE_QUEUES=y
195
196#
197# Timer support
198#
199CONFIG_SH_TMU=y
200CONFIG_SH_PCLK_FREQ_BOOL=y
201CONFIG_SH_PCLK_FREQ=32000000
202
203#
204# CPU Frequency scaling
205#
206# CONFIG_CPU_FREQ is not set
207
208#
209# DMA support
210#
211CONFIG_SH_DMA=y
212CONFIG_NR_ONCHIP_DMA_CHANNELS=6
213# CONFIG_NR_DMA_CHANNELS_BOOL is not set
214
215#
216# Companion Chips
217#
218# CONFIG_HD6446X_SERIES is not set
219
220#
221# Kernel features
222#
223# CONFIG_KEXEC is not set
224CONFIG_PREEMPT=y
225# CONFIG_SMP is not set
226CONFIG_CPU_HAS_INTEVT=y
227CONFIG_CPU_HAS_INTC2_IRQ=y
228
229#
230# Boot options
231#
232CONFIG_ZERO_PAGE_OFFSET=0x00001000
233CONFIG_BOOT_LINK_OFFSET=0x00800000
234# CONFIG_UBC_WAKEUP is not set
235CONFIG_CMDLINE_BOOL=y
236CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/hda1"
237
238#
239# Bus options
240#
241CONFIG_PCI=y
242CONFIG_SH_PCIDMA_NONCOHERENT=y
243CONFIG_PCI_AUTO=y
244CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
245CONFIG_PCI_LEGACY_PROC=y
246# CONFIG_PCI_DEBUG is not set
247
248#
249# PCCARD (PCMCIA/CardBus) support
250#
251# CONFIG_PCCARD is not set
252
253#
254# PCI Hotplug Support
255#
256CONFIG_HOTPLUG_PCI=y
257# CONFIG_HOTPLUG_PCI_FAKE is not set
258# CONFIG_HOTPLUG_PCI_CPCI is not set
259# CONFIG_HOTPLUG_PCI_SHPC is not set
260
261#
262# Executable file formats
263#
264CONFIG_BINFMT_ELF=y
265# CONFIG_BINFMT_FLAT is not set
266# CONFIG_BINFMT_MISC is not set
267
268#
269# Networking
270#
271CONFIG_NET=y
272
273#
274# Networking options
275#
276CONFIG_PACKET=y
277# CONFIG_PACKET_MMAP is not set
278CONFIG_UNIX=y
279# CONFIG_NET_KEY is not set
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282CONFIG_IP_ADVANCED_ROUTER=y
283CONFIG_ASK_IP_FIB_HASH=y
284# CONFIG_IP_FIB_TRIE is not set
285CONFIG_IP_FIB_HASH=y
286# CONFIG_IP_MULTIPLE_TABLES is not set
287# CONFIG_IP_ROUTE_MULTIPATH is not set
288# CONFIG_IP_ROUTE_VERBOSE is not set
289CONFIG_IP_PNP=y
290CONFIG_IP_PNP_DHCP=y
291# CONFIG_IP_PNP_BOOTP is not set
292# CONFIG_IP_PNP_RARP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_ARPD is not set
296# CONFIG_SYN_COOKIES is not set
297# CONFIG_INET_AH is not set
298# CONFIG_INET_ESP is not set
299# CONFIG_INET_IPCOMP is not set
300# CONFIG_INET_TUNNEL is not set
301CONFIG_INET_DIAG=y
302CONFIG_INET_TCP_DIAG=y
303# CONFIG_TCP_CONG_ADVANCED is not set
304CONFIG_TCP_CONG_BIC=y
305# CONFIG_IPV6 is not set
306# CONFIG_NETFILTER is not set
307
308#
309# DCCP Configuration (EXPERIMENTAL)
310#
311# CONFIG_IP_DCCP is not set
312
313#
314# SCTP Configuration (EXPERIMENTAL)
315#
316# CONFIG_IP_SCTP is not set
317# CONFIG_ATM is not set
318CONFIG_BRIDGE=m
319# CONFIG_VLAN_8021Q is not set
320# CONFIG_DECNET is not set
321# CONFIG_LLC2 is not set
322# CONFIG_IPX is not set
323# CONFIG_ATALK is not set
324# CONFIG_X25 is not set
325# CONFIG_LAPB is not set
326# CONFIG_NET_DIVERT is not set
327# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set
329
330#
331# QoS and/or fair queueing
332#
333# CONFIG_NET_SCHED is not set
334
335#
336# Network testing
337#
338# CONFIG_NET_PKTGEN is not set
339# CONFIG_HAMRADIO is not set
340# CONFIG_IRDA is not set
341# CONFIG_BT is not set
342# CONFIG_IEEE80211 is not set
343
344#
345# Device Drivers
346#
347
348#
349# Generic Driver Options
350#
351CONFIG_STANDALONE=y
352CONFIG_PREVENT_FIRMWARE_BUILD=y
353CONFIG_FW_LOADER=m
354# CONFIG_DEBUG_DRIVER is not set
355
356#
357# Connector - unified userspace <-> kernelspace linker
358#
359# CONFIG_CONNECTOR is not set
360
361#
362# Memory Technology Devices (MTD)
363#
364# CONFIG_MTD is not set
365
366#
367# Parallel port support
368#
369# CONFIG_PARPORT is not set
370
371#
372# Plug and Play support
373#
374
375#
376# Block devices
377#
378# CONFIG_BLK_CPQ_DA is not set
379# CONFIG_BLK_CPQ_CISS_DA is not set
380# CONFIG_BLK_DEV_DAC960 is not set
381# CONFIG_BLK_DEV_UMEM is not set
382# CONFIG_BLK_DEV_COW_COMMON is not set
383# CONFIG_BLK_DEV_LOOP is not set
384# CONFIG_BLK_DEV_NBD is not set
385# CONFIG_BLK_DEV_SX8 is not set
386CONFIG_BLK_DEV_RAM=y
387CONFIG_BLK_DEV_RAM_COUNT=16
388CONFIG_BLK_DEV_RAM_SIZE=4096
389# CONFIG_BLK_DEV_INITRD is not set
390# CONFIG_CDROM_PKTCDVD is not set
391# CONFIG_ATA_OVER_ETH is not set
392
393#
394# ATA/ATAPI/MFM/RLL support
395#
396CONFIG_IDE=m
397CONFIG_IDE_MAX_HWIFS=4
398CONFIG_BLK_DEV_IDE=m
399
400#
401# Please see Documentation/ide.txt for help/info on IDE drives
402#
403CONFIG_BLK_DEV_IDE_SATA=y
404CONFIG_BLK_DEV_IDEDISK=m
405CONFIG_IDEDISK_MULTI_MODE=y
406# CONFIG_BLK_DEV_IDECD is not set
407# CONFIG_BLK_DEV_IDETAPE is not set
408# CONFIG_BLK_DEV_IDEFLOPPY is not set
409CONFIG_BLK_DEV_IDESCSI=m
410# CONFIG_IDE_TASK_IOCTL is not set
411
412#
413# IDE chipset support/bugfixes
414#
415CONFIG_IDE_GENERIC=m
416CONFIG_BLK_DEV_IDEPCI=y
417CONFIG_IDEPCI_SHARE_IRQ=y
418# CONFIG_BLK_DEV_OFFBOARD is not set
419CONFIG_BLK_DEV_GENERIC=m
420# CONFIG_BLK_DEV_OPTI621 is not set
421CONFIG_BLK_DEV_IDEDMA_PCI=y
422# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
423CONFIG_IDEDMA_PCI_AUTO=y
424# CONFIG_IDEDMA_ONLYDISK is not set
425CONFIG_BLK_DEV_AEC62XX=m
426# CONFIG_BLK_DEV_ALI15X3 is not set
427# CONFIG_BLK_DEV_AMD74XX is not set
428# CONFIG_BLK_DEV_CMD64X is not set
429# CONFIG_BLK_DEV_TRIFLEX is not set
430# CONFIG_BLK_DEV_CY82C693 is not set
431# CONFIG_BLK_DEV_CS5520 is not set
432# CONFIG_BLK_DEV_CS5530 is not set
433# CONFIG_BLK_DEV_HPT34X is not set
434# CONFIG_BLK_DEV_HPT366 is not set
435# CONFIG_BLK_DEV_SC1200 is not set
436# CONFIG_BLK_DEV_PIIX is not set
437# CONFIG_BLK_DEV_IT821X is not set
438# CONFIG_BLK_DEV_NS87415 is not set
439# CONFIG_BLK_DEV_PDC202XX_OLD is not set
440CONFIG_BLK_DEV_PDC202XX_NEW=m
441# CONFIG_PDC202XX_FORCE is not set
442# CONFIG_BLK_DEV_SVWKS is not set
443CONFIG_BLK_DEV_SIIMAGE=m
444# CONFIG_BLK_DEV_SLC90E66 is not set
445# CONFIG_BLK_DEV_TRM290 is not set
446# CONFIG_BLK_DEV_VIA82CXXX is not set
447CONFIG_IDE_SH=y
448# CONFIG_IDE_ARM is not set
449CONFIG_BLK_DEV_IDEDMA=y
450# CONFIG_IDEDMA_IVB is not set
451CONFIG_IDEDMA_AUTO=y
452# CONFIG_BLK_DEV_HD is not set
453
454#
455# SCSI device support
456#
457# CONFIG_RAID_ATTRS is not set
458CONFIG_SCSI=m
459CONFIG_SCSI_PROC_FS=y
460
461#
462# SCSI support type (disk, tape, CD-ROM)
463#
464CONFIG_BLK_DEV_SD=m
465# CONFIG_CHR_DEV_ST is not set
466# CONFIG_CHR_DEV_OSST is not set
467# CONFIG_BLK_DEV_SR is not set
468CONFIG_CHR_DEV_SG=m
469# CONFIG_CHR_DEV_SCH is not set
470
471#
472# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
473#
474# CONFIG_SCSI_MULTI_LUN is not set
475# CONFIG_SCSI_CONSTANTS is not set
476# CONFIG_SCSI_LOGGING is not set
477
478#
479# SCSI Transport Attributes
480#
481# CONFIG_SCSI_SPI_ATTRS is not set
482# CONFIG_SCSI_FC_ATTRS is not set
483# CONFIG_SCSI_ISCSI_ATTRS is not set
484# CONFIG_SCSI_SAS_ATTRS is not set
485
486#
487# SCSI low-level drivers
488#
489# CONFIG_ISCSI_TCP is not set
490# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
491# CONFIG_SCSI_3W_9XXX is not set
492# CONFIG_SCSI_ACARD is not set
493# CONFIG_SCSI_AACRAID is not set
494# CONFIG_SCSI_AIC7XXX is not set
495# CONFIG_SCSI_AIC7XXX_OLD is not set
496# CONFIG_SCSI_AIC79XX is not set
497# CONFIG_SCSI_DPT_I2O is not set
498# CONFIG_MEGARAID_NEWGEN is not set
499# CONFIG_MEGARAID_LEGACY is not set
500# CONFIG_MEGARAID_SAS is not set
501# CONFIG_SCSI_SATA is not set
502# CONFIG_SCSI_DMX3191D is not set
503# CONFIG_SCSI_FUTURE_DOMAIN is not set
504# CONFIG_SCSI_IPS is not set
505# CONFIG_SCSI_INITIO is not set
506# CONFIG_SCSI_INIA100 is not set
507# CONFIG_SCSI_SYM53C8XX_2 is not set
508# CONFIG_SCSI_IPR is not set
509# CONFIG_SCSI_QLOGIC_FC is not set
510# CONFIG_SCSI_QLOGIC_1280 is not set
511CONFIG_SCSI_QLA2XXX=m
512# CONFIG_SCSI_QLA21XX is not set
513# CONFIG_SCSI_QLA22XX is not set
514# CONFIG_SCSI_QLA2300 is not set
515# CONFIG_SCSI_QLA2322 is not set
516# CONFIG_SCSI_QLA6312 is not set
517# CONFIG_SCSI_QLA24XX is not set
518# CONFIG_SCSI_LPFC is not set
519# CONFIG_SCSI_DC395x is not set
520# CONFIG_SCSI_DC390T is not set
521# CONFIG_SCSI_NSP32 is not set
522# CONFIG_SCSI_DEBUG is not set
523
524#
525# Multi-device support (RAID and LVM)
526#
527# CONFIG_MD is not set
528
529#
530# Fusion MPT device support
531#
532# CONFIG_FUSION is not set
533# CONFIG_FUSION_SPI is not set
534# CONFIG_FUSION_FC is not set
535# CONFIG_FUSION_SAS is not set
536
537#
538# IEEE 1394 (FireWire) support
539#
540# CONFIG_IEEE1394 is not set
541
542#
543# I2O device support
544#
545# CONFIG_I2O is not set
546
547#
548# Network device support
549#
550CONFIG_NETDEVICES=y
551# CONFIG_DUMMY is not set
552# CONFIG_BONDING is not set
553# CONFIG_EQUALIZER is not set
554# CONFIG_TUN is not set
555
556#
557# ARCnet devices
558#
559# CONFIG_ARCNET is not set
560
561#
562# PHY device support
563#
564# CONFIG_PHYLIB is not set
565
566#
567# Ethernet (10 or 100Mbit)
568#
569CONFIG_NET_ETHERNET=y
570CONFIG_MII=y
571# CONFIG_STNIC is not set
572# CONFIG_HAPPYMEAL is not set
573# CONFIG_SUNGEM is not set
574# CONFIG_CASSINI is not set
575# CONFIG_NET_VENDOR_3COM is not set
576# CONFIG_SMC91X is not set
577
578#
579# Tulip family network device support
580#
581# CONFIG_NET_TULIP is not set
582# CONFIG_HP100 is not set
583CONFIG_NE2000=y
584CONFIG_NET_PCI=y
585CONFIG_PCNET32=m
586# CONFIG_AMD8111_ETH is not set
587# CONFIG_ADAPTEC_STARFIRE is not set
588# CONFIG_B44 is not set
589# CONFIG_FORCEDETH is not set
590# CONFIG_DGRS is not set
591# CONFIG_EEPRO100 is not set
592# CONFIG_E100 is not set
593# CONFIG_FEALNX is not set
594# CONFIG_NATSEMI is not set
595# CONFIG_NE2K_PCI is not set
596CONFIG_8139CP=m
597CONFIG_8139TOO=m
598# CONFIG_8139TOO_PIO is not set
599# CONFIG_8139TOO_TUNE_TWISTER is not set
600CONFIG_8139TOO_8129=y
601# CONFIG_8139_OLD_RX_RESET is not set
602# CONFIG_SIS900 is not set
603# CONFIG_EPIC100 is not set
604# CONFIG_SUNDANCE is not set
605# CONFIG_TLAN is not set
606CONFIG_VIA_RHINE=m
607CONFIG_VIA_RHINE_MMIO=y
608
609#
610# Ethernet (1000 Mbit)
611#
612# CONFIG_ACENIC is not set
613# CONFIG_DL2K is not set
614CONFIG_E1000=m
615# CONFIG_E1000_NAPI is not set
616# CONFIG_NS83820 is not set
617# CONFIG_HAMACHI is not set
618# CONFIG_YELLOWFIN is not set
619CONFIG_R8169=y
620# CONFIG_R8169_NAPI is not set
621# CONFIG_SIS190 is not set
622# CONFIG_SKGE is not set
623# CONFIG_SK98LIN is not set
624# CONFIG_VIA_VELOCITY is not set
625# CONFIG_TIGON3 is not set
626# CONFIG_BNX2 is not set
627
628#
629# Ethernet (10000 Mbit)
630#
631# CONFIG_CHELSIO_T1 is not set
632# CONFIG_IXGB is not set
633# CONFIG_S2IO is not set
634
635#
636# Token Ring devices
637#
638# CONFIG_TR is not set
639
640#
641# Wireless LAN (non-hamradio)
642#
643CONFIG_NET_RADIO=y
644
645#
646# Obsolete Wireless cards support (pre-802.11)
647#
648# CONFIG_STRIP is not set
649
650#
651# Wireless 802.11b ISA/PCI cards support
652#
653CONFIG_HERMES=m
654# CONFIG_PLX_HERMES is not set
655# CONFIG_TMD_HERMES is not set
656# CONFIG_NORTEL_HERMES is not set
657# CONFIG_PCI_HERMES is not set
658# CONFIG_ATMEL is not set
659
660#
661# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
662#
663CONFIG_PRISM54=m
664# CONFIG_HOSTAP is not set
665CONFIG_NET_WIRELESS=y
666
667#
668# Wan interfaces
669#
670# CONFIG_WAN is not set
671# CONFIG_FDDI is not set
672# CONFIG_HIPPI is not set
673# CONFIG_PPP is not set
674# CONFIG_SLIP is not set
675# CONFIG_NET_FC is not set
676# CONFIG_SHAPER is not set
677# CONFIG_NETCONSOLE is not set
678# CONFIG_NETPOLL is not set
679# CONFIG_NET_POLL_CONTROLLER is not set
680
681#
682# ISDN subsystem
683#
684# CONFIG_ISDN is not set
685
686#
687# Telephony Support
688#
689# CONFIG_PHONE is not set
690
691#
692# Input device support
693#
694CONFIG_INPUT=y
695
696#
697# Userland interfaces
698#
699CONFIG_INPUT_MOUSEDEV=y
700# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
701CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
702CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
703# CONFIG_INPUT_JOYDEV is not set
704# CONFIG_INPUT_TSDEV is not set
705# CONFIG_INPUT_EVDEV is not set
706# CONFIG_INPUT_EVBUG is not set
707
708#
709# Input Device Drivers
710#
711CONFIG_INPUT_KEYBOARD=y
712CONFIG_KEYBOARD_ATKBD=y
713# CONFIG_KEYBOARD_SUNKBD is not set
714# CONFIG_KEYBOARD_LKKBD is not set
715# CONFIG_KEYBOARD_XTKBD is not set
716# CONFIG_KEYBOARD_NEWTON is not set
717# CONFIG_INPUT_MOUSE is not set
718# CONFIG_INPUT_JOYSTICK is not set
719# CONFIG_INPUT_TOUCHSCREEN is not set
720# CONFIG_INPUT_MISC is not set
721
722#
723# Hardware I/O ports
724#
725CONFIG_SERIO=y
726# CONFIG_SERIO_I8042 is not set
727# CONFIG_SERIO_SERPORT is not set
728# CONFIG_SERIO_PCIPS2 is not set
729CONFIG_SERIO_LIBPS2=y
730# CONFIG_SERIO_RAW is not set
731# CONFIG_GAMEPORT is not set
732
733#
734# Character devices
735#
736# CONFIG_VT is not set
737# CONFIG_SERIAL_NONSTANDARD is not set
738
739#
740# Serial drivers
741#
742# CONFIG_SERIAL_8250 is not set
743
744#
745# Non-8250 serial port support
746#
747CONFIG_SERIAL_SH_SCI=y
748CONFIG_SERIAL_SH_SCI_CONSOLE=y
749CONFIG_SERIAL_CORE=y
750CONFIG_SERIAL_CORE_CONSOLE=y
751# CONFIG_SERIAL_JSM is not set
752CONFIG_UNIX98_PTYS=y
753CONFIG_LEGACY_PTYS=y
754CONFIG_LEGACY_PTY_COUNT=256
755
756#
757# IPMI
758#
759# CONFIG_IPMI_HANDLER is not set
760
761#
762# Watchdog Cards
763#
764# CONFIG_WATCHDOG is not set
765# CONFIG_RTC is not set
766# CONFIG_GEN_RTC is not set
767# CONFIG_DTLK is not set
768# CONFIG_R3964 is not set
769# CONFIG_APPLICOM is not set
770
771#
772# Ftape, the floppy tape device driver
773#
774# CONFIG_DRM is not set
775# CONFIG_RAW_DRIVER is not set
776
777#
778# TPM devices
779#
780# CONFIG_TCG_TPM is not set
781# CONFIG_TELCLOCK is not set
782
783#
784# I2C support
785#
786# CONFIG_I2C is not set
787
788#
789# Dallas's 1-wire bus
790#
791# CONFIG_W1 is not set
792
793#
794# Hardware Monitoring support
795#
796CONFIG_HWMON=y
797# CONFIG_HWMON_VID is not set
798# CONFIG_HWMON_DEBUG_CHIP is not set
799
800#
801# Misc devices
802#
803
804#
805# Multimedia Capabilities Port drivers
806#
807
808#
809# Multimedia devices
810#
811# CONFIG_VIDEO_DEV is not set
812
813#
814# Digital Video Broadcasting Devices
815#
816# CONFIG_DVB is not set
817
818#
819# Graphics support
820#
821# CONFIG_FB is not set
822
823#
824# Sound
825#
826CONFIG_SOUND=m
827
828#
829# Advanced Linux Sound Architecture
830#
831# CONFIG_SND is not set
832
833#
834# Open Sound System
835#
836CONFIG_SOUND_PRIME=m
837# CONFIG_OBSOLETE_OSS_DRIVER is not set
838# CONFIG_SOUND_FUSION is not set
839# CONFIG_SOUND_ICH is not set
840# CONFIG_SOUND_TRIDENT is not set
841# CONFIG_SOUND_MSNDCLAS is not set
842# CONFIG_SOUND_MSNDPIN is not set
843
844#
845# USB support
846#
847CONFIG_USB_ARCH_HAS_HCD=y
848CONFIG_USB_ARCH_HAS_OHCI=y
849# CONFIG_USB is not set
850
851#
852# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
853#
854
855#
856# USB Gadget Support
857#
858# CONFIG_USB_GADGET is not set
859
860#
861# MMC/SD Card support
862#
863# CONFIG_MMC is not set
864
865#
866# InfiniBand support
867#
868# CONFIG_INFINIBAND is not set
869
870#
871# SN Devices
872#
873
874#
875# File systems
876#
877CONFIG_EXT2_FS=y
878# CONFIG_EXT2_FS_XATTR is not set
879# CONFIG_EXT2_FS_XIP is not set
880CONFIG_EXT3_FS=y
881CONFIG_EXT3_FS_XATTR=y
882# CONFIG_EXT3_FS_POSIX_ACL is not set
883# CONFIG_EXT3_FS_SECURITY is not set
884CONFIG_JBD=y
885# CONFIG_JBD_DEBUG is not set
886CONFIG_FS_MBCACHE=y
887# CONFIG_REISERFS_FS is not set
888# CONFIG_JFS_FS is not set
889CONFIG_FS_POSIX_ACL=y
890# CONFIG_XFS_FS is not set
891CONFIG_MINIX_FS=y
892# CONFIG_ROMFS_FS is not set
893CONFIG_INOTIFY=y
894# CONFIG_QUOTA is not set
895CONFIG_DNOTIFY=y
896# CONFIG_AUTOFS_FS is not set
897# CONFIG_AUTOFS4_FS is not set
898# CONFIG_FUSE_FS is not set
899
900#
901# CD-ROM/DVD Filesystems
902#
903# CONFIG_ISO9660_FS is not set
904# CONFIG_UDF_FS is not set
905
906#
907# DOS/FAT/NT Filesystems
908#
909CONFIG_FAT_FS=y
910CONFIG_MSDOS_FS=y
911CONFIG_VFAT_FS=y
912CONFIG_FAT_DEFAULT_CODEPAGE=437
913CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
914CONFIG_NTFS_FS=y
915# CONFIG_NTFS_DEBUG is not set
916CONFIG_NTFS_RW=y
917
918#
919# Pseudo filesystems
920#
921CONFIG_PROC_FS=y
922CONFIG_PROC_KCORE=y
923CONFIG_SYSFS=y
924# CONFIG_TMPFS is not set
925CONFIG_HUGETLBFS=y
926CONFIG_HUGETLB_PAGE=y
927CONFIG_RAMFS=y
928# CONFIG_RELAYFS_FS is not set
929
930#
931# Miscellaneous filesystems
932#
933# CONFIG_ADFS_FS is not set
934# CONFIG_AFFS_FS is not set
935# CONFIG_HFS_FS is not set
936# CONFIG_HFSPLUS_FS is not set
937# CONFIG_BEFS_FS is not set
938# CONFIG_BFS_FS is not set
939# CONFIG_EFS_FS is not set
940# CONFIG_CRAMFS is not set
941# CONFIG_VXFS_FS is not set
942# CONFIG_HPFS_FS is not set
943# CONFIG_QNX4FS_FS is not set
944# CONFIG_SYSV_FS is not set
945# CONFIG_UFS_FS is not set
946
947#
948# Network File Systems
949#
950CONFIG_NFS_FS=y
951CONFIG_NFS_V3=y
952# CONFIG_NFS_V3_ACL is not set
953CONFIG_NFS_V4=y
954# CONFIG_NFS_DIRECTIO is not set
955CONFIG_NFSD=y
956CONFIG_NFSD_V3=y
957# CONFIG_NFSD_V3_ACL is not set
958CONFIG_NFSD_V4=y
959CONFIG_NFSD_TCP=y
960CONFIG_ROOT_NFS=y
961CONFIG_LOCKD=y
962CONFIG_LOCKD_V4=y
963CONFIG_EXPORTFS=y
964CONFIG_NFS_COMMON=y
965CONFIG_SUNRPC=y
966CONFIG_SUNRPC_GSS=y
967CONFIG_RPCSEC_GSS_KRB5=y
968# CONFIG_RPCSEC_GSS_SPKM3 is not set
969# CONFIG_SMB_FS is not set
970# CONFIG_CIFS is not set
971# CONFIG_NCP_FS is not set
972# CONFIG_CODA_FS is not set
973# CONFIG_AFS_FS is not set
974# CONFIG_9P_FS is not set
975
976#
977# Partition Types
978#
979# CONFIG_PARTITION_ADVANCED is not set
980CONFIG_MSDOS_PARTITION=y
981
982#
983# Native Language Support
984#
985CONFIG_NLS=y
986CONFIG_NLS_DEFAULT="iso8859-1"
987CONFIG_NLS_CODEPAGE_437=y
988# CONFIG_NLS_CODEPAGE_737 is not set
989# CONFIG_NLS_CODEPAGE_775 is not set
990# CONFIG_NLS_CODEPAGE_850 is not set
991# CONFIG_NLS_CODEPAGE_852 is not set
992# CONFIG_NLS_CODEPAGE_855 is not set
993# CONFIG_NLS_CODEPAGE_857 is not set
994# CONFIG_NLS_CODEPAGE_860 is not set
995# CONFIG_NLS_CODEPAGE_861 is not set
996# CONFIG_NLS_CODEPAGE_862 is not set
997# CONFIG_NLS_CODEPAGE_863 is not set
998# CONFIG_NLS_CODEPAGE_864 is not set
999# CONFIG_NLS_CODEPAGE_865 is not set
1000# CONFIG_NLS_CODEPAGE_866 is not set
1001# CONFIG_NLS_CODEPAGE_869 is not set
1002# CONFIG_NLS_CODEPAGE_936 is not set
1003# CONFIG_NLS_CODEPAGE_950 is not set
1004CONFIG_NLS_CODEPAGE_932=y
1005# CONFIG_NLS_CODEPAGE_949 is not set
1006# CONFIG_NLS_CODEPAGE_874 is not set
1007# CONFIG_NLS_ISO8859_8 is not set
1008# CONFIG_NLS_CODEPAGE_1250 is not set
1009# CONFIG_NLS_CODEPAGE_1251 is not set
1010# CONFIG_NLS_ASCII is not set
1011CONFIG_NLS_ISO8859_1=y
1012# CONFIG_NLS_ISO8859_2 is not set
1013# CONFIG_NLS_ISO8859_3 is not set
1014# CONFIG_NLS_ISO8859_4 is not set
1015# CONFIG_NLS_ISO8859_5 is not set
1016# CONFIG_NLS_ISO8859_6 is not set
1017# CONFIG_NLS_ISO8859_7 is not set
1018# CONFIG_NLS_ISO8859_9 is not set
1019# CONFIG_NLS_ISO8859_13 is not set
1020# CONFIG_NLS_ISO8859_14 is not set
1021# CONFIG_NLS_ISO8859_15 is not set
1022# CONFIG_NLS_KOI8_R is not set
1023# CONFIG_NLS_KOI8_U is not set
1024# CONFIG_NLS_UTF8 is not set
1025
1026#
1027# Profiling support
1028#
1029# CONFIG_PROFILING is not set
1030
1031#
1032# Kernel hacking
1033#
1034# CONFIG_PRINTK_TIME is not set
1035CONFIG_DEBUG_KERNEL=y
1036# CONFIG_MAGIC_SYSRQ is not set
1037CONFIG_LOG_BUF_SHIFT=14
1038CONFIG_DETECT_SOFTLOCKUP=y
1039# CONFIG_SCHEDSTATS is not set
1040# CONFIG_DEBUG_SLAB is not set
1041CONFIG_DEBUG_PREEMPT=y
1042CONFIG_DEBUG_SPINLOCK=y
1043# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1044# CONFIG_DEBUG_KOBJECT is not set
1045# CONFIG_DEBUG_INFO is not set
1046CONFIG_DEBUG_FS=y
1047# CONFIG_DEBUG_VM is not set
1048CONFIG_FRAME_POINTER=y
1049# CONFIG_RCU_TORTURE_TEST is not set
1050# CONFIG_SH_STANDARD_BIOS is not set
1051# CONFIG_EARLY_SCIF_CONSOLE is not set
1052# CONFIG_KGDB is not set
1053
1054#
1055# Security options
1056#
1057# CONFIG_KEYS is not set
1058# CONFIG_SECURITY is not set
1059
1060#
1061# Cryptographic options
1062#
1063CONFIG_CRYPTO=y
1064CONFIG_CRYPTO_HMAC=y
1065# CONFIG_CRYPTO_NULL is not set
1066# CONFIG_CRYPTO_MD4 is not set
1067CONFIG_CRYPTO_MD5=y
1068# CONFIG_CRYPTO_SHA1 is not set
1069# CONFIG_CRYPTO_SHA256 is not set
1070# CONFIG_CRYPTO_SHA512 is not set
1071# CONFIG_CRYPTO_WP512 is not set
1072# CONFIG_CRYPTO_TGR192 is not set
1073CONFIG_CRYPTO_DES=y
1074# CONFIG_CRYPTO_BLOWFISH is not set
1075# CONFIG_CRYPTO_TWOFISH is not set
1076# CONFIG_CRYPTO_SERPENT is not set
1077# CONFIG_CRYPTO_AES is not set
1078# CONFIG_CRYPTO_CAST5 is not set
1079# CONFIG_CRYPTO_CAST6 is not set
1080# CONFIG_CRYPTO_TEA is not set
1081# CONFIG_CRYPTO_ARC4 is not set
1082# CONFIG_CRYPTO_KHAZAD is not set
1083# CONFIG_CRYPTO_ANUBIS is not set
1084# CONFIG_CRYPTO_DEFLATE is not set
1085# CONFIG_CRYPTO_MICHAEL_MIC is not set
1086# CONFIG_CRYPTO_CRC32C is not set
1087# CONFIG_CRYPTO_TEST is not set
1088
1089#
1090# Hardware crypto devices
1091#
1092
1093#
1094# Library routines
1095#
1096# CONFIG_CRC_CCITT is not set
1097# CONFIG_CRC16 is not set
1098CONFIG_CRC32=y
1099# CONFIG_LIBCRC32C is not set
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 0f15216cd39d..defc13c37d48 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -11,6 +11,8 @@ config SH_DMA
11config NR_ONCHIP_DMA_CHANNELS 11config NR_ONCHIP_DMA_CHANNELS
12 depends on SH_DMA 12 depends on SH_DMA
13 int "Number of on-chip DMAC channels" 13 int "Number of on-chip DMAC channels"
14 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
15 default "12" if CPU_SUBTYPE_SH7780
14 default "4" 16 default "4"
15 help 17 help
16 This allows you to specify the number of channels that the on-chip 18 This allows you to specify the number of channels that the on-chip
@@ -52,4 +54,3 @@ config DMA_PAGE_OPS_CHANNEL
52 are dual-address capable. 54 are dual-address capable.
53 55
54endmenu 56endmenu
55
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index e028a2d2a4ea..4428ee809651 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -11,14 +11,10 @@
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details. 12 * for more details.
13 */ 13 */
14
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h> 15#include <linux/interrupt.h>
18#include <linux/module.h> 16#include <linux/module.h>
19#include <asm/dreamcast/dma.h> 17#include <asm/dreamcast/dma.h>
20#include <asm/signal.h>
21#include <asm/irq.h>
22#include <asm/dma.h> 18#include <asm/dma.h>
23#include <asm/io.h> 19#include <asm/io.h>
24#include "dma-sh.h" 20#include "dma-sh.h"
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 86d6d0660d4c..3d8078f1c05f 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
7 7
8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o 8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o
10 11
11obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ 12obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
12 dma-dreamcast.o 13 dma-dreamcast.o
@@ -14,4 +15,5 @@ obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
14obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o 15obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o
15obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o 16obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
16obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o 17obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
18obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o
17obj-$(CONFIG_SH_TITAN) += ops-titan.o 19obj-$(CONFIG_SH_TITAN) += ops-titan.o
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
new file mode 100644
index 000000000000..b656b562ec99
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -0,0 +1,39 @@
1/*
2 * arch/sh/drivers/pci/fixups-r7780rp.c
3 *
4 * Highlander R7780RP-1 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include "pci-sh7780.h"
14#include <asm/io.h>
15
16int pci_fixup_pcic(void)
17{
18 outl(0x000043ff, PCI_REG(SH7780_PCIIMR));
19 outl(0x0000380f, PCI_REG(SH7780_PCIAINTM));
20
21 outl(0xfbb00047, PCI_REG(SH7780_PCICMD));
22 outl(0x00000000, PCI_REG(SH7780_PCIIBAR));
23
24 outl(0x00011912, PCI_REG(SH7780_PCISVID));
25 outl(0x08000000, PCI_REG(SH7780_PCICSCR0));
26 outl(0x0000001b, PCI_REG(SH7780_PCICSAR0));
27 outl(0xfd000000, PCI_REG(SH7780_PCICSCR1));
28 outl(0x0000000f, PCI_REG(SH7780_PCICSAR1));
29
30 outl(0xfd000000, PCI_REG(SH7780_PCIMBR0));
31 outl(0x00fc0000, PCI_REG(SH7780_PCIMBMR0));
32
33 /* Set IOBR for windows containing area specified in pci.h */
34 outl((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1)), PCI_REG(SH7780_PCIIOBR));
35 outl(((SH7780_PCI_IO_SIZE-1) & (7<<18)), PCI_REG(SH7780_PCIIOBMR));
36
37 return 0;
38}
39
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
new file mode 100644
index 000000000000..3254c4e917a9
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -0,0 +1,77 @@
1/*
2 * Author: Ian DaSilva (idasilva@mvista.com)
3 *
4 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * PCI initialization for the Renesas SH7780 Highlander R7780RP-1 board
10 */
11
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pci.h>
18#include <linux/module.h>
19
20#include <asm/io.h>
21#include "pci-sh7780.h"
22#include <asm/r7780rp/r7780rp.h>
23
24int __init pcibios_map_platform_irq(u8 slot, u8 pin)
25{
26 switch (slot) {
27 case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */
28 case 1: return IRQ_PCISLOT2; /* PCI Interrupt #2 */
29 case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */
30 case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */
31 default:
32 printk("PCI: Bad IRQ mapping request for slot %d, func %d\n", slot, pin-1);
33 return -1;
34 }
35}
36
37static struct resource sh7780_io_resource = {
38 .name = "SH7780_IO",
39 .start = 0x2000,
40 .end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
41 .flags = IORESOURCE_IO
42};
43
44static struct resource sh7780_mem_resource = {
45 .name = "SH7780_mem",
46 .start = SH7780_PCI_MEMORY_BASE,
47 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
48 .flags = IORESOURCE_MEM
49};
50
51extern struct pci_ops sh7780_pci_ops;
52
53struct pci_channel board_pci_channels[] = {
54 { &sh7780_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff },
55 { NULL, NULL, NULL, 0, 0 },
56};
57EXPORT_SYMBOL(board_pci_channels);
58
59static struct sh7780_pci_address_map sh7780_pci_map = {
60 .window0 = {
61 .base = SH7780_CS2_BASE_ADDR,
62 .size = 0x04000000,
63 },
64
65 .window1 = {
66 .base = SH7780_CS3_BASE_ADDR,
67 .size = 0x04000000,
68 },
69
70 .flags = SH7780_PCIC_NO_RESET,
71};
72
73int __init pcibios_init_platform(void)
74{
75 return sh7780_pcic_init(&sh7780_pci_map);
76}
77
diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c
index 4cef4d1d8c84..d55e46618549 100644
--- a/arch/sh/drivers/pci/pci-auto.c
+++ b/arch/sh/drivers/pci/pci-auto.c
@@ -45,11 +45,11 @@
45#include <linux/types.h> 45#include <linux/types.h>
46#include <linux/pci.h> 46#include <linux/pci.h>
47 47
48#undef DEBUG 48#define DEBUG
49#ifdef DEBUG 49#ifdef DEBUG
50#define DBG(x...) printk(x) 50#define DBG(x...) printk(x)
51#else 51#else
52#define DBG(x...) 52#define DBG(x...)
53#endif 53#endif
54 54
55/* 55/*
@@ -102,7 +102,7 @@ static u32 pciauto_upper_iospc;
102static u32 pciauto_lower_memspc; 102static u32 pciauto_lower_memspc;
103static u32 pciauto_upper_memspc; 103static u32 pciauto_upper_memspc;
104 104
105static void __init 105static void __init
106pciauto_setup_bars(struct pci_channel *hose, 106pciauto_setup_bars(struct pci_channel *hose,
107 int top_bus, 107 int top_bus,
108 int current_bus, 108 int current_bus,
@@ -116,7 +116,6 @@ pciauto_setup_bars(struct pci_channel *hose,
116 int found_mem64 = 0; 116 int found_mem64 = 0;
117 117
118 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) { 118 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
119#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
120 u32 bar_addr; 119 u32 bar_addr;
121 120
122 /* Read the old BAR value */ 121 /* Read the old BAR value */
@@ -125,7 +124,6 @@ pciauto_setup_bars(struct pci_channel *hose,
125 pci_devfn, 124 pci_devfn,
126 bar, 125 bar,
127 &bar_addr); 126 &bar_addr);
128#endif
129 127
130 /* Tickle the BAR and get the response */ 128 /* Tickle the BAR and get the response */
131 early_write_config_dword(hose, top_bus, 129 early_write_config_dword(hose, top_bus,
@@ -140,8 +138,7 @@ pciauto_setup_bars(struct pci_channel *hose,
140 bar, 138 bar,
141 &bar_response); 139 &bar_response);
142 140
143#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) 141 /*
144 /*
145 * Write the old BAR value back out, only update the BAR 142 * Write the old BAR value back out, only update the BAR
146 * if we implicitly want resources to be updated, which 143 * if we implicitly want resources to be updated, which
147 * is done by the generic code further down. -- PFM. 144 * is done by the generic code further down. -- PFM.
@@ -151,7 +148,6 @@ pciauto_setup_bars(struct pci_channel *hose,
151 pci_devfn, 148 pci_devfn,
152 bar, 149 bar,
153 bar_addr); 150 bar_addr);
154#endif
155 151
156 /* If BAR is not implemented go to the next BAR */ 152 /* If BAR is not implemented go to the next BAR */
157 if (!bar_response) 153 if (!bar_response)
@@ -177,7 +173,7 @@ retry:
177 PCI_BASE_ADDRESS_MEM_TYPE_64) 173 PCI_BASE_ADDRESS_MEM_TYPE_64)
178 found_mem64 = 1; 174 found_mem64 = 1;
179 175
180 addr_mask = PCI_BASE_ADDRESS_MEM_MASK; 176 addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
181 upper_limit = &pciauto_upper_memspc; 177 upper_limit = &pciauto_upper_memspc;
182 lower_limit = &pciauto_lower_memspc; 178 lower_limit = &pciauto_lower_memspc;
183 DBG(" Mem"); 179 DBG(" Mem");
@@ -193,22 +189,22 @@ retry:
193 if ((bar_value + bar_size) > *upper_limit) { 189 if ((bar_value + bar_size) > *upper_limit) {
194 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 190 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
195 if (io_resource_inuse->child) { 191 if (io_resource_inuse->child) {
196 io_resource_inuse = 192 io_resource_inuse =
197 io_resource_inuse->child; 193 io_resource_inuse->child;
198 pciauto_lower_iospc = 194 pciauto_lower_iospc =
199 io_resource_inuse->start; 195 io_resource_inuse->start;
200 pciauto_upper_iospc = 196 pciauto_upper_iospc =
201 io_resource_inuse->end + 1; 197 io_resource_inuse->end + 1;
202 goto retry; 198 goto retry;
203 } 199 }
204 200
205 } else { 201 } else {
206 if (mem_resource_inuse->child) { 202 if (mem_resource_inuse->child) {
207 mem_resource_inuse = 203 mem_resource_inuse =
208 mem_resource_inuse->child; 204 mem_resource_inuse->child;
209 pciauto_lower_memspc = 205 pciauto_lower_memspc =
210 mem_resource_inuse->start; 206 mem_resource_inuse->start;
211 pciauto_upper_memspc = 207 pciauto_upper_memspc =
212 mem_resource_inuse->end + 1; 208 mem_resource_inuse->end + 1;
213 goto retry; 209 goto retry;
214 } 210 }
@@ -230,7 +226,7 @@ retry:
230 * If we are a 64-bit decoder then increment to the 226 * If we are a 64-bit decoder then increment to the
231 * upper 32 bits of the bar and force it to locate 227 * upper 32 bits of the bar and force it to locate
232 * in the lower 4GB of memory. 228 * in the lower 4GB of memory.
233 */ 229 */
234 if (found_mem64) { 230 if (found_mem64) {
235 bar += 4; 231 bar += 4;
236 early_write_config_dword(hose, top_bus, 232 early_write_config_dword(hose, top_bus,
@@ -362,7 +358,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
362{ 358{
363 u32 temp; 359 u32 temp;
364 360
365#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) 361#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) && !defined(CONFIG_SH_R7780RP)
366 /* 362 /*
367 * [jsun] we always bump up baselines a little, so that if there 363 * [jsun] we always bump up baselines a little, so that if there
368 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM 364 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
@@ -396,7 +392,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
396 * configured by this routine to happily live behind a 392 * configured by this routine to happily live behind a
397 * P2P bridge in a system. 393 * P2P bridge in a system.
398 */ 394 */
399#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) 395#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
400 pciauto_lower_memspc += 0x00400000; 396 pciauto_lower_memspc += 0x00400000;
401 pciauto_lower_iospc += 0x00004000; 397 pciauto_lower_iospc += 0x00004000;
402#endif 398#endif
@@ -433,12 +429,12 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
433 int devfn_stop = 0xff; 429 int devfn_stop = 0xff;
434 430
435 sub_bus = current_bus; 431 sub_bus = current_bus;
436 432
437 if (hose->first_devfn) 433 if (hose->first_devfn)
438 devfn_start = hose->first_devfn; 434 devfn_start = hose->first_devfn;
439 if (hose->last_devfn) 435 if (hose->last_devfn)
440 devfn_stop = hose->last_devfn; 436 devfn_stop = hose->last_devfn;
441 437
442 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) { 438 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
443 439
444 if (PCI_FUNC(pci_devfn) && !found_multi) 440 if (PCI_FUNC(pci_devfn) && !found_multi)
@@ -471,7 +467,7 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
471 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { 467 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
472 DBG(" Bridge: primary=%.2x, secondary=%.2x\n", 468 DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
473 current_bus, sub_bus + 1); 469 current_bus, sub_bus + 1);
474#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) 470#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
475 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1); 471 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
476#endif 472#endif
477 pciauto_prescan_setup_bridge(hose, top_bus, current_bus, 473 pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
@@ -490,10 +486,10 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
490 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); 486 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
491 /* Place CardBus Socket/ExCA registers */ 487 /* Place CardBus Socket/ExCA registers */
492 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0); 488 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
493 489
494 pciauto_prescan_setup_cardbus_bridge(hose, top_bus, 490 pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
495 current_bus, pci_devfn, sub_bus); 491 current_bus, pci_devfn, sub_bus);
496 492
497 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", 493 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
498 sub_bus + 1, 494 sub_bus + 1,
499 pciauto_lower_iospc, pciauto_lower_memspc); 495 pciauto_lower_iospc, pciauto_lower_memspc);
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 682f3dae305d..65093ec1b55e 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -223,7 +223,7 @@ static int __init __area_sdram_check(unsigned int area)
223 223
224 word = inl(SH7751_BCR1); 224 word = inl(SH7751_BCR1);
225 /* check BCR for SDRAM in area */ 225 /* check BCR for SDRAM in area */
226 if(((word >> area) & 1) == 0) { 226 if (((word >> area) & 1) == 0) {
227 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", 227 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
228 area, word); 228 area, word);
229 return 0; 229 return 0;
@@ -232,7 +232,7 @@ static int __init __area_sdram_check(unsigned int area)
232 232
233 word = (u16)inw(SH7751_BCR2); 233 word = (u16)inw(SH7751_BCR2);
234 /* check BCR2 for 32bit SDRAM interface*/ 234 /* check BCR2 for 32bit SDRAM interface*/
235 if(((word >> (area << 1)) & 0x3) != 0x3) { 235 if (((word >> (area << 1)) & 0x3) != 0x3) {
236 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", 236 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
237 area, word); 237 area, word);
238 return 0; 238 return 0;
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
new file mode 100644
index 000000000000..e09721330ac2
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -0,0 +1,341 @@
1/*
2 * Low-Level PCI Support for the SH7780
3 *
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 *
14 */
15
16#undef DEBUG
17
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/pci.h>
23#include <linux/sched.h>
24#include <linux/ioport.h>
25#include <linux/errno.h>
26#include <linux/irq.h>
27#include <linux/delay.h>
28
29#include <asm/machvec.h>
30#include <asm/io.h>
31#include "pci-sh7780.h"
32
33static unsigned int pci_probe = PCI_PROBE_CONF1;
34extern int pci_fixup_pcic(void);
35
36/*
37 * Direct access to PCI hardware...
38 */
39
40#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
41
42/*
43 * Functions for accessing PCI configuration space with type 1 accesses
44 */
45static int sh7780_pci_read(struct pci_bus *bus, unsigned int devfn,
46 int where, int size, u32 *val)
47{
48 unsigned long flags;
49 u32 data;
50
51 /*
52 * PCIPDR may only be accessed as 32 bit words,
53 * so we must do byte alignment by hand
54 */
55 local_irq_save(flags);
56 outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
57 data = inl(PCI_REG(SH7780_PCIPDR));
58 local_irq_restore(flags);
59
60 switch (size) {
61 case 1:
62 *val = (data >> ((where & 3) << 3)) & 0xff;
63 break;
64 case 2:
65 *val = (data >> ((where & 2) << 3)) & 0xffff;
66 break;
67 case 4:
68 *val = data;
69 break;
70 default:
71 return PCIBIOS_FUNC_NOT_SUPPORTED;
72 }
73
74 return PCIBIOS_SUCCESSFUL;
75}
76
77/*
78 * Since SH7780 only does 32bit access we'll have to do a read,
79 * mask,write operation.
80 * We'll allow an odd byte offset, though it should be illegal.
81 */
82static int sh7780_pci_write(struct pci_bus *bus, unsigned int devfn,
83 int where, int size, u32 val)
84{
85 unsigned long flags;
86 int shift;
87 u32 data;
88
89 local_irq_save(flags);
90 outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
91 data = inl(PCI_REG(SH7780_PCIPDR));
92 local_irq_restore(flags);
93
94 switch (size) {
95 case 1:
96 shift = (where & 3) << 3;
97 data &= ~(0xff << shift);
98 data |= ((val & 0xff) << shift);
99 break;
100 case 2:
101 shift = (where & 2) << 3;
102 data &= ~(0xffff << shift);
103 data |= ((val & 0xffff) << shift);
104 break;
105 case 4:
106 data = val;
107 break;
108 default:
109 return PCIBIOS_FUNC_NOT_SUPPORTED;
110 }
111
112 outl(data, PCI_REG(SH7780_PCIPDR));
113
114 return PCIBIOS_SUCCESSFUL;
115}
116
117#undef CONFIG_CMD
118
119struct pci_ops sh7780_pci_ops = {
120 .read = sh7780_pci_read,
121 .write = sh7780_pci_write,
122};
123
124static int __init pci_check_direct(void)
125{
126 unsigned int tmp, id;
127
128 outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
129
130 /* check for SH7780/SH7780R hardware */
131 id = inl(PCI_REG(SH7780_PCIVID));
132 if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
133 (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
134 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
135 return -ENODEV;
136 }
137
138 /*
139 * Check if configuration works.
140 */
141 if (pci_probe & PCI_PROBE_CONF1) {
142 tmp = inl(PCI_REG(SH7780_PCIPAR));
143 outl(0x80000000, PCI_REG(SH7780_PCIPAR));
144 if (inl(PCI_REG(SH7780_PCIPAR)) == 0x80000000) {
145 outl(tmp, PCI_REG(SH7780_PCIPAR));
146 printk(KERN_INFO "PCI: Using configuration type 1\n");
147 request_region(PCI_REG(SH7780_PCIPAR), 8, "PCI conf1");
148 return 0;
149 }
150 outl(tmp, PCI_REG(SH7780_PCIPAR));
151 }
152
153 pr_debug("PCI: pci_check_direct failed\n");
154 return -EINVAL;
155}
156
157/***************************************************************************************/
158
159/*
160 * Handle bus scanning and fixups ....
161 */
162
163static void __init pci_fixup_ide_bases(struct pci_dev *d)
164{
165 int i;
166
167 /*
168 * PCI IDE controllers use non-standard I/O port decoding, respect it.
169 */
170 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
171 return;
172 pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
173 for(i=0; i<4; i++) {
174 struct resource *r = &d->resource[i];
175 if ((r->start & ~0x80) == 0x374) {
176 r->start |= 2;
177 r->end = r->start;
178 }
179 }
180}
181
182DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
183
184/*
185 * Called after each bus is probed, but before its children
186 * are examined.
187 */
188
189void __init pcibios_fixup_bus(struct pci_bus *b)
190{
191 pci_read_bridge_bases(b);
192}
193
194/*
195 * Initialization. Try all known PCI access methods. Note that we support
196 * using both PCI BIOS and direct access: in such cases, we use I/O ports
197 * to access config space.
198 *
199 * Note that the platform specific initialization (BSC registers, and memory
200 * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
201 * exists and via the platform defined function pcibios_init_platform().
202 * See pci_bigsur.c for implementation;
203 *
204 * The BIOS version of the pci functions is not yet implemented but it is left
205 * in for completeness. Currently an error will be genereated at compile time.
206 */
207
208static int __init sh7780_pci_init(void)
209{
210 int ret;
211
212 pr_debug("PCI: Starting intialization.\n");
213
214 /* Setup the INTC */
215 ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
216 ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
217 ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
218 ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
219 ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
220 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
221
222 if ((ret = pci_check_direct()) != 0)
223 return ret;
224
225 return pcibios_init_platform();
226}
227
228core_initcall(sh7780_pci_init);
229
230int __init sh7780_pcic_init(struct sh7780_pci_address_map *map)
231{
232 u32 word;
233
234 /*
235 * This code is unused for some boards as it is done in the
236 * bootloader and doing it here means the MAC addresses loaded
237 * by the bootloader get lost.
238 */
239 if (!(map->flags & SH7780_PCIC_NO_RESET)) {
240 /* toggle PCI reset pin */
241 word = SH7780_PCICR_PREFIX | SH7780_PCICR_PRST;
242 outl(word,PCI_REG(SH7780_PCICR));
243 /* Wait for a long time... not 1 sec. but long enough */
244 mdelay(100);
245 word = SH7780_PCICR_PREFIX;
246 outl(word,PCI_REG(SH7780_PCICR));
247 }
248
249 /* set the command/status bits to:
250 * Wait Cycle Control + Parity Enable + Bus Master +
251 * Mem space enable
252 */
253 outl(0x00000046, PCI_REG(SH7780_PCICMD));
254
255 /* define this host as the host bridge */
256 word = SH7780_PCI_HOST_BRIDGE << 24;
257 outl(word, PCI_REG(SH7780_PCIRID));
258
259 /* Set IO and Mem windows to local address
260 * Make PCI and local address the same for easy 1 to 1 mapping
261 * Window0 = map->window0.size @ non-cached area base = SDRAM
262 * Window1 = map->window1.size @ cached area base = SDRAM
263 */
264 word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
265 outl(0x07f00001, PCI_REG(SH7780_PCILSR0));
266 word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
267 outl(0x00000001, PCI_REG(SH7780_PCILSR1));
268 /* Set the values on window 0 PCI config registers */
269 word = P2SEGADDR(map->window0.base);
270 outl(0xa8000000, PCI_REG(SH7780_PCILAR0));
271 outl(0x08000000, PCI_REG(SH7780_PCIMBAR0));
272 /* Set the values on window 1 PCI config registers */
273 word = P2SEGADDR(map->window1.base);
274 outl(0x00000000, PCI_REG(SH7780_PCILAR1));
275 outl(0x00000000, PCI_REG(SH7780_PCIMBAR1));
276
277 /* Map IO space into PCI IO window
278 * The IO window is 64K-PCIBIOS_MIN_IO in size
279 * IO addresses will be translated to the
280 * PCI IO window base address
281 */
282 PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
283 (64*1024), SH7780_PCI_IO_BASE+PCIBIOS_MIN_IO);
284
285 /* NOTE: I'm ignoring the PCI error IRQs for now..
286 * TODO: add support for the internal error interrupts and
287 * DMA interrupts...
288 */
289
290#ifdef CONFIG_SH_R7780RP
291 pci_fixup_pcic();
292#endif
293
294 /* SH7780 init done, set central function init complete */
295 /* use round robin mode to stop a device starving/overruning */
296 word = SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | /* SH7780_PCICR_ARBM |*/ SH7780_PCICR_FTO;
297 outl(word, PCI_REG(SH7780_PCICR));
298
299 return 1;
300}
301
302char * __init pcibios_setup(char *str)
303{
304 if (!strcmp(str, "off")) {
305 pci_probe = 0;
306 return NULL;
307 }
308
309 return str;
310}
311
312/*
313 * IRQ functions
314 */
315static u8 __init sh7780_no_swizzle(struct pci_dev *dev, u8 *pin)
316{
317 /* no swizzling */
318 return PCI_SLOT(dev->devfn);
319}
320
321static int sh7780_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
322{
323 int irq = -1;
324
325 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
326 irq = pcibios_map_platform_irq(slot,pin);
327 if( irq < 0 ) {
328 pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev));
329 return irq;
330 }
331
332 pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
333
334 return irq;
335}
336
337void __init pcibios_fixup_irqs(void)
338{
339 pci_fixup_irqs(sh7780_no_swizzle, sh7780_pci_lookup_irq);
340}
341
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
new file mode 100644
index 000000000000..750d5d7753a2
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -0,0 +1,168 @@
1/*
2 * Low-Level PCI Support for SH7780 targets
3 *
4 * Dustin McIntire (dustin@sensoria.com) (c) 2001
5 * Paul Mundt (lethal@linux-sh.org) (c) 2003
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 */
11
12#ifndef _PCI_SH7780_H_
13#define _PCI_SH7780_H_
14
15#include <linux/pci.h>
16
17/* set debug level 4=verbose...1=terse */
18//#define DEBUG_PCI 3
19#undef DEBUG_PCI
20
21#ifdef DEBUG_PCI
22#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
23#else
24#define PCIDBG(n, x...)
25#endif
26
27/* startup values */
28#define PCI_PROBE_BIOS 1
29#define PCI_PROBE_CONF1 2
30#define PCI_PROBE_CONF2 4
31#define PCI_NO_SORT 0x100
32#define PCI_BIOS_SORT 0x200
33#define PCI_NO_CHECKS 0x400
34#define PCI_ASSIGN_ROMS 0x1000
35#define PCI_BIOS_IRQ_SCAN 0x2000
36
37/* Platform Specific Values */
38#define SH7780_VENDOR_ID 0x1912
39#define SH7780_DEVICE_ID 0x0002
40#define SH7781_DEVICE_ID 0x0001
41
42/* SH7780 Control Registers */
43#define SH7780_PCI_VCR0 0xFE000000
44#define SH7780_PCI_VCR1 0xFE000004
45#define SH7780_PCI_VCR2 0xFE000008
46
47/* SH7780 Specific Values */
48#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
49#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
50#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
51#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
52#if 1
53#define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */
54#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
55#else
56#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
57#define SH7780_PCI_IO_SIZE 0x00200000 /* Size of IO window */
58#endif
59
60#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
61#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
62
63/* SH7780 PCI Config Registers */
64#define SH7780_PCIVID 0x000 /* Vendor ID */
65#define SH7780_PCIDID 0x002 /* Device ID */
66#define SH7780_PCICMD 0x004 /* Command */
67#define SH7780_PCISTATUS 0x006 /* Status */
68#define SH7780_PCIRID 0x008 /* Revision ID */
69#define SH7780_PCIPIF 0x009 /* Program Interface */
70#define SH7780_PCISUB 0x00a /* Sub class code */
71#define SH7780_PCIBCC 0x00b /* Base class code */
72#define SH7780_PCICLS 0x00c /* Cache line size */
73#define SH7780_PCILTM 0x00d /* latency timer */
74#define SH7780_PCIHDR 0x00e /* Header type */
75#define SH7780_PCIBIST 0x00f /* BIST */
76#define SH7780_PCIIBAR 0x010 /* IO Base address */
77#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
78#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
79#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
80#define SH7780_PCISID 0x02e /* Sub system ID */
81#define SH7780_PCICP 0x034
82#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
83#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
84#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
85#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
86#define SH7780_PCICID 0x040
87#define SH7780_PCINIP 0x041
88#define SH7780_PCIPMC 0x042
89#define SH7780_PCIPMCSR 0x044
90#define SH7780_PCIPMCSR_BSE 0x046
91#define SH7780_PCICDD 0x047
92
93/* SH7780 PCI Local Registers */
94#define SH7780_PCICR 0x100 /* PCI Control Register */
95 #define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
96 #define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */
97 #define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
98 #define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */
99 #define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */
100 #define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
101 #define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */
102 #define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */
103 #define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
104#define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */
105#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
106#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
107#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
108#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
109#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
110#define SH7780_PCIAIR 0x11C /* Error Address Register */
111#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
112#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
113#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
114#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
115#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
116#define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */
117#define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */
118#define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */
119#define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */
120#define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */
121#define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */
122#define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */
123#define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */
124#define SH7780_PCIIOBR 0x1F8 /* Bank Register */
125#define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */
126#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
127#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
128#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
129#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
130#define SH7780_PCIPDR 0x220 /* Port IO Data Register */
131
132/* General Memory Config Addresses */
133#define SH7780_CS0_BASE_ADDR 0x0
134#define SH7780_MEM_REGION_SIZE 0x04000000
135#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
136#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
137#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
138#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
139#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
140#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
141
142/* General PCI values */
143#define SH7780_PCI_HOST_BRIDGE 0x6
144
145/* Flags */
146#define SH7780_PCIC_NO_RESET 0x0001
147
148/* External functions defined per platform i.e. Big Sur, SE... (these could be routed
149 * through the machine vectors... */
150extern int pcibios_init_platform(void);
151extern int pcibios_map_platform_irq(u8 slot, u8 pin);
152
153struct sh7780_pci_address_space {
154 unsigned long base;
155 unsigned long size;
156};
157
158struct sh7780_pci_address_map {
159 struct sh7780_pci_address_space window0;
160 struct sh7780_pci_address_space window1;
161 unsigned long flags;
162};
163
164/* arch/sh/drivers/pci/pci-sh7780.c */
165extern int sh7780_pcic_init(struct sh7780_pci_address_map *map);
166
167#endif /* _PCI_SH7780_H_ */
168
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index 30064bf6e154..e30e4b7aa70e 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -241,9 +241,9 @@ static struct intc2_init {
241 /* 110-111 reserved/unused */ 241 /* 110-111 reserved/unused */
242#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 242#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
243 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2}, 243 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
244#ifdef CONFIG_SH_RTC 244 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
245 { RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY }, 245 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
246#endif 246 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
247 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, 247 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
248 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, 248 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
249 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, 249 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 01ae394a6599..1f7f2c255ca2 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -26,4 +26,6 @@ EDOSK7705 SH_EDOSK7705
26SH4202_MICRODEV SH_SH4202_MICRODEV 26SH4202_MICRODEV SH_SH4202_MICRODEV
27SH03 SH_SH03 27SH03 SH_SH03
28LANDISK SH_LANDISK 28LANDISK SH_LANDISK
29R7780RP SH_R7780RP
30R7780MP SH_R7780MP
29TITAN SH_TITAN 31TITAN SH_TITAN
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
index 727634d886ce..bb2e1b03060c 100644
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -22,5 +22,8 @@
22#define P4SEG_TLB_DATA 0xf7000000 22#define P4SEG_TLB_DATA 0xf7000000
23#define P4SEG_REG_BASE 0xff000000 23#define P4SEG_REG_BASE 0xff000000
24 24
25#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
26#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
27
25#endif /* __ASM_CPU_SH4_ADDRSPACE_H */ 28#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
26 29
diff --git a/include/asm-sh/cpu-sh4/dma-sh7780.h b/include/asm-sh/cpu-sh4/dma-sh7780.h
new file mode 100644
index 000000000000..6c90d28331b2
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma-sh7780.h
@@ -0,0 +1,39 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int __attribute__ ((used)) ts_shift[] = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index 0dfe61f14802..3e4b3e6d80c0 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,11 +1,17 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
4#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
5#define SH_DMAC_BASE 0xfc808020 7#define SH_DMAC_BASE 0xfc808020
8
9#define CHCR_TS_MASK 0x18
10#define CHCR_TS_SHIFT 3
11
12#include <asm/cpu/dma-sh7780.h>
6#else 13#else
7#define SH_DMAC_BASE 0xffa00000 14#define SH_DMAC_BASE 0xffa00000
8#endif
9 15
10/* Definitions for the SuperH DMAC */ 16/* Definitions for the SuperH DMAC */
11#define TM_BURST 0x0000080 17#define TM_BURST 0x0000080
@@ -19,8 +25,6 @@
19 25
20#define DMAOR_COD 0x00000008 26#define DMAOR_COD 0x00000008
21 27
22#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
23
24/* 28/*
25 * The SuperH DMAC supports a number of transmit sizes, we list them here, 29 * The SuperH DMAC supports a number of transmit sizes, we list them here,
26 * with their respective values as they appear in the CHCR registers. 30 * with their respective values as they appear in the CHCR registers.
@@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = {
45 [XMIT_SZ_32BIT] = 2, 49 [XMIT_SZ_32BIT] = 2,
46 [XMIT_SZ_256BIT] = 5, 50 [XMIT_SZ_256BIT] = 5,
47}; 51};
52#endif
48 53
49#endif /* __ASM_CPU_SH4_DMA_H */ 54#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
index 69faf0171473..c4cff9d33927 100644
--- a/include/asm-sh/hs7751rvoip/hs7751rvoip.h
+++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
@@ -19,8 +19,6 @@
19#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */ 19#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
20#define PA_VERREG 0xa4000014 /* FPGA Version Register */ 20#define PA_VERREG 0xa4000014 /* FPGA Version Register */
21 21
22#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
23#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
24#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 22#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
25 23
26#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 24#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
index 7f90315cd830..895c5780e454 100644
--- a/include/asm-sh/irq-sh7780.h
+++ b/include/asm-sh/irq-sh7780.h
@@ -145,11 +145,6 @@
145#define TMU_CH5_IPR_POS 1 145#define TMU_CH5_IPR_POS 1
146#define TMU_CH5_PRIORITY 2 146#define TMU_CH5_PRIORITY 2
147 147
148#define RTC_IRQ 22
149#define RTC_IPR_ADDR INTC_INT2PRI1
150#define RTC_IPR_POS 0
151#define RTC_PRIORITY TIMER_PRIORITY
152
153/* SCIF0 */ 148/* SCIF0 */
154#define SCIF0_ERI_IRQ 40 149#define SCIF0_ERI_IRQ 40
155#define SCIF0_RXI_IRQ 41 150#define SCIF0_RXI_IRQ 41
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 611e67cd0627..7e8455b1cb44 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq);
577#define NR_INTC2_IRQS 64 577#define NR_INTC2_IRQS 64
578#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 578#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
579#define INTC2_BASE 0xffd40000 579#define INTC2_BASE 0xffd40000
580#define INTC2_FIRST_IRQ 22 580#define INTC2_FIRST_IRQ 21
581#define INTC2_INTMSK_OFFSET (0x38) 581#define INTC2_INTMSK_OFFSET (0x38)
582#define INTC2_INTMSKCLR_OFFSET (0x3c) 582#define INTC2_INTMSKCLR_OFFSET (0x3c)
583#define NR_INTC2_IRQS 60 583#define NR_INTC2_IRQS 60
diff --git a/include/asm-sh/landisk/iodata_landisk.h b/include/asm-sh/landisk/iodata_landisk.h
index 9db3cdfe6776..c74d3c73f377 100644
--- a/include/asm-sh/landisk/iodata_landisk.h
+++ b/include/asm-sh/landisk/iodata_landisk.h
@@ -22,8 +22,6 @@
22/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */ 22/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
23#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */ 23#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
24 24
25#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
26#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
27#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */ 25#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
28#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */ 26#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
29#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */ 27#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
diff --git a/include/asm-sh/r7780rp/ide.h b/include/asm-sh/r7780rp/ide.h
new file mode 100644
index 000000000000..a1ed78e0f617
--- /dev/null
+++ b/include/asm-sh/r7780rp/ide.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_R7780RP_IDE_H
2#define __ASM_SH_R7780RP_IDE_H
3
4/* Nothing to see here.. */
5#include <asm/mach/r7780rp.h>
6
7#endif /* __ASM_SH_R7780RP_IDE_H */
8
diff --git a/include/asm-sh/r7780rp/r7780rp.h b/include/asm-sh/r7780rp/r7780rp.h
new file mode 100644
index 000000000000..f95d9dba31a2
--- /dev/null
+++ b/include/asm-sh/r7780rp/r7780rp.h
@@ -0,0 +1,177 @@
1#ifndef __ASM_SH_RENESAS_R7780RP_H
2#define __ASM_SH_RENESAS_R7780RP_H
3
4/*
5 * linux/include/asm-sh/r7780rp.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Solutions Highlander R7780RP support
10 */
11
12/* Box specific addresses. */
13#if defined(CONFIG_SH_R7780MP)
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
16#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
17#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
18#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
19#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
20#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
21#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
22#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
23#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
24#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
25#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
26#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
27#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
28#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
29#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
30#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
31#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
32#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
33#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
34#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
35#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
36#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
37#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
38#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
39#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
40#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
41#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
42#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
43#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
44#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
45#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
46#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
47#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
48#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
49#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
50#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
51#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
52#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
53#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
54#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
55#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
56#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
57#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
58#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
59#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
60#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
61#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
62#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
63#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
64#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
65#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
66#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
67#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
68#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
69#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
70#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
71#define PA_PMR (PA_BCR+0x0900) /* */
72
73#define PA_AX88796L 0xa4100400 /* AX88796L Area */
74#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
75#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
76#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
77#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
78#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
79
80#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
81
82#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
83#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
84#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
85#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
86#define IRQ_CFCARD 1 /* CF Card IRQ */
87// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
88#define IRQ_TP 2 /* Touch Panel IRQ */
89#define IRQ_SCI1 3 /* SCI1 IRQ */
90#define IRQ_SCI0 4 /* SCI0 IRQ */
91#define IRQ_2SERIAL 5 /* Serial IRQ */
92#define IRQ_RTC 6 /* RTC A / B IRQ */
93#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
94#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
95#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
96#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
97#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
98#define IRQ_ONETH 13 /* On board Ethernet IRQ */
99#define IRQ_PSW 14 /* Push Switch IRQ */
100
101#else /* R7780RP */
102
103#define PA_BCR 0xa5000000 /* FPGA */
104#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
105#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
106#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
107#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
108#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
109#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
110#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
111#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
112#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
113#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
114#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
115#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
116#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
117#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
118#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
119#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
120#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
121#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
122#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
123#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
124#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
125#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
126#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
127#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
128#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
129#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
130#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
131#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
132#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
133#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
134#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
135#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
136#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
137#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
138#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
139#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
140#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
141#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
142#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
143#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
144#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
145#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
146
147#define PA_AX88796L 0xa5800400 /* AX88796L Area */
148#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
149#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
150#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
151#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
152#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
153
154#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
155
156#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
157#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
158#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
159#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
160#define IRQ_CFCARD 4 /* CF Card IRQ */
161#define IRQ_CFINST 5 /* CF Card Insert IRQ */
162#define IRQ_M66596 6 /* M66596 IRQ */
163#define IRQ_SDCARD 7 /* SD Card IRQ */
164#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
165#define IRQ_SCI 9 /* SCI IRQ */
166#define IRQ_2SERIAL 10 /* Serial IRQ */
167#define IRQ_EXTENTION 11 /* EXTn IRQ */
168#define IRQ_ONETH 12 /* On board Ethernet IRQ */
169#define IRQ_PSW 13 /* Push Switch IRQ */
170#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
171
172#endif /* CONFIG_SH_R7780MP */
173
174#define __IO_PREFIX r7780rp
175#include <asm/io_generic.h>
176
177#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/rts7751r2d/rts7751r2d.h b/include/asm-sh/rts7751r2d/rts7751r2d.h
index 4e09ba597e9a..b112ae221fd1 100644
--- a/include/asm-sh/rts7751r2d/rts7751r2d.h
+++ b/include/asm-sh/rts7751r2d/rts7751r2d.h
@@ -41,8 +41,6 @@
41 41
42#define PA_AX88796L 0xaa000400 /* AX88796L Area */ 42#define PA_AX88796L 0xaa000400 /* AX88796L Area */
43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ 43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
44#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
45#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
46#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 44#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
47#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ 45#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
48 46
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 08:43:36 -0500