bnx2x, cnic, bnx2i: use new FW/HSI

This is the new FW HSI blob and the relevant definitions without logic changes.
It also included code adaptation for new HSI. New features are not enabled.

New FW/HSI includes:
- Support for 57712 HW
- Future support for VF (not used)
- Improvements in FW interrupts scheme
- FW FCoE hooks (stubs for future usage)

Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

19 files changed, 4764 insertions, 3222 deletions

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 64329c5fbdea..8b053e0c00ab 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -33,13 +33,11 @@
 #define BNX2X_NEW_NAPI
 
 
-
 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
 #define BCM_CNIC 1
 #include "../cnic_if.h"
 #endif
 
-
 #ifdef BCM_CNIC
 #define BNX2X_MIN_MSIX_VEC_CNT 3
 #define BNX2X_MSIX_VEC_FP_START 2
@@ -129,16 +127,18 @@ void bnx2x_panic_dump(struct bnx2x *bp);
         } while (0)
 #endif
 
+#define bnx2x_mc_addr(ha)      ((ha)->addr)
 
 #define U64_LO(x)                       (u32)(((u64)(x)) & 0xffffffff)
 #define U64_HI(x)                       (u32)(((u64)(x)) >> 32)
 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 
 
-#define REG_ADDR(bp, offset)            (bp->regview + offset)
+#define REG_ADDR(bp, offset)            ((bp->regview) + (offset))
 
 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
+#define REG_RD16(bp, offset)            readw(REG_ADDR(bp, offset))
 
 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
@@ -160,6 +160,9 @@ void bnx2x_panic_dump(struct bnx2x *bp);
                                  offset, len32); \
         } while (0)
 
+#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
+        REG_WR_DMAE(bp, offset, valp, len32)
+
 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
         do { \
                 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
@@ -175,16 +178,52 @@ void bnx2x_panic_dump(struct bnx2x *bp);
                                          offsetof(struct shmem2_region, field))
 #define SHMEM2_RD(bp, field)            REG_RD(bp, SHMEM2_ADDR(bp, field))
 #define SHMEM2_WR(bp, field, val)       REG_WR(bp, SHMEM2_ADDR(bp, field), val)
+#define MF_CFG_ADDR(bp, field)          (bp->common.mf_cfg_base + \
+                                         offsetof(struct mf_cfg, field))
 
-#define MF_CFG_RD(bp, field)            SHMEM_RD(bp, mf_cfg.field)
-#define MF_CFG_WR(bp, field, val)       SHMEM_WR(bp, mf_cfg.field, val)
+#define MF_CFG_RD(bp, field)            REG_RD(bp, MF_CFG_ADDR(bp, field))
+#define MF_CFG_WR(bp, field, val)       REG_WR(bp,\
+                                               MF_CFG_ADDR(bp, field), (val))
 
 #define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 #define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 
+/* SP SB indices */
+
+/* General SP events - stats query, cfc delete, etc  */
+#define HC_SP_INDEX_ETH_DEF_CONS                3
+
+/* EQ completions */
+#define HC_SP_INDEX_EQ_CONS                     7
+
+/* iSCSI L2 */
+#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS           5
+#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS        1
+
+/**
+ *  CIDs and CLIDs:
+ *  CLIDs below is a CLID for func 0, then the CLID for other
+ *  functions will be calculated by the formula:
+ *
+ *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
+ *
+ */
+/* iSCSI L2 */
+#define BNX2X_ISCSI_ETH_CL_ID           17
+#define BNX2X_ISCSI_ETH_CID             17
+
+/** Additional rings budgeting */
+#ifdef BCM_CNIC
+#define CNIC_CONTEXT_USE                1
+#else
+#define CNIC_CONTEXT_USE                0
+#endif /* BCM_CNIC */
+
 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
 
+#define SM_RX_ID                        0
+#define SM_TX_ID                        1
 
 /* fast path */
 
@@ -254,11 +293,21 @@ union db_prod {
 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 
+union host_hc_status_block {
+        /* pointer to fp status block e1x */
+        struct host_hc_status_block_e1x *e1x_sb;
+};
 
 struct bnx2x_fastpath {
 
         struct napi_struct      napi;
-        struct host_status_block *status_blk;
+        union host_hc_status_block status_blk;
+        /* chip independed shortcuts into sb structure */
+        __le16                  *sb_index_values;
+        __le16                  *sb_running_index;
+        /* chip independed shortcut into rx_prods_offset memory */
+        u32                     ustorm_rx_prods_offset;
+
         dma_addr_t              status_blk_mapping;
 
         struct sw_tx_bd         *tx_buf_ring;
@@ -288,10 +337,15 @@ struct bnx2x_fastpath {
 #define BNX2X_FP_STATE_OPEN             0xa0000
 #define BNX2X_FP_STATE_HALTING          0xb0000
 #define BNX2X_FP_STATE_HALTED           0xc0000
+#define BNX2X_FP_STATE_TERMINATING      0xd0000
+#define BNX2X_FP_STATE_TERMINATED       0xe0000
 
         u8                      index;  /* number in fp array */
         u8                      cl_id;  /* eth client id */
-        u8                      sb_id;  /* status block number in HW */
+        u8                      cl_qzone_id;
+        u8                      fw_sb_id;       /* status block number in FW */
+        u8                      igu_sb_id;      /* status block number in HW */
+        u32                     cid;