diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-09-10 18:36:37 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-19 08:11:47 -0400 |
commit | 515b239269fb67fd167676d335a56ef0c13e53d5 (patch) | |
tree | bc2e9cf84eb57ab612b95f91e7d8ea1c7676bacc | |
parent | 507c1a454809da54af21091875f883e0364c5378 (diff) |
drm/i915: write D_COMP using the mailbox
You can't write it using the MCHBAR mirror, the write will just get
dropped.
This should make us BSpec-compliant, but there's no real bug I could
reproduce that is fixed by this patch.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Fix spelling mistake in the comment that Damien spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 10 |
2 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 384adfba3983..af6f93ca7296 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -1441,6 +1441,8 @@ | |||
1441 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | 1441 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
1442 | * every way. It is not accessible from the CP register read instructions. | 1442 | * every way. It is not accessible from the CP register read instructions. |
1443 | * | 1443 | * |
1444 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, | ||
1445 | * just read. | ||
1444 | */ | 1446 | */ |
1445 | #define MCHBAR_MIRROR_BASE 0x10000 | 1447 | #define MCHBAR_MIRROR_BASE 0x10000 |
1446 | 1448 | ||
@@ -4724,6 +4726,8 @@ | |||
4724 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | 4726 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
4725 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 | 4727 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
4726 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | 4728 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
4729 | #define GEN6_PCODE_READ_D_COMP 0x10 | ||
4730 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | ||
4727 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) | 4731 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
4728 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | 4732 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
4729 | #define GEN6_PCODE_DATA 0x138128 | 4733 | #define GEN6_PCODE_DATA 0x138128 |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4dd6561cb7c8..5e6fa778d763 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -6140,7 +6140,10 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv, | |||
6140 | 6140 | ||
6141 | val = I915_READ(D_COMP); | 6141 | val = I915_READ(D_COMP); |
6142 | val |= D_COMP_COMP_DISABLE; | 6142 | val |= D_COMP_COMP_DISABLE; |
6143 | I915_WRITE(D_COMP, val); | 6143 | mutex_lock(&dev_priv->rps.hw_lock); |
6144 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | ||
6145 | DRM_ERROR("Failed to disable D_COMP\n"); | ||
6146 | mutex_unlock(&dev_priv->rps.hw_lock); | ||
6144 | POSTING_READ(D_COMP); | 6147 | POSTING_READ(D_COMP); |
6145 | ndelay(100); | 6148 | ndelay(100); |
6146 | 6149 | ||
@@ -6182,7 +6185,10 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
6182 | val = I915_READ(D_COMP); | 6185 | val = I915_READ(D_COMP); |
6183 | val |= D_COMP_COMP_FORCE; | 6186 | val |= D_COMP_COMP_FORCE; |
6184 | val &= ~D_COMP_COMP_DISABLE; | 6187 | val &= ~D_COMP_COMP_DISABLE; |
6185 | I915_WRITE(D_COMP, val); | 6188 | mutex_lock(&dev_priv->rps.hw_lock); |
6189 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | ||
6190 | DRM_ERROR("Failed to enable D_COMP\n"); | ||
6191 | mutex_unlock(&dev_priv->rps.hw_lock); | ||
6186 | POSTING_READ(D_COMP); | 6192 | POSTING_READ(D_COMP); |
6187 | 6193 | ||
6188 | val = I915_READ(LCPLL_CTL); | 6194 | val = I915_READ(LCPLL_CTL); |