drm/radeon/kms: add 3DC compression support

There are 2 formats:
ATI1N: 64 bits per 4x4 block, one-channel format
ATI2N: 128 bits per 4x4 block, two-channel format

Signed-off-by: Dave Airlie <airlied@redhat.com>

2 files changed, 19 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 6a5d1177afab..3f2cc9e2e8d9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -887,6 +887,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].cpp = 1;
                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
                         break;
+                case R300_TX_FORMAT_ATI2N:
+                        if (p->rdev->family < CHIP_R420) {
+                                DRM_ERROR("Invalid texture format %u\n",
+                                          (idx_value & 0x1F));
+                                return -EINVAL;
+                        }
+                        /* The same rules apply as for DXT3/5. */
+                        /* Pass through. */
                 case R300_TX_FORMAT_DXT3:
                 case R300_TX_FORMAT_DXT5:
                         track->textures[i].cpp = 1;
@@ -951,6 +959,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].width_11 = tmp;
                         tmp = ((idx_value >> 16) & 1) << 11;
                         track->textures[i].height_11 = tmp;
+
+                        /* ATI1N */
+                        if (idx_value & (1 << 14)) {
+                                /* The same rules apply as for DXT1. */
+                                track->textures[i].compress_format =
+                                        R100_TRACK_COMP_DXT1;
+                        }
+                } else if (idx_value & (1 << 14)) {
+                        DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
+                        return -EINVAL;
                 }
                 break;
         case 0x4480:
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef35a65..1735a2b69580 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -900,6 +900,7 @@
 #       define R300_TX_FORMAT_FL_I32                0x1B
 #       define R300_TX_FORMAT_FL_I32A32             0x1C
 #       define R300_TX_FORMAT_FL_R32G32B32A32       0x1D
+#       define R300_TX_FORMAT_ATI2N                 0x1F
         /* alpha modes, convenience mostly */
         /* if you have alpha, pick constant appropriate to the
            number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */