diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-24 07:47:04 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-29 08:47:56 -0400 |
commit | 5093aec872e5be7a55d8dd2b639e8a3818dc19db (patch) | |
tree | 13fa9ff0778bfd5463c79fa3a81239afb81dc374 | |
parent | d1735a2ebd8868ee9b5bb419860e633f0f839042 (diff) |
arm: davinci: Cleanup irq chip code
Make use of the new functionality which ensures that irq_set_type is
called with the chip masked. Unmask is only done when the interrupt is
not disabled.
Retrieve the trigger type from irq_data in unmask
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r-- | arch/arm/mach-davinci/gpio.c | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 20d66e5e4663..f33d4380e367 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -218,7 +218,7 @@ static void gpio_irq_enable(struct irq_data *d) | |||
218 | { | 218 | { |
219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
220 | u32 mask = (u32) irq_data_get_irq_data(d); | 220 | u32 mask = (u32) irq_data_get_irq_data(d); |
221 | unsigned status = irq_desc[d->irq].status; | 221 | unsigned status = irqd_get_trigger_type(d); |
222 | 222 | ||
223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | 223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
224 | if (!status) | 224 | if (!status) |
@@ -238,16 +238,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned trigger) | |||
238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
239 | return -EINVAL; | 239 | return -EINVAL; |
240 | 240 | ||
241 | irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; | ||
242 | irq_desc[d->irq].status |= trigger; | ||
243 | |||
244 | /* don't enable the IRQ if it's currently disabled */ | ||
245 | if (irq_desc[d->irq].depth == 0) { | ||
246 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | ||
247 | ? &g->set_falling : &g->clr_falling); | ||
248 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | ||
249 | ? &g->set_rising : &g->clr_rising); | ||
250 | } | ||
251 | return 0; | 241 | return 0; |
252 | } | 242 | } |
253 | 243 | ||
@@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = { | |||
256 | .irq_enable = gpio_irq_enable, | 246 | .irq_enable = gpio_irq_enable, |
257 | .irq_disable = gpio_irq_disable, | 247 | .irq_disable = gpio_irq_disable, |
258 | .irq_set_type = gpio_irq_type, | 248 | .irq_set_type = gpio_irq_type, |
249 | .flags = IRQCHIP_SET_TYPE_MASKED, | ||
259 | }; | 250 | }; |
260 | 251 | ||
261 | static void | 252 | static void |
@@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
395 | 386 | ||
396 | /* AINTC handles mask/unmask; GPIO handles triggering */ | 387 | /* AINTC handles mask/unmask; GPIO handles triggering */ |
397 | irq = bank_irq; | 388 | irq = bank_irq; |
398 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | 389 | gpio_irqchip_unbanked = *irq_get_chip(irq); |
399 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | 390 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; |
400 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; | 391 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; |
401 | 392 | ||
@@ -409,7 +400,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
409 | set_irq_chip(irq, &gpio_irqchip_unbanked); | 400 | set_irq_chip(irq, &gpio_irqchip_unbanked); |
410 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 401 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
411 | set_irq_chip_data(irq, (__force void *) g); | 402 | set_irq_chip_data(irq, (__force void *) g); |
412 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; | 403 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
413 | } | 404 | } |
414 | 405 | ||
415 | goto done; | 406 | goto done; |