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authorAlexander Shishkin <alexander.shishkin@linux.intel.com>2012-05-11 10:25:58 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-05-11 20:01:06 -0400
commit4fd09e8e025d5a5b4a1fd67df9197c3d4e1b171d (patch)
tree9290e215bd00d10300ea7f1f540091f03adae880
parentab3999a26147e9c0d2949df751b86519065bf8bd (diff)
usb: gadget: remove langwell_udc
We have the chipidea driver now that supports both langwell and penwell, so there is no need for this one any more. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--drivers/usb/gadget/Kconfig16
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/langwell_udc.c3419
-rw-r--r--drivers/usb/gadget/langwell_udc.h223
-rw-r--r--include/linux/usb/langwell_udc.h310
5 files changed, 0 insertions, 3969 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1d7405c180d5..11c2b21862eb 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -431,22 +431,6 @@ config USB_GOKU
431 dynamically linked module called "goku_udc" and to force all 431 dynamically linked module called "goku_udc" and to force all
432 gadget drivers to also be dynamically linked. 432 gadget drivers to also be dynamically linked.
433 433
434config USB_LANGWELL
435 tristate "Intel Langwell USB Device Controller"
436 depends on PCI
437 depends on !PHYS_ADDR_T_64BIT
438 select USB_GADGET_DUALSPEED
439 help
440 Intel Langwell USB Device Controller is a High-Speed USB
441 On-The-Go device controller.
442
443 The number of programmable endpoints is different through
444 controller revision.
445
446 Say "y" to link the driver statically, or "m" to build a
447 dynamically linked module called "langwell_udc" and force all
448 gadget drivers to also be dynamically linked.
449
450config USB_EG20T 434config USB_EG20T
451 tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7831) UDC" 435 tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7831) UDC"
452 depends on PCI 436 depends on PCI
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 6ddfd26e8f38..51019aa9a268 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
24obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o 24obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
25obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o 25obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
26obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o 26obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
27obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
28obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o 27obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
29obj-$(CONFIG_USB_EG20T) += pch_udc.o 28obj-$(CONFIG_USB_EG20T) += pch_udc.o
30obj-$(CONFIG_USB_MV_UDC) += mv_udc.o 29obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
deleted file mode 100644
index e119519cdaf4..000000000000
--- a/drivers/usb/gadget/langwell_udc.c
+++ /dev/null
@@ -1,3419 +0,0 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10
11/* #undef DEBUG */
12/* #undef VERBOSE_DEBUG */
13
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/ioport.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/timer.h>
25#include <linux/list.h>
26#include <linux/interrupt.h>
27#include <linux/moduleparam.h>
28#include <linux/device.h>
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb/otg.h>
32#include <linux/pm.h>
33#include <linux/io.h>
34#include <linux/irq.h>
35#include <asm/unaligned.h>
36
37#include "langwell_udc.h"
38
39
40#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
41#define DRIVER_VERSION "16 May 2009"
42
43static const char driver_name[] = "langwell_udc";
44static const char driver_desc[] = DRIVER_DESC;
45
46
47/* for endpoint 0 operations */
48static const struct usb_endpoint_descriptor
49langwell_ep0_desc = {
50 .bLength = USB_DT_ENDPOINT_SIZE,
51 .bDescriptorType = USB_DT_ENDPOINT,
52 .bEndpointAddress = 0,
53 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
54 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
55};
56
57
58/*-------------------------------------------------------------------------*/
59/* debugging */
60
61#ifdef VERBOSE_DEBUG
62static inline void print_all_registers(struct langwell_udc *dev)
63{
64 int i;
65
66 /* Capability Registers */
67 dev_dbg(&dev->pdev->dev,
68 "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
69 CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
70 dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
71 readb(&dev->cap_regs->caplength));
72 dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
73 readw(&dev->cap_regs->hciversion));
74 dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
75 readl(&dev->cap_regs->hcsparams));
76 dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
77 readl(&dev->cap_regs->hccparams));
78 dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
79 readw(&dev->cap_regs->dciversion));
80 dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
81 readl(&dev->cap_regs->dccparams));
82
83 /* Operational Registers */
84 dev_dbg(&dev->pdev->dev,
85 "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
86 OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
87 dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
88 readl(&dev->op_regs->extsts));
89 dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
90 readl(&dev->op_regs->extintr));
91 dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
92 readl(&dev->op_regs->usbcmd));
93 dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
94 readl(&dev->op_regs->usbsts));
95 dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
96 readl(&dev->op_regs->usbintr));
97 dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
98 readl(&dev->op_regs->frindex));
99 dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
100 readl(&dev->op_regs->ctrldssegment));
101 dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
102 readl(&dev->op_regs->deviceaddr));
103 dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
104 readl(&dev->op_regs->endpointlistaddr));
105 dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
106 readl(&dev->op_regs->ttctrl));
107 dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
108 readl(&dev->op_regs->burstsize));
109 dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
110 readl(&dev->op_regs->txfilltuning));
111 dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
112 readl(&dev->op_regs->txttfilltuning));
113 dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
114 readl(&dev->op_regs->ic_usb));
115 dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
116 readl(&dev->op_regs->ulpi_viewport));
117 dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
118 readl(&dev->op_regs->configflag));
119 dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
120 readl(&dev->op_regs->portsc1));
121 dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
122 readl(&dev->op_regs->devlc));
123 dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
124 readl(&dev->op_regs->otgsc));
125 dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
126 readl(&dev->op_regs->usbmode));
127 dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
128 readl(&dev->op_regs->endptnak));
129 dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
130 readl(&dev->op_regs->endptnaken));
131 dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
132 readl(&dev->op_regs->endptsetupstat));
133 dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
134 readl(&dev->op_regs->endptprime));
135 dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
136 readl(&dev->op_regs->endptflush));
137 dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
138 readl(&dev->op_regs->endptstat));
139 dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
140 readl(&dev->op_regs->endptcomplete));
141
142 for (i = 0; i < dev->ep_max / 2; i++) {
143 dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
144 i, readl(&dev->op_regs->endptctrl[i]));
145 }
146}
147#else
148
149#define print_all_registers(dev) do { } while (0)
150
151#endif /* VERBOSE_DEBUG */
152
153
154/*-------------------------------------------------------------------------*/
155
156#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
157 USB_DIR_IN) : (usb_endpoint_dir_in((ep)->ep.desc)))
158
159#define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
160
161
162static char *type_string(const struct usb_endpoint_descriptor *desc)
163{
164 switch (usb_endpoint_type(desc)) {
165 case USB_ENDPOINT_XFER_BULK:
166 return "bulk";
167 case USB_ENDPOINT_XFER_ISOC:
168 return "iso";
169 case USB_ENDPOINT_XFER_INT:
170 return "int";
171 };
172
173 return "control";
174}
175
176
177/* configure endpoint control registers */
178static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
179 unsigned char is_in, unsigned char ep_type)
180{
181 struct langwell_udc *dev;
182 u32 endptctrl;
183
184 dev = ep->dev;
185 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
186
187 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
188 if (is_in) { /* TX */
189 if (ep_num)
190 endptctrl |= EPCTRL_TXR;
191 endptctrl |= EPCTRL_TXE;
192 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
193 } else { /* RX */
194 if (ep_num)
195 endptctrl |= EPCTRL_RXR;
196 endptctrl |= EPCTRL_RXE;
197 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
198 }
199
200 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
201
202 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
203}
204
205
206/* reset ep0 dQH and endptctrl */
207static void ep0_reset(struct langwell_udc *dev)
208{
209 struct langwell_ep *ep;
210 int i;
211
212 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
213
214 /* ep0 in and out */
215 for (i = 0; i < 2; i++) {
216 ep = &dev->ep[i];
217 ep->dev = dev;
218
219 /* ep0 dQH */
220 ep->dqh = &dev->ep_dqh[i];
221
222 /* configure ep0 endpoint capabilities in dQH */
223 ep->dqh->dqh_ios = 1;
224 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
225
226 /* enable ep0-in HW zero length termination select */
227 if (is_in(ep))
228 ep->dqh->dqh_zlt = 0;
229 ep->dqh->dqh_mult = 0;
230
231 ep->dqh->dtd_next = DTD_TERM;
232
233 /* configure ep0 control registers */
234 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
235 }
236
237 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
238}
239
240
241/*-------------------------------------------------------------------------*/
242
243/* endpoints operations */
244
245/* configure endpoint, making it usable */
246static int langwell_ep_enable(struct usb_ep *_ep,
247 const struct usb_endpoint_descriptor *desc)
248{
249 struct langwell_udc *dev;
250 struct langwell_ep *ep;
251 u16 max = 0;
252 unsigned long flags;
253 int i, retval = 0;
254 unsigned char zlt, ios = 0, mult = 0;
255
256 ep = container_of(_ep, struct langwell_ep, ep);
257 dev = ep->dev;
258 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
259
260 if (!_ep || !desc || ep->ep.desc
261 || desc->bDescriptorType != USB_DT_ENDPOINT)
262 return -EINVAL;
263
264 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
265 return -ESHUTDOWN;
266
267 max = usb_endpoint_maxp(desc);
268
269 /*
270 * disable HW zero length termination select
271 * driver handles zero length packet through req->req.zero
272 */
273 zlt = 1;
274
275 /*
276 * sanity check type, direction, address, and then
277 * initialize the endpoint capabilities fields in dQH
278 */
279 switch (usb_endpoint_type(desc)) {
280 case USB_ENDPOINT_XFER_CONTROL:
281 ios = 1;
282 break;
283 case USB_ENDPOINT_XFER_BULK:
284 if ((dev->gadget.speed == USB_SPEED_HIGH
285 && max != 512)
286 || (dev->gadget.speed == USB_SPEED_FULL
287 && max > 64)) {
288 goto done;
289 }
290 break;
291 case USB_ENDPOINT_XFER_INT:
292 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
293 goto done;
294
295 switch (dev->gadget.speed) {
296 case USB_SPEED_HIGH:
297 if (max <= 1024)
298 break;
299 case USB_SPEED_FULL:
300 if (max <= 64)
301 break;
302 default:
303 if (max <= 8)
304 break;
305 goto done;
306 }
307 break;
308 case USB_ENDPOINT_XFER_ISOC:
309 if (strstr(ep->ep.name, "-bulk")
310 || strstr(ep->ep.name, "-int"))
311 goto done;
312
313 switch (dev->gadget.speed) {
314 case USB_SPEED_HIGH:
315 if (max <= 1024)
316 break;
317 case USB_SPEED_FULL:
318 if (max <= 1023)
319 break;
320 default:
321 goto done;
322 }
323 /*
324 * FIXME:
325 * calculate transactions needed for high bandwidth iso
326 */
327 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
328 max = max & 0x8ff; /* bit 0~10 */
329 /* 3 transactions at most */
330 if (mult > 3)
331 goto done;
332 break;
333 default:
334 goto done;
335 }
336
337 spin_lock_irqsave(&dev->lock, flags);
338
339 ep->ep.maxpacket = max;
340 ep->ep.desc = desc;
341 ep->stopped = 0;
342 ep->ep_num = usb_endpoint_num(desc);
343
344 /* ep_type */
345 ep->ep_type = usb_endpoint_type(desc);
346
347 /* configure endpoint control registers */
348 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
349
350 /* configure endpoint capabilities in dQH */
351 i = ep->ep_num * 2 + is_in(ep);
352 ep->dqh = &dev->ep_dqh[i];
353 ep->dqh->dqh_ios = ios;
354 ep->dqh->dqh_mpl = cpu_to_le16(max);
355 ep->dqh->dqh_zlt = zlt;
356 ep->dqh->dqh_mult = mult;
357 ep->dqh->dtd_next = DTD_TERM;
358
359 dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
360 _ep->name,
361 ep->ep_num,
362 DIR_STRING(ep),
363 type_string(desc),
364 max);
365
366 spin_unlock_irqrestore(&dev->lock, flags);
367done:
368 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
369 return retval;
370}
371
372
373/*-------------------------------------------------------------------------*/
374
375/* retire a request */
376static void done(struct langwell_ep *ep, struct langwell_request *req,
377 int status)
378{
379 struct langwell_udc *dev = ep->dev;
380 unsigned stopped = ep->stopped;
381 struct langwell_dtd *curr_dtd, *next_dtd;
382 int i;
383
384 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
385
386 /* remove the req from ep->queue */
387 list_del_init(&req->queue);
388
389 if (req->req.status == -EINPROGRESS)
390 req->req.status = status;
391 else
392 status = req->req.status;
393
394 /* free dTD for the request */
395 next_dtd = req->head;
396 for (i = 0; i < req->dtd_count; i++) {
397 curr_dtd = next_dtd;
398 if (i != req->dtd_count - 1)
399 next_dtd = curr_dtd->next_dtd_virt;
400 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
401 }
402
403 usb_gadget_unmap_request(&dev->gadget, &req->req, is_in(ep));
404
405 if (status != -ESHUTDOWN)
406 dev_dbg(&dev->pdev->dev,
407 "complete %s, req %p, stat %d, len %u/%u\n",
408 ep->ep.name, &req->req, status,
409 req->req.actual, req->req.length);
410
411 /* don't modify queue heads during completion callback */
412 ep->stopped = 1;
413
414 spin_unlock(&dev->lock);
415 /* complete routine from gadget driver */
416 if (req->req.complete)
417 req->req.complete(&ep->ep, &req->req);
418
419 spin_lock(&dev->lock);
420 ep->stopped = stopped;
421
422 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
423}
424
425
426static void langwell_ep_fifo_flush(struct usb_ep *_ep);
427
428/* delete all endpoint requests, called with spinlock held */
429static void nuke(struct langwell_ep *ep, int status)
430{
431 /* called with spinlock held */
432 ep->stopped = 1;
433
434 /* endpoint fifo flush */
435 if (&ep->ep && ep->ep.desc)
436 langwell_ep_fifo_flush(&ep->ep);
437
438 while (!list_empty(&ep->queue)) {
439 struct langwell_request *req = NULL;
440 req = list_entry(ep->queue.next, struct langwell_request,
441 queue);
442 done(ep, req, status);
443 }
444}
445
446
447/*-------------------------------------------------------------------------*/
448
449/* endpoint is no longer usable */
450static int langwell_ep_disable(struct usb_ep *_ep)
451{
452 struct langwell_ep *ep;
453 unsigned long flags;
454 struct langwell_udc *dev;
455 int ep_num;
456 u32 endptctrl;
457
458 ep = container_of(_ep, struct langwell_ep, ep);
459 dev = ep->dev;
460 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
461
462 if (!_ep || !ep->ep.desc)
463 return -EINVAL;
464
465 spin_lock_irqsave(&dev->lock, flags);
466
467 /* disable endpoint control register */
468 ep_num = ep->ep_num;
469 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
470 if (is_in(ep))
471 endptctrl &= ~EPCTRL_TXE;
472 else
473 endptctrl &= ~EPCTRL_RXE;
474 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
475
476 /* nuke all pending requests (does flush) */
477 nuke(ep, -ESHUTDOWN);
478
479 ep->ep.desc = NULL;
480 ep->stopped = 1;
481
482 spin_unlock_irqrestore(&dev->lock, flags);
483
484 dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
485 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
486
487 return 0;
488}
489
490
491/* allocate a request object to use with this endpoint */
492static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
493 gfp_t gfp_flags)
494{
495 struct langwell_ep *ep;
496 struct langwell_udc *dev;
497 struct langwell_request *req = NULL;
498
499 if (!_ep)
500 return NULL;
501
502 ep = container_of(_ep, struct langwell_ep, ep);
503 dev = ep->dev;
504 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
505
506 req = kzalloc(sizeof(*req), gfp_flags);
507 if (!req)
508 return NULL;
509
510 req->req.dma = DMA_ADDR_INVALID;
511 INIT_LIST_HEAD(&req->queue);
512
513 dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
514 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
515 return &req->req;
516}
517
518
519/* free a request object */
520static void langwell_free_request(struct usb_ep *_ep,
521 struct usb_request *_req)
522{
523 struct langwell_ep *ep;
524 struct langwell_udc *dev;
525 struct langwell_request *req = NULL;
526
527 ep = container_of(_ep, struct langwell_ep, ep);
528 dev = ep->dev;
529 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
530
531 if (!_ep || !_req)
532 return;
533
534 req = container_of(_req, struct langwell_request, req);
535 WARN_ON(!list_empty(&req->queue));
536
537 if (_req)
538 kfree(req);
539
540 dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
541 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
542}
543
544
545/*-------------------------------------------------------------------------*/
546
547/* queue dTD and PRIME endpoint */
548static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
549{
550 u32 bit_mask, usbcmd, endptstat, dtd_dma;
551 u8 dtd_status;
552 int i;
553 struct langwell_dqh *dqh;
554 struct langwell_udc *dev;
555
556 dev = ep->dev;
557 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
558
559 i = ep->ep_num * 2 + is_in(ep);
560 dqh = &dev->ep_dqh[i];
561
562 if (ep->ep_num)
563 dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
564 else
565 /* ep0 */
566 dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
567
568 dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
569 i, &(dev->ep_dqh[i]));
570
571 bit_mask = is_in(ep) ?
572 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
573
574 dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
575
576 /* check if the pipe is empty */
577 if (!(list_empty(&ep->queue))) {
578 /* add dTD to the end of linked list */
579 struct langwell_request *lastreq;
580 lastreq = list_entry(ep->queue.prev,
581 struct langwell_request, queue);
582
583 lastreq->tail->dtd_next =
584 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
585
586 /* read prime bit, if 1 goto out */
587 if (readl(&dev->op_regs->endptprime) & bit_mask)
588 goto out;
589
590 do {
591 /* set ATDTW bit in USBCMD */
592 usbcmd = readl(&dev->op_regs->usbcmd);
593 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
594
595 /* read correct status bit */
596 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
597
598 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
599
600 /* write ATDTW bit to 0 */
601 usbcmd = readl(&dev->op_regs->usbcmd);
602 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
603
604 if (endptstat)
605 goto out;
606 }
607
608 /* write dQH next pointer and terminate bit to 0 */
609 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
610 dqh->dtd_next = cpu_to_le32(dtd_dma);
611
612 /* clear active and halt bit */
613 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
614 dqh->dtd_status &= dtd_status;
615 dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
616
617 /* ensure that updates to the dQH will occur before priming */
618 wmb();
619
620 /* write 1 to endptprime register to PRIME endpoint */
621 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
622 dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
623 writel(bit_mask, &dev->op_regs->endptprime);
624out:
625 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
626 return 0;
627}
628
629
630/* fill in the dTD structure to build a transfer descriptor */
631static struct langwell_dtd *build_dtd(struct langwell_request *req,
632 unsigned *length, dma_addr_t *dma, int *is_last)
633{
634 u32 buf_ptr;
635 struct langwell_dtd *dtd;
636 struct langwell_udc *dev;
637 int i;
638
639 dev = req->ep->dev;
640 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
641
642 /* the maximum transfer length, up to 16k bytes */
643 *length = min(req->req.length - req->req.actual,
644 (unsigned)DTD_MAX_TRANSFER_LENGTH);
645
646 /* create dTD dma_pool resource */
647 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
648 if (dtd == NULL)
649 return dtd;
650 dtd->dtd_dma = *dma;
651
652 /* initialize buffer page pointers */
653 buf_ptr = (u32)(req->req.dma + req->req.actual);
654 for (i = 0; i < 5; i++)
655 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
656
657 req->req.actual += *length;
658
659 /* fill in total bytes with transfer size */
660 dtd->dtd_total = cpu_to_le16(*length);
661 dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
662
663 /* set is_last flag if req->req.zero is set or not */
664 if (req->req.zero) {
665 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
666 *is_last = 1;
667 else
668 *is_last = 0;
669 } else if (req->req.length == req->req.actual) {
670 *is_last = 1;
671 } else
672 *is_last = 0;
673
674 if (*is_last == 0)
675 dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
676
677 /* set interrupt on complete bit for the last dTD */
678 if (*is_last && !req->req.no_interrupt)
679 dtd->dtd_ioc = 1;
680
681 /* set multiplier override 0 for non-ISO and non-TX endpoint */
682 dtd->dtd_multo = 0;
683
684 /* set the active bit of status field to 1 */
685 dtd->dtd_status = DTD_STS_ACTIVE;
686 dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
687 dtd->dtd_status);
688
689 dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
690 *length, (int)*dma);
691 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
692 return dtd;
693}
694
695
696/* generate dTD linked list for a request */
697static int req_to_dtd(struct langwell_request *req)
698{
699 unsigned count;
700 int is_last, is_first = 1;
701 struct langwell_dtd *dtd, *last_dtd = NULL;
702 struct langwell_udc *dev;
703 dma_addr_t dma;
704
705 dev = req->ep->dev;
706 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
707 do {
708 dtd = build_dtd(req, &count, &dma, &is_last);
709 if (dtd == NULL)
710 return -ENOMEM;
711
712 if (is_first) {
713 is_first = 0;
714 req->head = dtd;
715 } else {
716 last_dtd->dtd_next = cpu_to_le32(dma);
717 last_dtd->next_dtd_virt = dtd;
718 }
719 last_dtd = dtd;
720 req->dtd_count++;
721 } while (!is_last);
722
723 /* set terminate bit to 1 for the last dTD */
724 dtd->dtd_next = DTD_TERM;
725
726 req->tail = dtd;
727
728 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
729 return 0;
730}
731
732/*-------------------------------------------------------------------------*/
733
734/* queue (submits) an I/O requests to an endpoint */
735static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
736 gfp_t gfp_flags)
737{
738 struct langwell_request *req;
739 struct langwell_ep *ep;
740 struct langwell_udc *dev;
741 unsigned long flags;
742 int is_iso = 0;
743 int ret;
744
745 /* always require a cpu-view buffer */
746 req = container_of(_req, struct langwell_request, req);
747 ep = container_of(_ep, struct langwell_ep, ep);
748
749 if (!_req || !_req->complete || !_req->buf
750 || !list_empty(&req->queue)) {
751 return -EINVAL;
752 }
753
754 if (unlikely(!_ep || !ep->ep.desc))
755 return -EINVAL;
756
757 dev = ep->dev;
758 req->ep = ep;
759 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
760
761 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
762 if (req->req.length > ep->ep.maxpacket)
763 return -EMSGSIZE;
764 is_iso = 1;
765 }
766
767 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
768 return -ESHUTDOWN;
769
770 /* set up dma mapping */
771 ret = usb_gadget_map_request(&dev->gadget, &req->req, is_in(ep));
772 if (ret)
773 return ret;
774
775 dev_dbg(&dev->pdev->dev,
776 "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
777 _ep->name,
778 _req, _req->length, _req->buf, (int)_req->dma);
779
780 _req->status = -EINPROGRESS;
781 _req->actual = 0;
782 req->dtd_count = 0;
783
784 spin_lock_irqsave(&dev->lock, flags);
785
786 /* build and put dTDs to endpoint queue */
787 if (!req_to_dtd(req)) {
788 queue_dtd(ep, req);
789 } else {
790 spin_unlock_irqrestore(&dev->lock, flags);
791 return -ENOMEM;
792 }
793
794 /* update ep0 state */
795 if (ep->ep_num == 0)
796 dev->ep0_state = DATA_STATE_XMIT;
797
798 if (likely(req != NULL)) {
799 list_add_tail(&req->queue, &ep->queue);
800 dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
801 }
802
803 spin_unlock_irqrestore(&dev->lock, flags);
804
805 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
806 return 0;
807}
808
809
810/* dequeue (cancels, unlinks) an I/O request from an endpoint */
811static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
812{
813 struct langwell_ep *ep;
814 struct langwell_udc *dev;
815 struct langwell_request *req;
816 unsigned long flags;
817 int stopped, ep_num, retval = 0;
818 u32 endptctrl;
819
820 ep = container_of(_ep, struct langwell_ep, ep);
821 dev = ep->dev;
822 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
823
824 if (!_ep || !ep->ep.desc || !_req)
825 return -EINVAL;
826
827 if (!dev->driver)
828 return -ESHUTDOWN;
829
830 spin_lock_irqsave(&dev->lock, flags);
831 stopped = ep->stopped;
832
833 /* quiesce dma while we patch the queue */
834 ep->stopped = 1;
835 ep_num = ep->ep_num;
836
837 /* disable endpoint control register */
838 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
839 if (is_in(ep))
840 endptctrl &= ~EPCTRL_TXE;
841 else
842 endptctrl &= ~EPCTRL_RXE;
843 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
844
845 /* make sure it's still queued on this endpoint */
846 list_for_each_entry(req, &ep->queue, queue) {
847 if (&req->req == _req)
848 break;
849 }
850
851 if (&req->req != _req) {
852 retval = -EINVAL;
853 goto done;
854 }
855
856 /* queue head may be partially complete. */
857 if (ep->queue.next == &req->queue) {
858 dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
859 _req->status = -ECONNRESET;
860 langwell_ep_fifo_flush(&ep->ep);
861
862 /* not the last request in endpoint queue */
863 if (likely(ep->queue.next == &req->queue)) {
864 struct langwell_dqh *dqh;
865 struct langwell_request *next_req;
866
867 dqh = ep->dqh;
868 next_req = list_entry(req->queue.next,
869 struct langwell_request, queue);
870
871 /* point the dQH to the first dTD of next request */
872 writel((u32) next_req->head, &dqh->dqh_current);
873 }
874 } else {
875 struct langwell_request *prev_req;
876
877 prev_req = list_entry(req->queue.prev,
878 struct langwell_request, queue);
879 writel(readl(&req->tail->dtd_next),
880 &prev_req->tail->dtd_next);
881 }
882
883 done(ep, req, -ECONNRESET);
884
885done:
886 /* enable endpoint again */
887 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
888 if (is_in(ep))
889 endptctrl |= EPCTRL_TXE;
890 else
891 endptctrl |= EPCTRL_RXE;
892 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
893
894 ep->stopped = stopped;
895 spin_unlock_irqrestore(&dev->lock, flags);
896
897 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
898 return retval;
899}
900
901
902/*-------------------------------------------------------------------------*/
903
904/* endpoint set/clear halt */
905static void ep_set_halt(struct langwell_ep *ep, int value)
906{
907 u32 endptctrl = 0;
908 int ep_num;
909 struct langwell_udc *dev = ep->dev;
910 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
911
912 ep_num = ep->ep_num;
913 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
914
915 /* value: 1 - set halt, 0 - clear halt */
916 if (value) {
917 /* set the stall bit */
918 if (is_in(ep))
919 endptctrl |= EPCTRL_TXS;
920 else
921 endptctrl |= EPCTRL_RXS;
922 } else {
923 /* clear the stall bit and reset data toggle */
924 if (is_in(ep)) {
925 endptctrl &= ~EPCTRL_TXS;
926 endptctrl |= EPCTRL_TXR;
927 } else {
928 endptctrl &= ~EPCTRL_RXS;
929 endptctrl |= EPCTRL_RXR;
930 }
931 }
932
933 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
934
935 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
936}
937
938
939/* set the endpoint halt feature */
940static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
941{
942 struct langwell_ep *ep;
943 struct langwell_udc *dev;
944 unsigned long flags;
945 int retval = 0;
946
947 ep = container_of(_ep, struct langwell_ep, ep);
948 dev = ep->dev;
949
950 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
951
952 if (!_ep || !ep->ep.desc)
953 return -EINVAL;
954
955 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
956 return -ESHUTDOWN;
957
958 if (usb_endpoint_xfer_isoc(ep->ep.desc))
959 return -EOPNOTSUPP;
960
961 spin_lock_irqsave(&dev->lock, flags);
962
963 /*
964 * attempt to halt IN ep will fail if any transfer requests
965 * are still queue
966 */
967 if (!list_empty(&ep->queue) && is_in(ep) && value) {
968 /* IN endpoint FIFO holds bytes */
969 dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
970 retval = -EAGAIN;
971 goto done;
972 }
973
974 /* endpoint set/clear halt */
975 if (ep->ep_num) {
976 ep_set_halt(ep, value);
977 } else { /* endpoint 0 */
978 dev->ep0_state = WAIT_FOR_SETUP;
979 dev->ep0_dir = USB_DIR_OUT;
980 }
981done:
982 spin_unlock_irqrestore(&dev->lock, flags);
983 dev_dbg(&dev->pdev->dev, "%s %s halt\n",
984 _ep->name, value ? "set" : "clear");
985 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
986 return retval;
987}
988
989
990/* set the halt feature and ignores clear requests */
991static int langwell_ep_set_wedge(struct usb_ep *_ep)
992{
993 struct langwell_ep *ep;
994 struct langwell_udc *dev;
995
996 ep = container_of(_ep, struct langwell_ep, ep);
997 dev = ep->dev;
998
999 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1000
1001 if (!_ep || !ep->ep.desc)
1002 return -EINVAL;
1003
1004 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1005 return usb_ep_set_halt(_ep);
1006}
1007
1008
1009/* flush contents of a fifo */
1010static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1011{
1012 struct langwell_ep *ep;
1013 struct langwell_udc *dev;
1014 u32 flush_bit;
1015 unsigned long timeout;
1016
1017 ep = container_of(_ep, struct langwell_ep, ep);
1018 dev = ep->dev;
1019
1020 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1021
1022 if (!_ep || !ep->ep.desc) {
1023 dev_vdbg(&dev->pdev->dev, "ep or ep->ep.desc is NULL\n");
1024 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1025 return;
1026 }
1027
1028 dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
1029 _ep->name, DIR_STRING(ep));
1030
1031 /* flush endpoint buffer */
1032 if (ep->ep_num == 0)
1033 flush_bit = (1 << 16) | 1;
1034 else if (is_in(ep))
1035 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1036 else
1037 flush_bit = 1 << ep->ep_num; /* RX */
1038
1039 /* wait until flush complete */
1040 timeout = jiffies + FLUSH_TIMEOUT;
1041 do {
1042 writel(flush_bit, &dev->op_regs->endptflush);
1043 while (readl(&dev->op_regs->endptflush)) {
1044 if (time_after(jiffies, timeout)) {
1045 dev_err(&dev->pdev->dev, "ep flush timeout\n");
1046 goto done;
1047 }
1048 cpu_relax();
1049 }
1050 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1051done:
1052 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1053}
1054
1055
1056/* endpoints operations structure */
1057static const struct usb_ep_ops langwell_ep_ops = {
1058
1059 /* configure endpoint, making it usable */
1060 .enable = langwell_ep_enable,
1061
1062 /* endpoint is no longer usable */
1063 .disable = langwell_ep_disable,
1064
1065 /* allocate a request object to use with this endpoint */
1066 .alloc_request = langwell_alloc_request,
1067
1068 /* free a request object */
1069 .free_request = langwell_free_request,
1070
1071 /* queue (submits) an I/O requests to an endpoint */
1072 .queue = langwell_ep_queue,
1073
1074 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1075 .dequeue = langwell_ep_dequeue,
1076
1077 /* set the endpoint halt feature */
1078 .set_halt = langwell_ep_set_halt,
1079
1080 /* set the halt feature and ignores clear requests */
1081 .set_wedge = langwell_ep_set_wedge,
1082
1083 /* flush contents of a fifo */
1084 .fifo_flush = langwell_ep_fifo_flush,
1085};
1086
1087
1088/*-------------------------------------------------------------------------*/
1089
1090/* device controller usb_gadget_ops structure */
1091
1092/* returns the current frame number */
1093static int langwell_get_frame(struct usb_gadget *_gadget)
1094{
1095 struct langwell_udc *dev;
1096 u16 retval;
1097
1098 if (!_gadget)
1099 return -ENODEV;
1100
1101 dev = container_of(_gadget, struct langwell_udc, gadget);
1102 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1103
1104 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1105
1106 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1107 return retval;
1108}
1109
1110
1111/* enter or exit PHY low power state */
1112static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
1113{
1114 u32 devlc;
1115 u8 devlc_byte2;
1116 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1117
1118 devlc = readl(&dev->op_regs->devlc);
1119 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1120
1121 if (flag)
1122 devlc |= LPM_PHCD;
1123 else
1124 devlc &= ~LPM_PHCD;
1125
1126 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1127 devlc_byte2 = (devlc >> 16) & 0xff;
1128 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1129
1130 devlc = readl(&dev->op_regs->devlc);
1131 dev_vdbg(&dev->pdev->dev,
1132 "%s PHY low power suspend, devlc = 0x%08x\n",
1133 flag ? "enter" : "exit", devlc);
1134}
1135
1136
1137/* tries to wake up the host connected to this gadget */
1138static int langwell_wakeup(struct usb_gadget *_gadget)
1139{
1140 struct langwell_udc *dev;
1141 u32 portsc1;
1142 unsigned long flags;
1143
1144 if (!_gadget)
1145 return 0;
1146
1147 dev = container_of(_gadget, struct langwell_udc, gadget);
1148 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1149
1150 /* remote wakeup feature not enabled by host */
1151 if (!dev->remote_wakeup) {
1152 dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
1153 return -ENOTSUPP;
1154 }
1155
1156 spin_lock_irqsave(&dev->lock, flags);
1157
1158 portsc1 = readl(&dev->op_regs->portsc1);
1159 if (!(portsc1 & PORTS_SUSP)) {
1160 spin_unlock_irqrestore(&dev->lock, flags);
1161 return 0;
1162 }
1163
1164 /* LPM L1 to L0 or legacy remote wakeup */
1165 if (dev->lpm && dev->lpm_state == LPM_L1)
1166 dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
1167 else
1168 dev_info(&dev->pdev->dev, "device remote wakeup\n");
1169
1170 /* exit PHY low power suspend */
1171 if (dev->pdev->device != 0x0829)
1172 langwell_phy_low_power(dev, 0);
1173
1174 /* force port resume */
1175 portsc1 |= PORTS_FPR;
1176 writel(portsc1, &dev->op_regs->portsc1);
1177
1178 spin_unlock_irqrestore(&dev->lock, flags);
1179
1180 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1181 return 0;
1182}
1183
1184
1185/* notify controller that VBUS is powered or not */
1186static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1187{
1188 struct langwell_udc *dev;
1189 unsigned long flags;
1190 u32 usbcmd;
1191
1192 if (!_gadget)
1193 return -ENODEV;
1194
1195 dev = container_of(_gadget, struct langwell_udc, gadget);
1196 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1197
1198 spin_lock_irqsave(&dev->lock, flags);
1199 dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
1200 is_active ? "on" : "off");
1201
1202 dev->vbus_active = (is_active != 0);
1203 if (dev->driver && dev->softconnected && dev->vbus_active) {
1204 usbcmd = readl(&dev->op_regs->usbcmd);
1205 usbcmd |= CMD_RUNSTOP;
1206 writel(usbcmd, &dev->op_regs->usbcmd);
1207 } else {
1208 usbcmd = readl(&dev->op_regs->usbcmd);
1209 usbcmd &= ~CMD_RUNSTOP;
1210 writel(usbcmd, &dev->op_regs->usbcmd);
1211 }
1212
1213 spin_unlock_irqrestore(&dev->lock, flags);
1214
1215 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1216 return 0;
1217}
1218
1219
1220/* constrain controller's VBUS power usage */
1221static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1222{
1223 struct langwell_udc *dev;
1224
1225 if (!_gadget)
1226 return -ENODEV;
1227
1228 dev = container_of(_gadget, struct langwell_udc, gadget);
1229 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1230
1231 if (dev->transceiver) {
1232 dev_vdbg(&dev->pdev->dev, "usb_phy_set_power\n");
1233 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1234 return usb_phy_set_power(dev->transceiver, mA);
1235 }
1236
1237 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1238 return -ENOTSUPP;
1239}
1240
1241
1242/* D+ pullup, software-controlled connect/disconnect to USB host */
1243static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1244{
1245 struct langwell_udc *dev;
1246 u32 usbcmd;
1247 unsigned long flags;
1248
1249 if (!_gadget)
1250 return -ENODEV;
1251
1252 dev = container_of(_gadget, struct langwell_udc, gadget);
1253
1254 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1255
1256 spin_lock_irqsave(&dev->lock, flags);
1257 dev->softconnected = (is_on != 0);
1258
1259 if (dev->driver && dev->softconnected && dev->vbus_active) {
1260 usbcmd = readl(&dev->op_regs->usbcmd);
1261 usbcmd |= CMD_RUNSTOP;
1262 writel(usbcmd, &dev->op_regs->usbcmd);
1263 } else {
1264 usbcmd = readl(&dev->op_regs->usbcmd);
1265 usbcmd &= ~CMD_RUNSTOP;
1266 writel(usbcmd, &dev->op_regs->usbcmd);
1267 }
1268 spin_unlock_irqrestore(&dev->lock, flags);
1269
1270 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1271 return 0;
1272}
1273
1274static int langwell_start(struct usb_gadget *g,
1275 struct usb_gadget_driver *driver);
1276
1277static int langwell_stop(struct usb_gadget *g,
1278 struct usb_gadget_driver *driver);
1279
1280/* device controller usb_gadget_ops structure */
1281static const struct usb_gadget_ops langwell_ops = {
1282
1283 /* returns the current frame number */
1284 .get_frame = langwell_get_frame,
1285
1286 /* tries to wake up the host connected to this gadget */
1287 .wakeup = langwell_wakeup,
1288
1289 /* set the device selfpowered feature, always selfpowered */
1290 /* .set_selfpowered = langwell_set_selfpowered, */
1291
1292 /* notify controller that VBUS is powered or not */
1293 .vbus_session = langwell_vbus_session,
1294
1295 /* constrain controller's VBUS power usage */
1296 .vbus_draw = langwell_vbus_draw,
1297
1298 /* D+ pullup, software-controlled connect/disconnect to USB host */
1299 .pullup = langwell_pullup,
1300
1301 .udc_start = langwell_start,
1302 .udc_stop = langwell_stop,
1303};
1304
1305
1306/*-------------------------------------------------------------------------*/
1307
1308/* device controller operations */
1309
1310/* reset device controller */
1311static int langwell_udc_reset(struct langwell_udc *dev)
1312{
1313 u32 usbcmd, usbmode, devlc, endpointlistaddr;
1314 u8 devlc_byte0, devlc_byte2;
1315 unsigned long timeout;
1316
1317 if (!dev)
1318 return -EINVAL;
1319
1320 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1321
1322 /* set controller to stop state */
1323 usbcmd = readl(&dev->op_regs->usbcmd);
1324 usbcmd &= ~CMD_RUNSTOP;
1325 writel(usbcmd, &dev->op_regs->usbcmd);
1326
1327 /* reset device controller */
1328 usbcmd = readl(&dev->op_regs->usbcmd);
1329 usbcmd |= CMD_RST;
1330 writel(usbcmd, &dev->op_regs->usbcmd);
1331
1332 /* wait for reset to complete */
1333 timeout = jiffies + RESET_TIMEOUT;
1334 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1335 if (time_after(jiffies, timeout)) {
1336 dev_err(&dev->pdev->dev, "device reset timeout\n");
1337 return -ETIMEDOUT;
1338 }
1339 cpu_relax();
1340 }
1341
1342 /* set controller to device mode */
1343 usbmode = readl(&dev->op_regs->usbmode);
1344 usbmode |= MODE_DEVICE;
1345
1346 /* turn setup lockout off, require setup tripwire in usbcmd */
1347 usbmode |= MODE_SLOM;
1348
1349 writel(usbmode, &dev->op_regs->usbmode);
1350 usbmode = readl(&dev->op_regs->usbmode);
1351 dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
1352
1353 /* Write-Clear setup status */
1354 writel(0, &dev->op_regs->usbsts);
1355
1356 /* if support USB LPM, ACK all LPM token */
1357 if (dev->lpm) {
1358 devlc = readl(&dev->op_regs->devlc);
1359 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1360 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1361 devlc &= ~LPM_STL; /* don't STALL LPM token */
1362 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
1363 devlc_byte0 = devlc & 0xff;
1364 devlc_byte2 = (devlc >> 16) & 0xff;
1365 writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
1366 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1367 devlc = readl(&dev->op_regs->devlc);
1368 dev_vdbg(&dev->pdev->dev,
1369 "ACK LPM token, devlc = 0x%08x\n", devlc);
1370 }
1371
1372 /* fill endpointlistaddr register */
1373 endpointlistaddr = dev->ep_dqh_dma;
1374 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1375 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1376
1377 dev_vdbg(&dev->pdev->dev,
1378 "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1379 dev->ep_dqh, endpointlistaddr,
1380 readl(&dev->op_regs->endpointlistaddr));
1381 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1382 return 0;
1383}
1384
1385
1386/* reinitialize device controller endpoints */
1387static int eps_reinit(struct langwell_udc *dev)
1388{
1389 struct langwell_ep *ep;
1390 char name[14];
1391 int i;
1392
1393 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1394
1395 /* initialize ep0 */
1396 ep = &dev->ep[0];
1397 ep->dev = dev;
1398 strncpy(ep->name, "ep0", sizeof(ep->name));
1399 ep->ep.name = ep->name;
1400 ep->ep.ops = &langwell_ep_ops;
1401 ep->stopped = 0;
1402 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1403 ep->ep_num = 0;
1404 ep->ep.desc = &langwell_ep0_desc;
1405 INIT_LIST_HEAD(&ep->queue);
1406
1407 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1408
1409 /* initialize other endpoints */
1410 for (i = 2; i < dev->ep_max; i++) {
1411 ep = &dev->ep[i];
1412 if (i % 2)
1413 snprintf(name, sizeof(name), "ep%din", i / 2);
1414 else
1415 snprintf(name, sizeof(name), "ep%dout", i / 2);
1416 ep->dev = dev;
1417 strncpy(ep->name, name, sizeof(ep->name));
1418 ep->ep.name = ep->name;
1419
1420 ep->ep.ops = &langwell_ep_ops;
1421 ep->stopped = 0;
1422 ep->ep.maxpacket = (unsigned short) ~0;
1423 ep->ep_num = i / 2;
1424
1425 INIT_LIST_HEAD(&ep->queue);
1426 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1427 }
1428
1429 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1430 return 0;
1431}
1432
1433
1434/* enable interrupt and set controller to run state */
1435static void langwell_udc_start(struct langwell_udc *dev)
1436{
1437 u32 usbintr, usbcmd;
1438 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1439
1440 /* enable interrupts */
1441 usbintr = INTR_ULPIE /* ULPI */
1442 | INTR_SLE /* suspend */
1443 /* | INTR_SRE SOF received */
1444 | INTR_URE /* USB reset */
1445 | INTR_AAE /* async advance */
1446 | INTR_SEE /* system error */
1447 | INTR_FRE /* frame list rollover */
1448 | INTR_PCE /* port change detect */
1449 | INTR_UEE /* USB error interrupt */
1450 | INTR_UE; /* USB interrupt */
1451 writel(usbintr, &dev->op_regs->usbintr);
1452
1453 /* clear stopped bit */
1454 dev->stopped = 0;
1455
1456 /* set controller to run */
1457 usbcmd = readl(&dev->op_regs->usbcmd);
1458 usbcmd |= CMD_RUNSTOP;
1459 writel(usbcmd, &dev->op_regs->usbcmd);
1460
1461 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1462}
1463
1464
1465/* disable interrupt and set controller to stop state */
1466static void langwell_udc_stop(struct langwell_udc *dev)
1467{
1468 u32 usbcmd;
1469
1470 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1471
1472 /* disable all interrupts */
1473 writel(0, &dev->op_regs->usbintr);
1474
1475 /* set stopped bit */
1476 dev->stopped = 1;
1477
1478 /* set controller to stop state */
1479 usbcmd = readl(&dev->op_regs->usbcmd);
1480 usbcmd &= ~CMD_RUNSTOP;
1481 writel(usbcmd, &dev->op_regs->usbcmd);
1482
1483 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1484}
1485
1486
1487/* stop all USB activities */
1488static void stop_activity(struct langwell_udc *dev)
1489{
1490 struct langwell_ep *ep;
1491 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1492
1493 nuke(&dev->ep[0], -ESHUTDOWN);
1494
1495 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1496 nuke(ep, -ESHUTDOWN);
1497 }
1498
1499 /* report disconnect; the driver is already quiesced */
1500 if (dev->driver) {
1501 spin_unlock(&dev->lock);
1502 dev->driver->disconnect(&dev->gadget);
1503 spin_lock(&dev->lock);
1504 }
1505
1506 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1507}
1508
1509
1510/*-------------------------------------------------------------------------*/
1511
1512/* device "function" sysfs attribute file */
1513static ssize_t show_function(struct device *_dev,
1514 struct device_attribute *attr, char *buf)
1515{
1516 struct langwell_udc *dev = dev_get_drvdata(_dev);
1517
1518 if (!dev->driver || !dev->driver->function
1519 || strlen(dev->driver->function) > PAGE_SIZE)
1520 return 0;
1521
1522 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1523}
1524static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1525
1526
1527static inline enum usb_device_speed lpm_device_speed(u32 reg)
1528{
1529 switch (LPM_PSPD(reg)) {
1530 case LPM_SPEED_HIGH:
1531 return USB_SPEED_HIGH;
1532 case LPM_SPEED_FULL:
1533 return USB_SPEED_FULL;
1534 case LPM_SPEED_LOW:
1535 return USB_SPEED_LOW;
1536 default:
1537 return USB_SPEED_UNKNOWN;
1538 }
1539}
1540
1541/* device "langwell_udc" sysfs attribute file */
1542static ssize_t show_langwell_udc(struct device *_dev,
1543 struct device_attribute *attr, char *buf)
1544{
1545 struct langwell_udc *dev = dev_get_drvdata(_dev);
1546 struct langwell_request *req;
1547 struct langwell_ep *ep = NULL;
1548 char *next;
1549 unsigned size;
1550 unsigned t;
1551 unsigned i;
1552 unsigned long flags;
1553 u32 tmp_reg;
1554
1555 next = buf;
1556 size = PAGE_SIZE;
1557 spin_lock_irqsave(&dev->lock, flags);
1558
1559 /* driver basic information */
1560 t = scnprintf(next, size,
1561 DRIVER_DESC "\n"
1562 "%s version: %s\n"
1563 "Gadget driver: %s\n\n",
1564 driver_name, DRIVER_VERSION,
1565 dev->driver ? dev->driver->driver.name : "(none)");
1566 size -= t;
1567 next += t;
1568
1569 /* device registers */
1570 tmp_reg = readl(&dev->op_regs->usbcmd);
1571 t = scnprintf(next, size,
1572 "USBCMD reg:\n"
1573 "SetupTW: %d\n"
1574 "Run/Stop: %s\n\n",
1575 (tmp_reg & CMD_SUTW) ? 1 : 0,
1576 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1577 size -= t;
1578 next += t;
1579
1580 tmp_reg = readl(&dev->op_regs->usbsts);
1581 t = scnprintf(next, size,
1582 "USB Status Reg:\n"
1583 "Device Suspend: %d\n"
1584 "Reset Received: %d\n"
1585 "System Error: %s\n"
1586 "USB Error Interrupt: %s\n\n",
1587 (tmp_reg & STS_SLI) ? 1 : 0,
1588 (tmp_reg & STS_URI) ? 1 : 0,
1589 (tmp_reg & STS_SEI) ? "Error" : "No error",
1590 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1591 size -= t;
1592 next += t;
1593
1594 tmp_reg = readl(&dev->op_regs->usbintr);
1595 t = scnprintf(next, size,
1596 "USB Intrrupt Enable Reg:\n"
1597 "Sleep Enable: %d\n"
1598 "SOF Received Enable: %d\n"
1599 "Reset Enable: %d\n"
1600 "System Error Enable: %d\n"
1601 "Port Change Dectected Enable: %d\n"
1602 "USB Error Intr Enable: %d\n"
1603 "USB Intr Enable: %d\n\n",
1604 (tmp_reg & INTR_SLE) ? 1 : 0,
1605 (tmp_reg & INTR_SRE) ? 1 : 0,
1606 (tmp_reg & INTR_URE) ? 1 : 0,
1607 (tmp_reg & INTR_SEE) ? 1 : 0,
1608 (tmp_reg & INTR_PCE) ? 1 : 0,
1609 (tmp_reg & INTR_UEE) ? 1 : 0,
1610 (tmp_reg & INTR_UE) ? 1 : 0);
1611 size -= t;
1612 next += t;
1613
1614 tmp_reg = readl(&dev->op_regs->frindex);
1615 t = scnprintf(next, size,
1616 "USB Frame Index Reg:\n"
1617 "Frame Number is 0x%08x\n\n",
1618 (tmp_reg & FRINDEX_MASK));
1619 size -= t;
1620 next += t;
1621
1622 tmp_reg = readl(&dev->op_regs->deviceaddr);
1623 t = scnprintf(next, size,
1624 "USB Device Address Reg:\n"
1625 "Device Addr is 0x%x\n\n",
1626 USBADR(tmp_reg));
1627 size -= t;
1628 next += t;
1629
1630 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1631 t = scnprintf(next, size,
1632 "USB Endpoint List Address Reg:\n"
1633 "Endpoint List Pointer is 0x%x\n\n",
1634 EPBASE(tmp_reg));
1635 size -= t;
1636 next += t;
1637
1638 tmp_reg = readl(&dev->op_regs->portsc1);
1639 t = scnprintf(next, size,
1640 "USB Port Status & Control Reg:\n"
1641 "Port Reset: %s\n"
1642 "Port Suspend Mode: %s\n"
1643 "Over-current Change: %s\n"
1644 "Port Enable/Disable Change: %s\n"
1645 "Port Enabled/Disabled: %s\n"
1646 "Current Connect Status: %s\n"
1647 "LPM Suspend Status: %s\n\n",
1648 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1649 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1650 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1651 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1652 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
1653 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
1654 (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
1655 size -= t;
1656 next += t;
1657
1658 tmp_reg = readl(&dev->op_regs->devlc);
1659 t = scnprintf(next, size,
1660 "Device LPM Control Reg:\n"
1661 "Parallel Transceiver : %d\n"
1662 "Serial Transceiver : %d\n"
1663 "Port Speed: %s\n"
1664 "Port Force Full Speed Connenct: %s\n"
1665 "PHY Low Power Suspend Clock: %s\n"
1666 "BmAttributes: %d\n\n",
1667 LPM_PTS(tmp_reg),
1668 (tmp_reg & LPM_STS) ? 1 : 0,
1669 usb_speed_string(lpm_device_speed(tmp_reg)),
1670 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1671 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1672 LPM_BA(tmp_reg));
1673 size -= t;
1674 next += t;
1675
1676 tmp_reg = readl(&dev->op_regs->usbmode);
1677 t = scnprintf(next, size,
1678 "USB Mode Reg:\n"
1679 "Controller Mode is : %s\n\n", ({
1680 char *s;
1681 switch (MODE_CM(tmp_reg)) {
1682 case MODE_IDLE:
1683 s = "Idle"; break;
1684 case MODE_DEVICE:
1685 s = "Device Controller"; break;
1686 case MODE_HOST:
1687 s = "Host Controller"; break;
1688 default:
1689 s = "None"; break;
1690 }
1691 s;
1692 }));
1693 size -= t;
1694 next += t;
1695
1696 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1697 t = scnprintf(next, size,
1698 "Endpoint Setup Status Reg:\n"
1699 "SETUP on ep 0x%04x\n\n",
1700 tmp_reg & SETUPSTAT_MASK);
1701 size -= t;
1702 next += t;
1703
1704 for (i = 0; i < dev->ep_max / 2; i++) {
1705 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1706 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1707 i, tmp_reg);
1708 size -= t;
1709 next += t;
1710 }
1711 tmp_reg = readl(&dev->op_regs->endptprime);
1712 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1713 size -= t;
1714 next += t;
1715
1716 /* langwell_udc, langwell_ep, langwell_request structure information */
1717 ep = &dev->ep[0];
1718 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1719 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1720 size -= t;
1721 next += t;
1722
1723 if (list_empty(&ep->queue)) {
1724 t = scnprintf(next, size, "its req queue is empty\n\n");
1725 size -= t;
1726 next += t;
1727 } else {
1728 list_for_each_entry(req, &ep->queue, queue) {
1729 t = scnprintf(next, size,
1730 "req %p actual 0x%x length 0x%x buf %p\n",
1731 &req->req, req->req.actual,
1732 req->req.length, req->req.buf);
1733 size -= t;
1734 next += t;
1735 }
1736 }
1737 /* other gadget->eplist ep */
1738 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1739 if (ep->ep.desc) {
1740 t = scnprintf(next, size,
1741 "\n%s MaxPacketSize: 0x%x, "
1742 "ep_num: %d\n",
1743 ep->ep.name, ep->ep.maxpacket,
1744 ep->ep_num);
1745 size -= t;
1746 next += t;
1747
1748 if (list_empty(&ep->queue)) {
1749 t = scnprintf(next, size,
1750 "its req queue is empty\n\n");
1751 size -= t;
1752 next += t;
1753 } else {
1754 list_for_each_entry(req, &ep->queue, queue) {
1755 t = scnprintf(next, size,
1756 "req %p actual 0x%x length "
1757 "0x%x buf %p\n",
1758 &req->req, req->req.actual,
1759 req->req.length, req->req.buf);
1760 size -= t;
1761 next += t;
1762 }
1763 }
1764 }
1765 }
1766
1767 spin_unlock_irqrestore(&dev->lock, flags);
1768 return PAGE_SIZE - size;
1769}
1770static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1771
1772
1773/* device "remote_wakeup" sysfs attribute file */
1774static ssize_t store_remote_wakeup(struct device *_dev,
1775 struct device_attribute *attr, const char *buf, size_t count)
1776{
1777 struct langwell_udc *dev = dev_get_drvdata(_dev);
1778 unsigned long flags;
1779 ssize_t rc = count;
1780
1781 if (count > 2)
1782 return -EINVAL;
1783
1784 if (count > 0 && buf[count-1] == '\n')
1785 ((char *) buf)[count-1] = 0;
1786
1787 if (buf[0] != '1')
1788 return -EINVAL;
1789
1790 /* force remote wakeup enabled in case gadget driver doesn't support */
1791 spin_lock_irqsave(&dev->lock, flags);
1792 dev->remote_wakeup = 1;
1793 dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1794 spin_unlock_irqrestore(&dev->lock, flags);
1795
1796 langwell_wakeup(&dev->gadget);
1797
1798 return rc;
1799}
1800static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
1801
1802
1803/*-------------------------------------------------------------------------*/
1804
1805/*
1806 * when a driver is successfully registered, it will receive
1807 * control requests including set_configuration(), which enables
1808 * non-control requests. then usb traffic follows until a
1809 * disconnect is reported. then a host may connect again, or
1810 * the driver might get unbound.
1811 */
1812
1813static int langwell_start(struct usb_gadget *g,
1814 struct usb_gadget_driver *driver)
1815{
1816 struct langwell_udc *dev = gadget_to_langwell(g);
1817 unsigned long flags;
1818 int retval;
1819
1820 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1821
1822 spin_lock_irqsave(&dev->lock, flags);
1823
1824 /* hook up the driver ... */
1825 driver->driver.bus = NULL;
1826 dev->driver = driver;
1827 dev->gadget.dev.driver = &driver->driver;
1828
1829 spin_unlock_irqrestore(&dev->lock, flags);
1830
1831 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1832 if (retval)
1833 goto err;
1834
1835 dev->usb_state = USB_STATE_ATTACHED;
1836 dev->ep0_state = WAIT_FOR_SETUP;
1837 dev->ep0_dir = USB_DIR_OUT;
1838
1839 /* enable interrupt and set controller to run state */
1840 if (dev->got_irq)
1841 langwell_udc_start(dev);
1842
1843 dev_vdbg(&dev->pdev->dev,
1844 "After langwell_udc_start(), print all registers:\n");
1845 print_all_registers(dev);
1846
1847 dev_info(&dev->pdev->dev, "register driver: %s\n",
1848 driver->driver.name);
1849 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1850
1851 return 0;
1852
1853err:
1854 dev->gadget.dev.driver = NULL;
1855 dev->driver = NULL;
1856
1857 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1858
1859 return retval;
1860}
1861
1862/* unregister gadget driver */
1863static int langwell_stop(struct usb_gadget *g,
1864 struct usb_gadget_driver *driver)
1865{
1866 struct langwell_udc *dev = gadget_to_langwell(g);
1867 unsigned long flags;
1868
1869 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1870
1871 /* exit PHY low power suspend */
1872 if (dev->pdev->device != 0x0829)
1873 langwell_phy_low_power(dev, 0);
1874
1875 /* unbind OTG transceiver */
1876 if (dev->transceiver)
1877 (void)otg_set_peripheral(dev->transceiver->otg, 0);
1878
1879 /* disable interrupt and set controller to stop state */
1880 langwell_udc_stop(dev);
1881
1882 dev->usb_state = USB_STATE_ATTACHED;
1883 dev->ep0_state = WAIT_FOR_SETUP;
1884 dev->ep0_dir = USB_DIR_OUT;
1885
1886 spin_lock_irqsave(&dev->lock, flags);
1887
1888 /* stop all usb activities */
1889 dev->gadget.speed = USB_SPEED_UNKNOWN;
1890 dev->gadget.dev.driver = NULL;
1891 dev->driver = NULL;
1892 stop_activity(dev);
1893 spin_unlock_irqrestore(&dev->lock, flags);
1894
1895 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1896
1897 dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
1898 driver->driver.name);
1899 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1900
1901 return 0;
1902}
1903
1904/*-------------------------------------------------------------------------*/
1905
1906/*
1907 * setup tripwire is used as a semaphore to ensure that the setup data
1908 * payload is extracted from a dQH without being corrupted
1909 */
1910static void setup_tripwire(struct langwell_udc *dev)
1911{
1912 u32 usbcmd,
1913 endptsetupstat;
1914 unsigned long timeout;
1915 struct langwell_dqh *dqh;
1916
1917 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1918
1919 /* ep0 OUT dQH */
1920 dqh = &dev->ep_dqh[EP_DIR_OUT];
1921
1922 /* Write-Clear endptsetupstat */
1923 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1924 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1925
1926 /* wait until endptsetupstat is cleared */
1927 timeout = jiffies + SETUPSTAT_TIMEOUT;
1928 while (readl(&dev->op_regs->endptsetupstat)) {
1929 if (time_after(jiffies, timeout)) {
1930 dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
1931 break;
1932 }
1933 cpu_relax();
1934 }
1935
1936 /* while a hazard exists when setup packet arrives */
1937 do {
1938 /* set setup tripwire bit */
1939 usbcmd = readl(&dev->op_regs->usbcmd);
1940 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
1941
1942 /* copy the setup packet to local buffer */
1943 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
1944 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
1945
1946 /* Write-Clear setup tripwire bit */
1947 usbcmd = readl(&dev->op_regs->usbcmd);
1948 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
1949
1950 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1951}
1952
1953
1954/* protocol ep0 stall, will automatically be cleared on new transaction */
1955static void ep0_stall(struct langwell_udc *dev)
1956{
1957 u32 endptctrl;
1958
1959 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1960
1961 /* set TX and RX to stall */
1962 endptctrl = readl(&dev->op_regs->endptctrl[0]);
1963 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
1964 writel(endptctrl, &dev->op_regs->endptctrl[0]);
1965
1966 /* update ep0 state */
1967 dev->ep0_state = WAIT_FOR_SETUP;
1968 dev->ep0_dir = USB_DIR_OUT;
1969
1970 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
1971}
1972
1973
1974/* PRIME a status phase for ep0 */
1975static int prime_status_phase(struct langwell_udc *dev, int dir)
1976{
1977 struct langwell_request *req;
1978 struct langwell_ep *ep;
1979 int status = 0;
1980
1981 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
1982
1983 if (dir == EP_DIR_IN)
1984 dev->ep0_dir = USB_DIR_IN;
1985 else
1986 dev->ep0_dir = USB_DIR_OUT;
1987
1988 ep = &dev->ep[0];
1989 dev->ep0_state = WAIT_FOR_OUT_STATUS;
1990
1991 req = dev->status_req;
1992
1993 req->ep = ep;
1994 req->req.length = 0;
1995 req->req.status = -EINPROGRESS;
1996 req->req.actual = 0;
1997 req->req.complete = NULL;
1998 req->dtd_count = 0;
1999
2000 if (!req_to_dtd(req))
2001 status = queue_dtd(ep, req);
2002 else
2003 return -ENOMEM;
2004
2005 if (status)
2006 dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
2007
2008 list_add_tail(&req->queue, &ep->queue);
2009
2010 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2011 return status;
2012}
2013
2014
2015/* SET_ADDRESS request routine */
2016static void set_address(struct langwell_udc *dev, u16 value,
2017 u16 index, u16 length)
2018{
2019 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2020
2021 /* save the new address to device struct */
2022 dev->dev_addr = (u8) value;
2023 dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
2024
2025 /* update usb state */
2026 dev->usb_state = USB_STATE_ADDRESS;
2027
2028 /* STATUS phase */
2029 if (prime_status_phase(dev, EP_DIR_IN))
2030 ep0_stall(dev);
2031
2032 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2033}
2034
2035
2036/* return endpoint by windex */
2037static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2038 u16 wIndex)
2039{
2040 struct langwell_ep *ep;
2041 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2042
2043 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2044 return &dev->ep[0];
2045
2046 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2047 u8 bEndpointAddress;
2048 if (!ep->ep.desc)
2049 continue;
2050
2051 bEndpointAddress = ep->ep.desc->bEndpointAddress;
2052 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2053 continue;
2054
2055 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2056 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2057 return ep;
2058 }
2059
2060 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2061 return NULL;
2062}
2063
2064
2065/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2066static int ep_is_stall(struct langwell_ep *ep)
2067{
2068 struct langwell_udc *dev = ep->dev;
2069 u32 endptctrl;
2070 int retval;
2071
2072 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2073
2074 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2075 if (is_in(ep))
2076 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2077 else
2078 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2079
2080 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2081 return retval;
2082}
2083
2084
2085/* GET_STATUS request routine */
2086static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2087 u16 index, u16 length)
2088{
2089 struct langwell_request *req;
2090 struct langwell_ep *ep;
2091 u16 status_data = 0; /* 16 bits cpu view status data */
2092 int status = 0;
2093
2094 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2095
2096 ep = &dev->ep[0];
2097
2098 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2099 /* get device status */
2100 status_data = dev->dev_status;
2101 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2102 /* get interface status */
2103 status_data = 0;
2104 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2105 /* get endpoint status */
2106 struct langwell_ep *epn;
2107 epn = get_ep_by_windex(dev, index);
2108 /* stall if endpoint doesn't exist */
2109 if (!epn)
2110 goto stall;
2111
2112 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2113 }
2114
2115 dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
2116
2117 dev->ep0_dir = USB_DIR_IN;
2118
2119 /* borrow the per device status_req */
2120 req = dev->status_req;
2121
2122 /* fill in the reqest structure */
2123 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2124 req->ep = ep;
2125 req->req.length = 2;
2126 req->req.status = -EINPROGRESS;
2127 req->req.actual = 0;
2128 req->req.complete = NULL;
2129 req->dtd_count = 0;
2130
2131 /* prime the data phase */
2132 if (!req_to_dtd(req))
2133 status = queue_dtd(ep, req);
2134 else /* no mem */
2135 goto stall;
2136
2137 if (status) {
2138 dev_err(&dev->pdev->dev,
2139 "response error on GET_STATUS request\n");
2140 goto stall;
2141 }
2142
2143 list_add_tail(&req->queue, &ep->queue);
2144 dev->ep0_state = DATA_STATE_XMIT;
2145
2146 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2147 return;
2148stall:
2149 ep0_stall(dev);
2150 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2151}
2152
2153
2154/* setup packet interrupt handler */
2155static void handle_setup_packet(struct langwell_udc *dev,
2156 struct usb_ctrlrequest *setup)
2157{
2158 u16 wValue = le16_to_cpu(setup->wValue);
2159 u16 wIndex = le16_to_cpu(setup->wIndex);
2160 u16 wLength = le16_to_cpu(setup->wLength);
2161 u32 portsc1;
2162
2163 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2164
2165 /* ep0 fifo flush */
2166 nuke(&dev->ep[0], -ESHUTDOWN);
2167
2168 dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
2169 setup->bRequestType, setup->bRequest,
2170 wValue, wIndex, wLength);
2171
2172 /* RNDIS gadget delegate */
2173 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2174 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2175 goto delegate;
2176 }
2177
2178 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2179 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2180 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2181 goto delegate;
2182 }
2183
2184 /* We process some stardard setup requests here */
2185 switch (setup->bRequest) {
2186 case USB_REQ_GET_STATUS:
2187 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
2188 /* get status, DATA and STATUS phase */
2189 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2190 != (USB_DIR_IN | USB_TYPE_STANDARD))
2191 break;
2192 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2193 goto end;
2194
2195 case USB_REQ_SET_ADDRESS:
2196 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
2197 /* STATUS phase */
2198 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2199 | USB_RECIP_DEVICE))
2200 break;
2201 set_address(dev, wValue, wIndex, wLength);
2202 goto end;
2203
2204 case USB_REQ_CLEAR_FEATURE:
2205 case USB_REQ_SET_FEATURE:
2206 /* STATUS phase */
2207 {
2208 int rc = -EOPNOTSUPP;
2209 if (setup->bRequest == USB_REQ_SET_FEATURE)
2210 dev_dbg(&dev->pdev->dev,
2211 "SETUP: USB_REQ_SET_FEATURE\n");
2212 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
2213 dev_dbg(&dev->pdev->dev,
2214 "SETUP: USB_REQ_CLEAR_FEATURE\n");
2215
2216 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2217 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2218 struct langwell_ep *epn;
2219 epn = get_ep_by_windex(dev, wIndex);
2220 /* stall if endpoint doesn't exist */
2221 if (!epn) {
2222 ep0_stall(dev);
2223 goto end;
2224 }
2225
2226 if (wValue != 0 || wLength != 0
2227 || epn->ep_num > dev->ep_max)
2228 break;
2229
2230 spin_unlock(&dev->lock);
2231 rc = langwell_ep_set_halt(&epn->ep,
2232 (setup->bRequest == USB_REQ_SET_FEATURE)
2233 ? 1 : 0);
2234 spin_lock(&dev->lock);
2235
2236 } else if ((setup->bRequestType & (USB_RECIP_MASK
2237 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2238 | USB_TYPE_STANDARD)) {
2239 rc = 0;
2240 switch (wValue) {
2241 case USB_DEVICE_REMOTE_WAKEUP:
2242 if (setup->bRequest == USB_REQ_SET_FEATURE) {
2243 dev->remote_wakeup = 1;
2244 dev->dev_status |= (1 << wValue);
2245 } else {
2246 dev->remote_wakeup = 0;
2247 dev->dev_status &= ~(1 << wValue);
2248 }
2249 break;
2250 case USB_DEVICE_TEST_MODE:
2251 dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
2252 if ((wIndex & 0xff) ||
2253 (dev->gadget.speed != USB_SPEED_HIGH))
2254 ep0_stall(dev);
2255
2256 switch (wIndex >> 8) {
2257 case TEST_J:
2258 case TEST_K:
2259 case TEST_SE0_NAK:
2260 case TEST_PACKET:
2261 case TEST_FORCE_EN:
2262 if (prime_status_phase(dev, EP_DIR_IN))
2263 ep0_stall(dev);
2264 portsc1 = readl(&dev->op_regs->portsc1);
2265 portsc1 |= (wIndex & 0xf00) << 8;
2266 writel(portsc1, &dev->op_regs->portsc1);
2267 goto end;
2268 default:
2269 rc = -EOPNOTSUPP;
2270 }
2271 break;
2272 default:
2273 rc = -EOPNOTSUPP;
2274 break;
2275 }
2276
2277 if (!gadget_is_otg(&dev->gadget))
2278 break;
2279 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
2280 dev->gadget.b_hnp_enable = 1;
2281 else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2282 dev->gadget.a_hnp_support = 1;
2283 else if (setup->bRequest ==
2284 USB_DEVICE_A_ALT_HNP_SUPPORT)
2285 dev->gadget.a_alt_hnp_support = 1;
2286 else
2287 break;
2288 } else
2289 break;
2290
2291 if (rc == 0) {
2292 if (prime_status_phase(dev, EP_DIR_IN))
2293 ep0_stall(dev);
2294 }
2295 goto end;
2296 }
2297
2298 case USB_REQ_GET_DESCRIPTOR:
2299 dev_dbg(&dev->pdev->dev,
2300 "SETUP: USB_REQ_GET_DESCRIPTOR\n");
2301 goto delegate;
2302
2303 case USB_REQ_SET_DESCRIPTOR:
2304 dev_dbg(&dev->pdev->dev,
2305 "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
2306 goto delegate;
2307
2308 case USB_REQ_GET_CONFIGURATION:
2309 dev_dbg(&dev->pdev->dev,
2310 "SETUP: USB_REQ_GET_CONFIGURATION\n");
2311 goto delegate;
2312
2313 case USB_REQ_SET_CONFIGURATION:
2314 dev_dbg(&dev->pdev->dev,
2315 "SETUP: USB_REQ_SET_CONFIGURATION\n");
2316 goto delegate;
2317
2318 case USB_REQ_GET_INTERFACE:
2319 dev_dbg(&dev->pdev->dev,
2320 "SETUP: USB_REQ_GET_INTERFACE\n");
2321 goto delegate;
2322
2323 case USB_REQ_SET_INTERFACE:
2324 dev_dbg(&dev->pdev->dev,
2325 "SETUP: USB_REQ_SET_INTERFACE\n");
2326 goto delegate;
2327
2328 case USB_REQ_SYNCH_FRAME:
2329 dev_dbg(&dev->pdev->dev,
2330 "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
2331 goto delegate;
2332
2333 default:
2334 /* delegate USB standard requests to the gadget driver */
2335 goto delegate;
2336delegate:
2337 /* USB requests handled by gadget */
2338 if (wLength) {
2339 /* DATA phase from gadget, STATUS phase from udc */
2340 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2341 ? USB_DIR_IN : USB_DIR_OUT;
2342 dev_vdbg(&dev->pdev->dev,
2343 "dev->ep0_dir = 0x%x, wLength = %d\n",
2344 dev->ep0_dir, wLength);
2345 spin_unlock(&dev->lock);
2346 if (dev->driver->setup(&dev->gadget,
2347 &dev->local_setup_buff) < 0)
2348 ep0_stall(dev);
2349 spin_lock(&dev->lock);
2350 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2351 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2352 } else {
2353 /* no DATA phase, IN STATUS phase from gadget */
2354 dev->ep0_dir = USB_DIR_IN;
2355 dev_vdbg(&dev->pdev->dev,
2356 "dev->ep0_dir = 0x%x, wLength = %d\n",
2357 dev->ep0_dir, wLength);
2358 spin_unlock(&dev->lock);
2359 if (dev->driver->setup(&dev->gadget,
2360 &dev->local_setup_buff) < 0)
2361 ep0_stall(dev);
2362 spin_lock(&dev->lock);
2363 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2364 }
2365 break;
2366 }
2367end:
2368 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2369}
2370
2371
2372/* transfer completion, process endpoint request and free the completed dTDs
2373 * for this request
2374 */
2375static int process_ep_req(struct langwell_udc *dev, int index,
2376 struct langwell_request *curr_req)
2377{
2378 struct langwell_dtd *curr_dtd;
2379 struct langwell_dqh *curr_dqh;
2380 int td_complete, actual, remaining_length;
2381 int i, dir;
2382 u8 dtd_status = 0;
2383 int retval = 0;
2384
2385 curr_dqh = &dev->ep_dqh[index];
2386 dir = index % 2;
2387
2388 curr_dtd = curr_req->head;
2389 td_complete = 0;
2390 actual = curr_req->req.length;
2391
2392 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2393
2394 for (i = 0; i < curr_req->dtd_count; i++) {
2395
2396 /* command execution states by dTD */
2397 dtd_status = curr_dtd->dtd_status;
2398
2399 barrier();
2400 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2401 actual -= remaining_length;
2402
2403 if (!dtd_status) {
2404 /* transfers completed successfully */
2405 if (!remaining_length) {
2406 td_complete++;
2407 dev_vdbg(&dev->pdev->dev,
2408 "dTD transmitted successfully\n");
2409 } else {
2410 if (dir) {
2411 dev_vdbg(&dev->pdev->dev,
2412 "TX dTD remains data\n");
2413 retval = -EPROTO;
2414 break;
2415
2416 } else {
2417 td_complete++;
2418 break;
2419 }
2420 }
2421 } else {
2422 /* transfers completed with errors */
2423 if (dtd_status & DTD_STS_ACTIVE) {
2424 dev_dbg(&dev->pdev->dev,
2425 "dTD status ACTIVE dQH[%d]\n", index);
2426 retval = 1;
2427 return retval;
2428 } else if (dtd_status & DTD_STS_HALTED) {
2429 dev_err(&dev->pdev->dev,
2430 "dTD error %08x dQH[%d]\n",
2431 dtd_status, index);
2432 /* clear the errors and halt condition */
2433 curr_dqh->dtd_status = 0;
2434 retval = -EPIPE;
2435 break;
2436 } else if (dtd_status & DTD_STS_DBE) {
2437 dev_dbg(&dev->pdev->dev,
2438 "data buffer (overflow) error\n");
2439 retval = -EPROTO;
2440 break;
2441 } else if (dtd_status & DTD_STS_TRE) {
2442 dev_dbg(&dev->pdev->dev,
2443 "transaction(ISO) error\n");
2444 retval = -EILSEQ;
2445 break;
2446 } else
2447 dev_err(&dev->pdev->dev,
2448 "unknown error (0x%x)!\n",
2449 dtd_status);
2450 }
2451
2452 if (i != curr_req->dtd_count - 1)
2453 curr_dtd = (struct langwell_dtd *)
2454 curr_dtd->next_dtd_virt;
2455 }
2456
2457 if (retval)
2458 return retval;
2459
2460 curr_req->req.actual = actual;
2461
2462 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2463 return 0;
2464}
2465
2466
2467/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2468static void ep0_req_complete(struct langwell_udc *dev,
2469 struct langwell_ep *ep0, struct langwell_request *req)
2470{
2471 u32 new_addr;
2472 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2473
2474 if (dev->usb_state == USB_STATE_ADDRESS) {
2475 /* set the new address */
2476 new_addr = (u32)dev->dev_addr;
2477 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2478
2479 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
2480 dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
2481 }
2482
2483 done(ep0, req, 0);
2484
2485 switch (dev->ep0_state) {
2486 case DATA_STATE_XMIT:
2487 /* receive status phase */
2488 if (prime_status_phase(dev, EP_DIR_OUT))
2489 ep0_stall(dev);
2490 break;
2491 case DATA_STATE_RECV:
2492 /* send status phase */
2493 if (prime_status_phase(dev, EP_DIR_IN))
2494 ep0_stall(dev);
2495 break;
2496 case WAIT_FOR_OUT_STATUS:
2497 dev->ep0_state = WAIT_FOR_SETUP;
2498 break;
2499 case WAIT_FOR_SETUP:
2500 dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
2501 break;
2502 default:
2503 ep0_stall(dev);
2504 break;
2505 }
2506
2507 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2508}
2509
2510
2511/* USB transfer completion interrupt */
2512static void handle_trans_complete(struct langwell_udc *dev)
2513{
2514 u32 complete_bits;
2515 int i, ep_num, dir, bit_mask, status;
2516 struct langwell_ep *epn;
2517 struct langwell_request *curr_req, *temp_req;
2518
2519 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2520
2521 complete_bits = readl(&dev->op_regs->endptcomplete);
2522 dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
2523 complete_bits);
2524
2525 /* Write-Clear the bits in endptcomplete register */
2526 writel(complete_bits, &dev->op_regs->endptcomplete);
2527
2528 if (!complete_bits) {
2529 dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
2530 goto done;
2531 }
2532
2533 for (i = 0; i < dev->ep_max; i++) {
2534 ep_num = i / 2;
2535 dir = i % 2;
2536
2537 bit_mask = 1 << (ep_num + 16 * dir);
2538
2539 if (!(complete_bits & bit_mask))
2540 continue;
2541
2542 /* ep0 */
2543 if (i == 1)
2544 epn = &dev->ep[0];
2545 else
2546 epn = &dev->ep[i];
2547
2548 if (epn->name == NULL) {
2549 dev_warn(&dev->pdev->dev, "invalid endpoint\n");
2550 continue;
2551 }
2552
2553 if (i < 2)
2554 /* ep0 in and out */
2555 dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
2556 epn->name,
2557 is_in(epn) ? "in" : "out");
2558 else
2559 dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
2560 epn->name);
2561
2562 /* process the req queue until an uncomplete request */
2563 list_for_each_entry_safe(curr_req, temp_req,
2564 &epn->queue, queue) {
2565 status = process_ep_req(dev, i, curr_req);
2566 dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
2567 epn->name, status);
2568
2569 if (status)
2570 break;
2571
2572 /* write back status to req */
2573 curr_req->req.status = status;
2574
2575 /* ep0 request completion */
2576 if (ep_num == 0) {
2577 ep0_req_complete(dev, epn, curr_req);
2578 break;
2579 } else {
2580 done(epn, curr_req, status);
2581 }
2582 }
2583 }
2584done:
2585 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2586}
2587
2588/* port change detect interrupt handler */
2589static void handle_port_change(struct langwell_udc *dev)
2590{
2591 u32 portsc1, devlc;
2592
2593 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2594
2595 if (dev->bus_reset)
2596 dev->bus_reset = 0;
2597
2598 portsc1 = readl(&dev->op_regs->portsc1);
2599 devlc = readl(&dev->op_regs->devlc);
2600 dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
2601 portsc1, devlc);
2602
2603 /* bus reset is finished */
2604 if (!(portsc1 & PORTS_PR)) {
2605 /* get the speed */
2606 dev->gadget.speed = lpm_device_speed(devlc);
2607 dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
2608 dev->gadget.speed);
2609 }
2610
2611 /* LPM L0 to L1 */
2612 if (dev->lpm && dev->lpm_state == LPM_L0)
2613 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
2614 dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
2615 dev->lpm_state = LPM_L1;
2616 }
2617
2618 /* LPM L1 to L0, force resume or remote wakeup finished */
2619 if (dev->lpm && dev->lpm_state == LPM_L1)
2620 if (!(portsc1 & PORTS_SUSP)) {
2621 dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
2622 dev->lpm_state = LPM_L0;
2623 }
2624
2625 /* update USB state */
2626 if (!dev->resume_state)
2627 dev->usb_state = USB_STATE_DEFAULT;
2628
2629 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2630}
2631
2632
2633/* USB reset interrupt handler */
2634static void handle_usb_reset(struct langwell_udc *dev)
2635{
2636 u32 deviceaddr,
2637 endptsetupstat,
2638 endptcomplete;
2639 unsigned long timeout;
2640
2641 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2642
2643 /* Write-Clear the device address */
2644 deviceaddr = readl(&dev->op_regs->deviceaddr);
2645 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2646
2647 dev->dev_addr = 0;
2648
2649 /* clear usb state */
2650 dev->resume_state = 0;
2651
2652 /* LPM L1 to L0, reset */
2653 if (dev->lpm)
2654 dev->lpm_state = LPM_L0;
2655
2656 dev->ep0_dir = USB_DIR_OUT;
2657 dev->ep0_state = WAIT_FOR_SETUP;
2658
2659 /* remote wakeup reset to 0 when the device is reset */
2660 dev->remote_wakeup = 0;
2661 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
2662 dev->gadget.b_hnp_enable = 0;
2663 dev->gadget.a_hnp_support = 0;
2664 dev->gadget.a_alt_hnp_support = 0;
2665
2666 /* Write-Clear all the setup token semaphores */
2667 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2668 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2669
2670 /* Write-Clear all the endpoint complete status bits */
2671 endptcomplete = readl(&dev->op_regs->endptcomplete);
2672 writel(endptcomplete, &dev->op_regs->endptcomplete);
2673
2674 /* wait until all endptprime bits cleared */
2675 timeout = jiffies + PRIME_TIMEOUT;
2676 while (readl(&dev->op_regs->endptprime)) {
2677 if (time_after(jiffies, timeout)) {
2678 dev_err(&dev->pdev->dev, "USB reset timeout\n");
2679 break;
2680 }
2681 cpu_relax();
2682 }
2683
2684 /* write 1s to endptflush register to clear any primed buffers */
2685 writel((u32) ~0, &dev->op_regs->endptflush);
2686
2687 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
2688 dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
2689 /* bus is reseting */
2690 dev->bus_reset = 1;
2691
2692 /* reset all the queues, stop all USB activities */
2693 stop_activity(dev);
2694 dev->usb_state = USB_STATE_DEFAULT;
2695 } else {
2696 dev_vdbg(&dev->pdev->dev, "device controller reset\n");
2697 /* controller reset */
2698 langwell_udc_reset(dev);
2699
2700 /* reset all the queues, stop all USB activities */
2701 stop_activity(dev);
2702
2703 /* reset ep0 dQH and endptctrl */
2704 ep0_reset(dev);
2705
2706 /* enable interrupt and set controller to run state */
2707 langwell_udc_start(dev);
2708
2709 dev->usb_state = USB_STATE_ATTACHED;
2710 }
2711
2712 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2713}
2714
2715
2716/* USB bus suspend/resume interrupt */
2717static void handle_bus_suspend(struct langwell_udc *dev)
2718{
2719 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2720
2721 dev->resume_state = dev->usb_state;
2722 dev->usb_state = USB_STATE_SUSPENDED;
2723
2724 /* report suspend to the driver */
2725 if (dev->driver) {
2726 if (dev->driver->suspend) {
2727 spin_unlock(&dev->lock);
2728 dev->driver->suspend(&dev->gadget);
2729 spin_lock(&dev->lock);
2730 dev_dbg(&dev->pdev->dev, "suspend %s\n",
2731 dev->driver->driver.name);
2732 }
2733 }
2734
2735 /* enter PHY low power suspend */
2736 if (dev->pdev->device != 0x0829)
2737 langwell_phy_low_power(dev, 0);
2738
2739 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2740}
2741
2742
2743static void handle_bus_resume(struct langwell_udc *dev)
2744{
2745 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2746
2747 dev->usb_state = dev->resume_state;
2748 dev->resume_state = 0;
2749
2750 /* exit PHY low power suspend */
2751 if (dev->pdev->device != 0x0829)
2752 langwell_phy_low_power(dev, 0);
2753
2754 /* report resume to the driver */
2755 if (dev->driver) {
2756 if (dev->driver->resume) {
2757 spin_unlock(&dev->lock);
2758 dev->driver->resume(&dev->gadget);
2759 spin_lock(&dev->lock);
2760 dev_dbg(&dev->pdev->dev, "resume %s\n",
2761 dev->driver->driver.name);
2762 }
2763 }
2764
2765 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2766}
2767
2768
2769/* USB device controller interrupt handler */
2770static irqreturn_t langwell_irq(int irq, void *_dev)
2771{
2772 struct langwell_udc *dev = _dev;
2773 u32 usbsts,
2774 usbintr,
2775 irq_sts,
2776 portsc1;
2777
2778 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
2779
2780 if (dev->stopped) {
2781 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2782 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2783 return IRQ_NONE;
2784 }
2785
2786 spin_lock(&dev->lock);
2787
2788 /* USB status */
2789 usbsts = readl(&dev->op_regs->usbsts);
2790
2791 /* USB interrupt enable */
2792 usbintr = readl(&dev->op_regs->usbintr);
2793
2794 irq_sts = usbsts & usbintr;
2795 dev_vdbg(&dev->pdev->dev,
2796 "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
2797 usbsts, usbintr, irq_sts);
2798
2799 if (!irq_sts) {
2800 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2801 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2802 spin_unlock(&dev->lock);
2803 return IRQ_NONE;
2804 }
2805
2806 /* Write-Clear interrupt status bits */
2807 writel(irq_sts, &dev->op_regs->usbsts);
2808
2809 /* resume from suspend */
2810 portsc1 = readl(&dev->op_regs->portsc1);
2811 if (dev->usb_state == USB_STATE_SUSPENDED)
2812 if (!(portsc1 & PORTS_SUSP))
2813 handle_bus_resume(dev);
2814
2815 /* USB interrupt */
2816 if (irq_sts & STS_UI) {
2817 dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
2818
2819 /* setup packet received from ep0 */
2820 if (readl(&dev->op_regs->endptsetupstat)
2821 & EP0SETUPSTAT_MASK) {
2822 dev_vdbg(&dev->pdev->dev,
2823 "USB SETUP packet received interrupt\n");
2824 /* setup tripwire semaphone */
2825 setup_tripwire(dev);
2826 handle_setup_packet(dev, &dev->local_setup_buff);
2827 }
2828
2829 /* USB transfer completion */
2830 if (readl(&dev->op_regs->endptcomplete)) {
2831 dev_vdbg(&dev->pdev->dev,
2832 "USB transfer completion interrupt\n");
2833 handle_trans_complete(dev);
2834 }
2835 }
2836
2837 /* SOF received interrupt (for ISO transfer) */
2838 if (irq_sts & STS_SRI) {
2839 /* FIXME */
2840 /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
2841 }
2842
2843 /* port change detect interrupt */
2844 if (irq_sts & STS_PCI) {
2845 dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
2846 handle_port_change(dev);
2847 }
2848
2849 /* suspend interrupt */
2850 if (irq_sts & STS_SLI) {
2851 dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
2852 handle_bus_suspend(dev);
2853 }
2854
2855 /* USB reset interrupt */
2856 if (irq_sts & STS_URI) {
2857 dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
2858 handle_usb_reset(dev);
2859 }
2860
2861 /* USB error or system error interrupt */
2862 if (irq_sts & (STS_UEI | STS_SEI)) {
2863 /* FIXME */
2864 dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
2865 }
2866
2867 spin_unlock(&dev->lock);
2868
2869 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2870 return IRQ_HANDLED;
2871}
2872
2873
2874/*-------------------------------------------------------------------------*/
2875
2876/* release device structure */
2877static void gadget_release(struct device *_dev)
2878{
2879 struct langwell_udc *dev = dev_get_drvdata(_dev);
2880
2881 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2882
2883 complete(dev->done);
2884
2885 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2886 kfree(dev);
2887}
2888
2889
2890/* enable SRAM caching if SRAM detected */
2891static void sram_init(struct langwell_udc *dev)
2892{
2893 struct pci_dev *pdev = dev->pdev;
2894
2895 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2896
2897 dev->sram_addr = pci_resource_start(pdev, 1);
2898 dev->sram_size = pci_resource_len(pdev, 1);
2899 dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
2900 dev->sram_addr, dev->sram_size);
2901 dev->got_sram = 1;
2902
2903 if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
2904 dev_warn(&dev->pdev->dev, "SRAM request failed\n");
2905 dev->got_sram = 0;
2906 } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
2907 dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
2908 dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
2909 pci_release_region(pdev, 1);
2910 dev->got_sram = 0;
2911 }
2912
2913 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2914}
2915
2916
2917/* release SRAM caching */
2918static void sram_deinit(struct langwell_udc *dev)
2919{
2920 struct pci_dev *pdev = dev->pdev;
2921
2922 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2923
2924 dma_release_declared_memory(&pdev->dev);
2925 pci_release_region(pdev, 1);
2926
2927 dev->got_sram = 0;
2928
2929 dev_info(&dev->pdev->dev, "release SRAM caching\n");
2930 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2931}
2932
2933
2934/* tear down the binding between this driver and the pci device */
2935static void langwell_udc_remove(struct pci_dev *pdev)
2936{
2937 struct langwell_udc *dev = pci_get_drvdata(pdev);
2938
2939 DECLARE_COMPLETION(done);
2940
2941 BUG_ON(dev->driver);
2942 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2943
2944 dev->done = &done;
2945
2946 /* free dTD dma_pool and dQH */
2947 if (dev->dtd_pool)
2948 dma_pool_destroy(dev->dtd_pool);
2949
2950 if (dev->ep_dqh)
2951 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
2952 dev->ep_dqh, dev->ep_dqh_dma);
2953
2954 /* release SRAM caching */
2955 if (dev->has_sram && dev->got_sram)
2956 sram_deinit(dev);
2957
2958 if (dev->status_req) {
2959 kfree(dev->status_req->req.buf);
2960 kfree(dev->status_req);
2961 }
2962
2963 kfree(dev->ep);
2964
2965 /* disable IRQ handler */
2966 if (dev->got_irq)
2967 free_irq(pdev->irq, dev);
2968
2969 if (dev->cap_regs)
2970 iounmap(dev->cap_regs);
2971
2972 if (dev->region)
2973 release_mem_region(pci_resource_start(pdev, 0),
2974 pci_resource_len(pdev, 0));
2975
2976 if (dev->enabled)
2977 pci_disable_device(pdev);
2978
2979 dev->cap_regs = NULL;
2980
2981 dev_info(&dev->pdev->dev, "unbind\n");
2982 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
2983
2984 device_unregister(&dev->gadget.dev);
2985 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
2986 device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
2987
2988 pci_set_drvdata(pdev, NULL);
2989
2990 /* free dev, wait for the release() finished */
2991 wait_for_completion(&done);
2992}
2993
2994
2995/*
2996 * wrap this driver around the specified device, but
2997 * don't respond over USB until a gadget driver binds to us.
2998 */
2999static int langwell_udc_probe(struct pci_dev *pdev,
3000 const struct pci_device_id *id)
3001{
3002 struct langwell_udc *dev;
3003 unsigned long resource, len;
3004 void __iomem *base = NULL;
3005 size_t size;
3006 int retval;
3007
3008 /* alloc, and start init */
3009 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3010 if (dev == NULL) {
3011 retval = -ENOMEM;
3012 goto error;
3013 }
3014
3015 /* initialize device spinlock */
3016 spin_lock_init(&dev->lock);
3017
3018 dev->pdev = pdev;
3019 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3020
3021 pci_set_drvdata(pdev, dev);
3022
3023 /* now all the pci goodies ... */
3024 if (pci_enable_device(pdev) < 0) {
3025 retval = -ENODEV;
3026 goto error;
3027 }
3028 dev->enabled = 1;
3029
3030 /* control register: BAR 0 */
3031 resource = pci_resource_start(pdev, 0);
3032 len = pci_resource_len(pdev, 0);
3033 if (!request_mem_region(resource, len, driver_name)) {
3034 dev_err(&dev->pdev->dev, "controller already in use\n");
3035 retval = -EBUSY;
3036 goto error;
3037 }
3038 dev->region = 1;
3039
3040 base = ioremap_nocache(resource, len);
3041 if (base == NULL) {
3042 dev_err(&dev->pdev->dev, "can't map memory\n");
3043 retval = -EFAULT;
3044 goto error;
3045 }
3046
3047 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
3048 dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
3049 dev->op_regs = (struct langwell_op_regs __iomem *)
3050 (base + OP_REG_OFFSET);
3051 dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
3052
3053 /* irq setup after old hardware is cleaned up */
3054 if (!pdev->irq) {
3055 dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
3056 retval = -ENODEV;
3057 goto error;
3058 }
3059
3060 dev->has_sram = 1;
3061 dev->got_sram = 0;
3062 dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
3063
3064 /* enable SRAM caching if detected */
3065 if (dev->has_sram && !dev->got_sram)
3066 sram_init(dev);
3067
3068 dev_info(&dev->pdev->dev,
3069 "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
3070 pdev->irq, resource, len, base);
3071 /* enables bus-mastering for device dev */
3072 pci_set_master(pdev);
3073
3074 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3075 driver_name, dev) != 0) {
3076 dev_err(&dev->pdev->dev,
3077 "request interrupt %d failed\n", pdev->irq);
3078 retval = -EBUSY;
3079 goto error;
3080 }
3081 dev->got_irq = 1;
3082
3083 /* set stopped bit */
3084 dev->stopped = 1;
3085
3086 /* capabilities and endpoint number */
3087 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3088 dev->dciversion = readw(&dev->cap_regs->dciversion);
3089 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
3090 dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
3091 dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
3092 dev->dciversion);
3093 dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
3094 readl(&dev->cap_regs->dccparams));
3095 dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
3096 if (!dev->devcap) {
3097 dev_err(&dev->pdev->dev, "can't support device mode\n");
3098 retval = -ENODEV;
3099 goto error;
3100 }
3101
3102 /* a pair of endpoints (out/in) for each address */
3103 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
3104 dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
3105
3106 /* allocate endpoints memory */
3107 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3108 GFP_KERNEL);
3109 if (!dev->ep) {
3110 dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
3111 retval = -ENOMEM;
3112 goto error;
3113 }
3114
3115 /* allocate device dQH memory */
3116 size = dev->ep_max * sizeof(struct langwell_dqh);
3117 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
3118 if (size < DQH_ALIGNMENT)
3119 size = DQH_ALIGNMENT;
3120 else if ((size % DQH_ALIGNMENT) != 0) {
3121 size += DQH_ALIGNMENT + 1;
3122 size &= ~(DQH_ALIGNMENT - 1);
3123 }
3124 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3125 &dev->ep_dqh_dma, GFP_KERNEL);
3126 if (!dev->ep_dqh) {
3127 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
3128 retval = -ENOMEM;
3129 goto error;
3130 }
3131 dev->ep_dqh_size = size;
3132 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
3133
3134 /* initialize ep0 status request structure */
3135 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3136 if (!dev->status_req) {
3137 dev_err(&dev->pdev->dev,
3138 "allocate status_req memory failed\n");
3139 retval = -ENOMEM;
3140 goto error;
3141 }
3142 INIT_LIST_HEAD(&dev->status_req->queue);
3143
3144 /* allocate a small amount of memory to get valid address */
3145 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3146 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3147
3148 dev->resume_state = USB_STATE_NOTATTACHED;
3149 dev->usb_state = USB_STATE_POWERED;
3150 dev->ep0_dir = USB_DIR_OUT;
3151
3152 /* remote wakeup reset to 0 when the device is reset */
3153 dev->remote_wakeup = 0;
3154 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
3155
3156 /* reset device controller */
3157 langwell_udc_reset(dev);
3158
3159 /* initialize gadget structure */
3160 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3161 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3162 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3163 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
3164 dev->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
3165
3166 /* the "gadget" abstracts/virtualizes the controller */
3167 dev_set_name(&dev->gadget.dev, "gadget");
3168 dev->gadget.dev.parent = &pdev->dev;
3169 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3170 dev->gadget.dev.release = gadget_release;
3171 dev->gadget.name = driver_name; /* gadget name */
3172
3173 /* controller endpoints reinit */
3174 eps_reinit(dev);
3175
3176 /* reset ep0 dQH and endptctrl */
3177 ep0_reset(dev);
3178
3179 /* create dTD dma_pool resource */
3180 dev->dtd_pool = dma_pool_create("langwell_dtd",
3181 &dev->pdev->dev,
3182 sizeof(struct langwell_dtd),
3183 DTD_ALIGNMENT,
3184 DMA_BOUNDARY);
3185
3186 if (!dev->dtd_pool) {
3187 retval = -ENOMEM;
3188 goto error;
3189 }
3190
3191 /* done */
3192 dev_info(&dev->pdev->dev, "%s\n", driver_desc);
3193 dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
3194 dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
3195 dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
3196 dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
3197 dev->dciversion);
3198 dev_info(&dev->pdev->dev, "Controller mode: %s\n",
3199 dev->devcap ? "Device" : "Host");
3200 dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
3201 dev->lpm ? "Yes" : "No");
3202
3203 dev_vdbg(&dev->pdev->dev,
3204 "After langwell_udc_probe(), print all registers:\n");
3205 print_all_registers(dev);
3206
3207 retval = device_register(&dev->gadget.dev);
3208 if (retval)
3209 goto error;
3210
3211 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3212 if (retval)
3213 goto error;
3214
3215 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3216 if (retval)
3217 goto error;
3218
3219 retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
3220 if (retval)
3221 goto error_attr1;
3222
3223 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3224 return 0;
3225
3226error_attr1:
3227 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
3228error:
3229 if (dev) {
3230 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3231 langwell_udc_remove(pdev);
3232 }
3233
3234 return retval;
3235}
3236
3237
3238/* device controller suspend */
3239static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3240{
3241 struct langwell_udc *dev = pci_get_drvdata(pdev);
3242
3243 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3244
3245 usb_del_gadget_udc(&dev->gadget);
3246 /* disable interrupt and set controller to stop state */
3247 langwell_udc_stop(dev);
3248
3249 /* disable IRQ handler */
3250 if (dev->got_irq)
3251 free_irq(pdev->irq, dev);
3252 dev->got_irq = 0;
3253
3254 /* save PCI state */
3255 pci_save_state(pdev);
3256
3257 spin_lock_irq(&dev->lock);
3258 /* stop all usb activities */
3259 stop_activity(dev);
3260 spin_unlock_irq(&dev->lock);
3261
3262 /* free dTD dma_pool and dQH */
3263 if (dev->dtd_pool)
3264 dma_pool_destroy(dev->dtd_pool);
3265
3266 if (dev->ep_dqh)
3267 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3268 dev->ep_dqh, dev->ep_dqh_dma);
3269
3270 /* release SRAM caching */
3271 if (dev->has_sram && dev->got_sram)
3272 sram_deinit(dev);
3273
3274 /* set device power state */
3275 pci_set_power_state(pdev, PCI_D3hot);
3276
3277 /* enter PHY low power suspend */
3278 if (dev->pdev->device != 0x0829)
3279 langwell_phy_low_power(dev, 1);
3280
3281 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3282 return 0;
3283}
3284
3285
3286/* device controller resume */
3287static int langwell_udc_resume(struct pci_dev *pdev)
3288{
3289 struct langwell_udc *dev = pci_get_drvdata(pdev);
3290 size_t size;
3291
3292 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3293
3294 /* exit PHY low power suspend */
3295 if (dev->pdev->device != 0x0829)
3296 langwell_phy_low_power(dev, 0);
3297
3298 /* set device D0 power state */
3299 pci_set_power_state(pdev, PCI_D0);
3300
3301 /* enable SRAM caching if detected */
3302 if (dev->has_sram && !dev->got_sram)
3303 sram_init(dev);
3304
3305 /* allocate device dQH memory */
3306 size = dev->ep_max * sizeof(struct langwell_dqh);
3307 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
3308 if (size < DQH_ALIGNMENT)
3309 size = DQH_ALIGNMENT;
3310 else if ((size % DQH_ALIGNMENT) != 0) {
3311 size += DQH_ALIGNMENT + 1;
3312 size &= ~(DQH_ALIGNMENT - 1);
3313 }
3314 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3315 &dev->ep_dqh_dma, GFP_KERNEL);
3316 if (!dev->ep_dqh) {
3317 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
3318 return -ENOMEM;
3319 }
3320 dev->ep_dqh_size = size;
3321 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
3322
3323 /* create dTD dma_pool resource */
3324 dev->dtd_pool = dma_pool_create("langwell_dtd",
3325 &dev->pdev->dev,
3326 sizeof(struct langwell_dtd),
3327 DTD_ALIGNMENT,
3328 DMA_BOUNDARY);
3329
3330 if (!dev->dtd_pool)
3331 return -ENOMEM;
3332
3333 /* restore PCI state */
3334 pci_restore_state(pdev);
3335
3336 /* enable IRQ handler */
3337 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3338 driver_name, dev) != 0) {
3339 dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
3340 pdev->irq);
3341 return -EBUSY;
3342 }
3343 dev->got_irq = 1;
3344
3345 /* reset and start controller to run state */
3346 if (dev->stopped) {
3347 /* reset device controller */
3348 langwell_udc_reset(dev);
3349
3350 /* reset ep0 dQH and endptctrl */
3351 ep0_reset(dev);
3352
3353 /* start device if gadget is loaded */
3354 if (dev->driver)
3355 langwell_udc_start(dev);
3356 }
3357
3358 /* reset USB status */
3359 dev->usb_state = USB_STATE_ATTACHED;
3360 dev->ep0_state = WAIT_FOR_SETUP;
3361 dev->ep0_dir = USB_DIR_OUT;
3362
3363 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3364 return 0;
3365}
3366
3367
3368/* pci driver shutdown */
3369static void langwell_udc_shutdown(struct pci_dev *pdev)
3370{
3371 struct langwell_udc *dev = pci_get_drvdata(pdev);
3372 u32 usbmode;
3373
3374 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3375
3376 /* reset controller mode to IDLE */
3377 usbmode = readl(&dev->op_regs->usbmode);
3378 dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
3379 usbmode &= (~3 | MODE_IDLE);
3380 writel(usbmode, &dev->op_regs->usbmode);
3381
3382 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3383}
3384
3385/*-------------------------------------------------------------------------*/
3386
3387static const struct pci_device_id pci_ids[] = { {
3388 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3389 .class_mask = ~0,
3390 .vendor = 0x8086,
3391 .device = 0x0811,
3392 .subvendor = PCI_ANY_ID,
3393 .subdevice = PCI_ANY_ID,
3394}, { /* end: all zeroes */ }
3395};
3396
3397MODULE_DEVICE_TABLE(pci, pci_ids);
3398
3399
3400static struct pci_driver langwell_pci_driver = {
3401 .name = (char *) driver_name,
3402 .id_table = pci_ids,
3403
3404 .probe = langwell_udc_probe,
3405 .remove = langwell_udc_remove,
3406
3407 /* device controller suspend/resume */
3408 .suspend = langwell_udc_suspend,
3409 .resume = langwell_udc_resume,
3410
3411 .shutdown = langwell_udc_shutdown,
3412};
3413
3414module_pci_driver(langwell_pci_driver);
3415
3416MODULE_DESCRIPTION(DRIVER_DESC);
3417MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3418MODULE_VERSION(DRIVER_VERSION);
3419MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
deleted file mode 100644
index 38fa3c86d85c..000000000000
--- a/drivers/usb/gadget/langwell_udc.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#include <linux/usb/langwell_udc.h>
11
12/*-------------------------------------------------------------------------*/
13
14/* driver data structures and utilities */
15
16/*
17 * dTD: Device Endpoint Transfer Descriptor
18 * describe to the device controller the location and quantity of
19 * data to be send/received for given transfer
20 */
21struct langwell_dtd {
22 u32 dtd_next;
23/* bits 31:5, next transfer element pointer */
24#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
25#define DTD_NEXT_MASK (0x7ffffff << 5)
26/* terminate */
27#define DTD_TERM BIT(0)
28 /* bits 7:0, execution back states */
29 u32 dtd_status:8;
30#define DTD_STATUS(d) (((d)>>0)&0xff)
31#define DTD_STS_ACTIVE BIT(7) /* active */
32#define DTD_STS_HALTED BIT(6) /* halted */
33#define DTD_STS_DBE BIT(5) /* data buffer error */
34#define DTD_STS_TRE BIT(3) /* transaction error */
35 /* bits 9:8 */
36 u32 dtd_res0:2;
37 /* bits 11:10, multipier override */
38 u32 dtd_multo:2;
39#define DTD_MULTO (BIT(11) | BIT(10))
40 /* bits 14:12 */
41 u32 dtd_res1:3;
42 /* bit 15, interrupt on complete */
43 u32 dtd_ioc:1;
44#define DTD_IOC BIT(15)
45 /* bits 30:16, total bytes */
46 u32 dtd_total:15;
47#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
48#define DTD_MAX_TRANSFER_LENGTH 0x4000
49 /* bit 31 */
50 u32 dtd_res2:1;
51 /* dTD buffer pointer page 0 to 4 */
52 u32 dtd_buf[5];
53#define DTD_OFFSET_MASK 0xfff
54/* bits 31:12, buffer pointer */
55#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
56/* bits 11:0, current offset */
57#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
58/* bits 10:0, frame number */
59#define DTD_FRAME(d) (((d)>>0)&0x7ff)
60
61 /* driver-private parts */
62
63 /* dtd dma address */
64 dma_addr_t dtd_dma;
65 /* next dtd virtual address */
66 struct langwell_dtd *next_dtd_virt;
67};
68
69
70/*
71 * dQH: Device Endpoint Queue Head
72 * describe where all transfers are managed
73 * 48-byte data structure, aligned on 64-byte boundary
74 *
75 * These are associated with dTD structure
76 */
77struct langwell_dqh {
78 /* endpoint capabilities and characteristics */
79 u32 dqh_res0:15; /* bits 14:0 */
80 u32 dqh_ios:1; /* bit 15, interrupt on setup */
81#define DQH_IOS BIT(15)
82 u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
83#define DQH_MPL (0x7ff << 16)
84 u32 dqh_res1:2; /* bits 28:27 */
85 u32 dqh_zlt:1; /* bit 29, zero length termination */
86#define DQH_ZLT BIT(29)
87 u32 dqh_mult:2; /* bits 31:30 */
88#define DQH_MULT (BIT(30) | BIT(31))
89
90 /* current dTD pointer */
91 u32 dqh_current; /* locate the transfer in progress */
92#define DQH_C_DTD(e) \
93 (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
94
95 /* transfer overlay, hardware parts of a struct langwell_dtd */
96 u32 dtd_next;
97 u32 dtd_status:8; /* bits 7:0, execution back states */
98 u32 dtd_res0:2; /* bits 9:8 */
99 u32 dtd_multo:2; /* bits 11:10, multipier override */
100 u32 dtd_res1:3; /* bits 14:12 */
101 u32 dtd_ioc:1; /* bit 15, interrupt on complete */
102 u32 dtd_total:15; /* bits 30:16, total bytes */
103 u32 dtd_res2:1; /* bit 31 */
104 u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
105
106 u32 dqh_res2;
107 struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
108} __attribute__ ((aligned(64)));
109
110
111/* endpoint data structure */
112struct langwell_ep {
113 struct usb_ep ep;
114 dma_addr_t dma;
115 struct langwell_udc *dev;
116 unsigned long irqs;
117 struct list_head queue;
118 struct langwell_dqh *dqh;
119 char name[14];
120 unsigned stopped:1,
121 ep_type:2,
122 ep_num:8;
123};
124
125
126/* request data structure */
127struct langwell_request {
128 struct usb_request req;
129 struct langwell_dtd *dtd, *head, *tail;
130 struct langwell_ep *ep;
131 dma_addr_t dtd_dma;
132 struct list_head queue;
133 unsigned dtd_count;
134 unsigned mapped:1;
135};
136
137
138/* ep0 transfer state */
139enum ep0_state {
140 WAIT_FOR_SETUP,
141 DATA_STATE_XMIT,
142 DATA_STATE_NEED_ZLP,
143 WAIT_FOR_OUT_STATUS,
144 DATA_STATE_RECV,
145};
146
147
148/* device suspend state */
149enum lpm_state {
150 LPM_L0, /* on */
151 LPM_L1, /* LPM L1 sleep */
152 LPM_L2, /* suspend */
153 LPM_L3, /* off */
154};
155
156
157/* device data structure */
158struct langwell_udc {
159 /* each pci device provides one gadget, several endpoints */
160 struct usb_gadget gadget;
161 spinlock_t lock; /* device lock */
162 struct langwell_ep *ep;
163 struct usb_gadget_driver *driver;
164 struct usb_phy *transceiver;
165 u8 dev_addr;
166 u32 usb_state;
167 u32 resume_state;
168 u32 bus_reset;
169 enum lpm_state lpm_state;
170 enum ep0_state ep0_state;
171 u32 ep0_dir;
172 u16 dciversion;
173 unsigned ep_max;
174 unsigned devcap:1,
175 enabled:1,
176 region:1,
177 got_irq:1,
178 powered:1,
179 remote_wakeup:1,
180 rate:1,
181 is_reset:1,
182 softconnected:1,
183 vbus_active:1,
184 suspended:1,
185 stopped:1,
186 lpm:1, /* LPM capability */
187 has_sram:1, /* SRAM caching */
188 got_sram:1;
189
190 /* pci state used to access those endpoints */
191 struct pci_dev *pdev;
192
193 /* Langwell otg transceiver */
194 struct langwell_otg *lotg;
195
196 /* control registers */
197 struct langwell_cap_regs __iomem *cap_regs;
198 struct langwell_op_regs __iomem *op_regs;
199
200 struct usb_ctrlrequest local_setup_buff;
201 struct langwell_dqh *ep_dqh;
202 size_t ep_dqh_size;
203 dma_addr_t ep_dqh_dma;
204
205 /* ep0 status request */
206 struct langwell_request *status_req;
207
208 /* dma pool */
209 struct dma_pool *dtd_pool;
210
211 /* make sure release() is done */
212 struct completion *done;
213
214 /* for private SRAM caching */
215 unsigned int sram_addr;
216 unsigned int sram_size;
217
218 /* device status data for get_status request */
219 u16 dev_status;
220};
221
222#define gadget_to_langwell(g) container_of((g), struct langwell_udc, gadget)
223
diff --git a/include/linux/usb/langwell_udc.h b/include/linux/usb/langwell_udc.h
deleted file mode 100644
index 2d2d1bbad9d2..000000000000
--- a/include/linux/usb/langwell_udc.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#ifndef __LANGWELL_UDC_H
21#define __LANGWELL_UDC_H
22
23
24/* MACRO defines */
25#define CAP_REG_OFFSET 0x0
26#define OP_REG_OFFSET 0x28
27
28#define DMA_ADDR_INVALID (~(dma_addr_t)0)
29
30#define DQH_ALIGNMENT 2048
31#define DTD_ALIGNMENT 64
32#define DMA_BOUNDARY 4096
33
34#define EP0_MAX_PKT_SIZE 64
35#define EP_DIR_IN 1
36#define EP_DIR_OUT 0
37
38#define FLUSH_TIMEOUT 1000
39#define RESET_TIMEOUT 1000
40#define SETUPSTAT_TIMEOUT 100
41#define PRIME_TIMEOUT 100
42
43
44/* device memory space registers */
45
46/* Capability Registers, BAR0 + CAP_REG_OFFSET */
47struct langwell_cap_regs {
48 /* offset: 0x0 */
49 u8 caplength; /* offset of Operational Register */
50 u8 _reserved3;
51 u16 hciversion; /* H: BCD encoding of host version */
52 u32 hcsparams; /* H: host port steering logic capability */
53 u32 hccparams; /* H: host multiple mode control capability */
54#define HCC_LEN BIT(17) /* Link power management (LPM) capability */
55 u8 _reserved4[0x20-0xc];
56 /* offset: 0x20 */
57 u16 dciversion; /* BCD encoding of device version */
58 u8 _reserved5[0x24-0x22];
59 u32 dccparams; /* overall device controller capability */
60#define HOSTCAP BIT(8) /* host capable */
61#define DEVCAP BIT(7) /* device capable */
62#define DEN(d) \
63 (((d)>>0)&0x1f) /* bits 4:0, device endpoint number */
64} __attribute__ ((packed));
65
66
67/* Operational Registers, BAR0 + OP_REG_OFFSET */
68struct langwell_op_regs {
69 /* offset: 0x28 */
70 u32 extsts;
71#define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
72#define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
73#define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
74#define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
75#define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
76 u32 extintr;
77#define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
78#define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
79#define EXTI_UPIE BIT(2) /* USB host periodic interrupt enable */
80#define EXTI_UAIE BIT(1) /* USB host asynchronous interrupt enable */
81#define EXTI_NAKE BIT(0) /* NAK interrupt enable */
82 /* offset: 0x30 */
83 u32 usbcmd;
84#define CMD_HIRD(u) \
85 (((u)>>24)&0xf) /* bits 27:24, host init resume duration */
86#define CMD_ITC(u) \
87 (((u)>>16)&0xff) /* bits 23:16, interrupt threshold control */
88#define CMD_PPE BIT(15) /* per-port change events enable */
89#define CMD_ATDTW BIT(14) /* add dTD tripwire */
90#define CMD_SUTW BIT(13) /* setup tripwire */
91#define CMD_ASPE BIT(11) /* asynchronous schedule park mode enable */
92#define CMD_FS2 BIT(10) /* frame list size */
93#define CMD_ASP1 BIT(9) /* asynchronous schedule park mode count */
94#define CMD_ASP0 BIT(8)
95#define CMD_LR BIT(7) /* light host/device controller reset */
96#define CMD_IAA BIT(6) /* interrupt on async advance doorbell */
97#define CMD_ASE BIT(5) /* asynchronous schedule enable */
98#define CMD_PSE BIT(4) /* periodic schedule enable */
99#define CMD_FS1 BIT(3)
100#define CMD_FS0 BIT(2)
101#define CMD_RST BIT(1) /* controller reset */
102#define CMD_RUNSTOP BIT(0) /* run/stop */
103 u32 usbsts;
104#define STS_PPCI(u) \
105 (((u)>>16)&0xffff) /* bits 31:16, port-n change detect */
106#define STS_AS BIT(15) /* asynchronous schedule status */
107#define STS_PS BIT(14) /* periodic schedule status */
108#define STS_RCL BIT(13) /* reclamation */
109#define STS_HCH BIT(12) /* HC halted */
110#define STS_ULPII BIT(10) /* ULPI interrupt */
111#define STS_SLI BIT(8) /* DC suspend */
112#define STS_SRI BIT(7) /* SOF received */
113#define STS_URI BIT(6) /* USB reset received */
114#define STS_AAI BIT(5) /* interrupt on async advance */
115#define STS_SEI BIT(4) /* system error */
116#define STS_FRI BIT(3) /* frame list rollover */
117#define STS_PCI BIT(2) /* port change detect */
118#define STS_UEI BIT(1) /* USB error interrupt */
119#define STS_UI BIT(0) /* USB interrupt */
120 u32 usbintr;
121/* bits 31:16, per-port interrupt enable */
122#define INTR_PPCE(u) (((u)>>16)&0xffff)
123#define INTR_ULPIE BIT(10) /* ULPI enable */
124#define INTR_SLE BIT(8) /* DC sleep/suspend enable */
125#define INTR_SRE BIT(7) /* SOF received enable */
126#define INTR_URE BIT(6) /* USB reset enable */
127#define INTR_AAE BIT(5) /* interrupt on async advance enable */
128#define INTR_SEE BIT(4) /* system error enable */
129#define INTR_FRE BIT(3) /* frame list rollover enable */
130#define INTR_PCE BIT(2) /* port change detect enable */
131#define INTR_UEE BIT(1) /* USB error interrupt enable */
132#define INTR_UE BIT(0) /* USB interrupt enable */
133 u32 frindex; /* frame index */
134#define FRINDEX_MASK (0x3fff << 0)
135 u32 ctrldssegment; /* not used */
136 u32 deviceaddr;
137#define USBADR_SHIFT 25
138#define USBADR(d) \
139 (((d)>>25)&0x7f) /* bits 31:25, device address */
140#define USBADR_MASK (0x7f << 25)
141#define USBADRA BIT(24) /* device address advance */
142 u32 endpointlistaddr;/* endpoint list top memory address */
143/* bits 31:11, endpoint list pointer */
144#define EPBASE(d) (((d)>>11)&0x1fffff)
145#define ENDPOINTLISTADDR_MASK (0x1fffff << 11)
146 u32 ttctrl; /* H: TT operatin, not used */
147 /* offset: 0x50 */
148 u32 burstsize; /* burst size of data movement */
149#define TXPBURST(b) \
150 (((b)>>8)&0xff) /* bits 15:8, TX burst length */
151#define RXPBURST(b) \
152 (((b)>>0)&0xff) /* bits 7:0, RX burst length */
153 u32 txfilltuning; /* TX tuning */
154 u32 txttfilltuning; /* H: TX TT tuning */
155 u32 ic_usb; /* control the IC_USB FS/LS transceiver */
156 /* offset: 0x60 */
157 u32 ulpi_viewport; /* indirect access to ULPI PHY */
158#define ULPIWU BIT(31) /* ULPI wakeup */
159#define ULPIRUN BIT(30) /* ULPI read/write run */
160#define ULPIRW BIT(29) /* ULPI read/write control */
161#define ULPISS BIT(27) /* ULPI sync state */
162#define ULPIPORT(u) \
163 (((u)>>24)&7) /* bits 26:24, ULPI port number */
164#define ULPIADDR(u) \
165 (((u)>>16)&0xff) /* bits 23:16, ULPI data address */
166#define ULPIDATRD(u) \
167 (((u)>>8)&0xff) /* bits 15:8, ULPI data read */
168#define ULPIDATWR(u) \
169 (((u)>>0)&0xff) /* bits 7:0, ULPI date write */
170 u8 _reserved6[0x70-0x64];
171 /* offset: 0x70 */
172 u32 configflag; /* H: not used */
173 u32 portsc1; /* port status */
174#define DA(p) \
175 (((p)>>25)&0x7f) /* bits 31:25, device address */
176#define PORTS_SSTS (BIT(24) | BIT(23)) /* suspend status */
177#define PORTS_WKOC BIT(22) /* wake on over-current enable */
178#define PORTS_WKDS BIT(21) /* wake on disconnect enable */
179#define PORTS_WKCN BIT(20) /* wake on connect enable */
180#define PORTS_PTC(p) (((p)>>16)&0xf) /* bits 19:16, port test control */
181#define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
182#define PORTS_PO BIT(13) /* port owner */
183#define PORTS_PP BIT(12) /* port power */
184#define PORTS_LS (BIT(11) | BIT(10)) /* line status */
185#define PORTS_SLP BIT(9) /* suspend using L1 */
186#define PORTS_PR BIT(8) /* port reset */
187#define PORTS_SUSP BIT(7) /* suspend */
188#define PORTS_FPR BIT(6) /* force port resume */
189#define PORTS_OCC BIT(5) /* over-current change */
190#define PORTS_OCA BIT(4) /* over-current active */
191#define PORTS_PEC BIT(3) /* port enable/disable change */
192#define PORTS_PE BIT(2) /* port enable/disable */
193#define PORTS_CSC BIT(1) /* connect status change */
194#define PORTS_CCS BIT(0) /* current connect status */
195 u8 _reserved7[0xb4-0x78];
196 /* offset: 0xb4 */
197 u32 devlc; /* control LPM and each USB port behavior */
198/* bits 31:29, parallel transceiver select */
199#define LPM_PTS(d) (((d)>>29)&7)
200#define LPM_STS BIT(28) /* serial transceiver select */
201#define LPM_PTW BIT(27) /* parallel transceiver width */
202#define LPM_PSPD(d) (((d)>>25)&3) /* bits 26:25, port speed */
203#define LPM_PSPD_MASK (BIT(26) | BIT(25))
204#define LPM_SPEED_FULL 0
205#define LPM_SPEED_LOW 1
206#define LPM_SPEED_HIGH 2
207#define LPM_SRT BIT(24) /* shorten reset time */
208#define LPM_PFSC BIT(23) /* port force full speed connect */
209#define LPM_PHCD BIT(22) /* PHY low power suspend clock disable */
210#define LPM_STL BIT(16) /* STALL reply to LPM token */
211#define LPM_BA(d) \
212 (((d)>>1)&0x7ff) /* bits 11:1, BmAttributes */
213#define LPM_NYT_ACK BIT(0) /* NYET/ACK reply to LPM token */
214 u8 _reserved8[0xf4-0xb8];
215 /* offset: 0xf4 */
216 u32 otgsc; /* On-The-Go status and control */
217#define OTGSC_DPIE BIT(30) /* data pulse interrupt enable */
218#define OTGSC_MSE BIT(29) /* 1 ms timer interrupt enable */
219#define OTGSC_BSEIE BIT(28) /* B session end interrupt enable */
220#define OTGSC_BSVIE BIT(27) /* B session valid interrupt enable */
221#define OTGSC_ASVIE BIT(26) /* A session valid interrupt enable */
222#define OTGSC_AVVIE BIT(25) /* A VBUS valid interrupt enable */
223#define OTGSC_IDIE BIT(24) /* USB ID interrupt enable */
224#define OTGSC_DPIS BIT(22) /* data pulse interrupt status */
225#define OTGSC_MSS BIT(21) /* 1 ms timer interrupt status */
226#define OTGSC_BSEIS BIT(20) /* B session end interrupt status */
227#define OTGSC_BSVIS BIT(19) /* B session valid interrupt status */
228#define OTGSC_ASVIS BIT(18) /* A session valid interrupt status */
229#define OTGSC_AVVIS BIT(17) /* A VBUS valid interrupt status */
230#define OTGSC_IDIS BIT(16) /* USB ID interrupt status */
231#define OTGSC_DPS BIT(14) /* data bus pulsing status */
232#define OTGSC_MST BIT(13) /* 1 ms timer toggle */
233#define OTGSC_BSE BIT(12) /* B session end */
234#define OTGSC_BSV BIT(11) /* B session valid */
235#define OTGSC_ASV BIT(10) /* A session valid */
236#define OTGSC_AVV BIT(9) /* A VBUS valid */
237#define OTGSC_USBID BIT(8) /* USB ID */
238#define OTGSC_HABA BIT(7) /* hw assist B-disconnect to A-connect */
239#define OTGSC_HADP BIT(6) /* hw assist data pulse */
240#define OTGSC_IDPU BIT(5) /* ID pullup */
241#define OTGSC_DP BIT(4) /* data pulsing */
242#define OTGSC_OT BIT(3) /* OTG termination */
243#define OTGSC_HAAR BIT(2) /* hw assist auto reset */
244#define OTGSC_VC BIT(1) /* VBUS charge */
245#define OTGSC_VD BIT(0) /* VBUS discharge */
246 u32 usbmode;
247#define MODE_VBPS BIT(5) /* R/W VBUS power select */
248#define MODE_SDIS BIT(4) /* R/W stream disable mode */
249#define MODE_SLOM BIT(3) /* R/W setup lockout mode */
250#define MODE_ENSE BIT(2) /* endian select */
251#define MODE_CM(u) (((u)>>0)&3) /* bits 1:0, controller mode */
252#define MODE_IDLE 0
253#define MODE_DEVICE 2
254#define MODE_HOST 3
255 u8 _reserved9[0x100-0xfc];
256 /* offset: 0x100 */
257 u32 endptnak;
258#define EPTN(e) \
259 (((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK */
260#define EPRN(e) \
261 (((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK */
262 u32 endptnaken;
263#define EPTNE(e) \
264 (((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK enable */
265#define EPRNE(e) \
266 (((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK enable */
267 u32 endptsetupstat;
268#define SETUPSTAT_MASK (0xffff << 0) /* bits 15:0 */
269#define EP0SETUPSTAT_MASK 1
270 u32 endptprime;
271/* bits 31:16, prime endpoint transmit buffer */
272#define PETB(e) (((e)>>16)&0xffff)
273/* bits 15:0, prime endpoint receive buffer */
274#define PERB(e) (((e)>>0)&0xffff)
275 /* offset: 0x110 */
276 u32 endptflush;
277/* bits 31:16, flush endpoint transmit buffer */
278#define FETB(e) (((e)>>16)&0xffff)
279/* bits 15:0, flush endpoint receive buffer */
280#define FERB(e) (((e)>>0)&0xffff)
281 u32 endptstat;
282/* bits 31:16, endpoint transmit buffer ready */
283#define ETBR(e) (((e)>>16)&0xffff)
284/* bits 15:0, endpoint receive buffer ready */
285#define ERBR(e) (((e)>>0)&0xffff)
286 u32 endptcomplete;
287/* bits 31:16, endpoint transmit complete event */
288#define ETCE(e) (((e)>>16)&0xffff)
289/* bits 15:0, endpoint receive complete event */
290#define ERCE(e) (((e)>>0)&0xffff)
291 /* offset: 0x11c */
292 u32 endptctrl[16];
293#define EPCTRL_TXE BIT(23) /* TX endpoint enable */
294#define EPCTRL_TXR BIT(22) /* TX data toggle reset */
295#define EPCTRL_TXI BIT(21) /* TX data toggle inhibit */
296#define EPCTRL_TXT(e) (((e)>>18)&3) /* bits 19:18, TX endpoint type */
297#define EPCTRL_TXT_SHIFT 18
298#define EPCTRL_TXD BIT(17) /* TX endpoint data source */
299#define EPCTRL_TXS BIT(16) /* TX endpoint STALL */
300#define EPCTRL_RXE BIT(7) /* RX endpoint enable */
301#define EPCTRL_RXR BIT(6) /* RX data toggle reset */
302#define EPCTRL_RXI BIT(5) /* RX data toggle inhibit */
303#define EPCTRL_RXT(e) (((e)>>2)&3) /* bits 3:2, RX endpoint type */
304#define EPCTRL_RXT_SHIFT 2 /* bits 19:18, TX endpoint type */
305#define EPCTRL_RXD BIT(1) /* RX endpoint data sink */
306#define EPCTRL_RXS BIT(0) /* RX endpoint STALL */
307} __attribute__ ((packed));
308
309#endif /* __LANGWELL_UDC_H */
310
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