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authorJarod Wilson <jarod@redhat.com>2010-10-15 10:07:37 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-10-21 05:54:20 -0400
commit4e6e29ad10dc8ff174d7fd15b54e32c783fd8ab8 (patch)
tree16498c200bbd20e5af4422c493fbac85e178329d
parent06e6588edfb2be6fb3e544097c07274bd7b64084 (diff)
[media] IR/nuvoton: address all checkpatch.pl issues
The driver was missing KERN_ facilities on a number of printks. The register dump functions have been updated to use KERN_INFO, so that the register dump gets logged in syslog (they only run on driver load, and only when debug is enabled). The buffer dump routine now uses KERN_DEBUG, as that spew will happen quite frequently (several times every IR signal), and shouldn't need to be logged. Also split up the small handful of lines that were just over 80 characaters, and fixed the ioctl.h include. Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/media/IR/nuvoton-cir.c112
-rw-r--r--drivers/media/IR/nuvoton-cir.h2
2 files changed, 60 insertions, 54 deletions
diff --git a/drivers/media/IR/nuvoton-cir.c b/drivers/media/IR/nuvoton-cir.c
index fdb280ed01ce..2f0f78078b57 100644
--- a/drivers/media/IR/nuvoton-cir.c
+++ b/drivers/media/IR/nuvoton-cir.c
@@ -126,40 +126,43 @@ static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
126 return val; 126 return val;
127} 127}
128 128
129#define pr_reg(text, ...) \
130 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
131
129/* dump current cir register contents */ 132/* dump current cir register contents */
130static void cir_dump_regs(struct nvt_dev *nvt) 133static void cir_dump_regs(struct nvt_dev *nvt)
131{ 134{
132 nvt_efm_enable(nvt); 135 nvt_efm_enable(nvt);
133 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 136 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
134 137
135 printk("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); 138 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
136 printk(" * CR CIR ACTIVE : 0x%x\n", 139 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
137 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 140 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
138 printk(" * CR CIR BASE ADDR: 0x%x\n", 141 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
139 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 142 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
140 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 143 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
141 printk(" * CR CIR IRQ NUM: 0x%x\n", 144 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
142 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 145 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
143 146
144 nvt_efm_disable(nvt); 147 nvt_efm_disable(nvt);
145 148
146 printk("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); 149 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
147 printk(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); 150 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
148 printk(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); 151 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
149 printk(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); 152 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
150 printk(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); 153 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
151 printk(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); 154 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
152 printk(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); 155 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
153 printk(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); 156 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
154 printk(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); 157 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
155 printk(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); 158 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
156 printk(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); 159 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
157 printk(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); 160 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
158 printk(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); 161 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
159 printk(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); 162 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
160 printk(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); 163 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
161 printk(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); 164 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
162 printk(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); 165 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
163} 166}
164 167
165/* dump current cir wake register contents */ 168/* dump current cir wake register contents */
@@ -170,59 +173,59 @@ static void cir_wake_dump_regs(struct nvt_dev *nvt)
170 nvt_efm_enable(nvt); 173 nvt_efm_enable(nvt);
171 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 174 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
172 175
173 printk("%s: Dump CIR WAKE logical device registers:\n", 176 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
174 NVT_DRIVER_NAME); 177 NVT_DRIVER_NAME);
175 printk(" * CR CIR WAKE ACTIVE : 0x%x\n", 178 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
176 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 179 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
177 printk(" * CR CIR WAKE BASE ADDR: 0x%x\n", 180 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
178 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 181 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
179 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 182 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
180 printk(" * CR CIR WAKE IRQ NUM: 0x%x\n", 183 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
181 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 184 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
182 185
183 nvt_efm_disable(nvt); 186 nvt_efm_disable(nvt);
184 187
185 printk("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); 188 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
186 printk(" * IRCON: 0x%x\n", 189 pr_reg(" * IRCON: 0x%x\n",
187 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); 190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
188 printk(" * IRSTS: 0x%x\n", 191 pr_reg(" * IRSTS: 0x%x\n",
189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); 192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
190 printk(" * IREN: 0x%x\n", 193 pr_reg(" * IREN: 0x%x\n",
191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); 194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
192 printk(" * FIFO CMP DEEP: 0x%x\n", 195 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); 196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
194 printk(" * FIFO CMP TOL: 0x%x\n", 197 pr_reg(" * FIFO CMP TOL: 0x%x\n",
195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); 198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
196 printk(" * FIFO COUNT: 0x%x\n", 199 pr_reg(" * FIFO COUNT: 0x%x\n",
197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); 200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
198 printk(" * SLCH: 0x%x\n", 201 pr_reg(" * SLCH: 0x%x\n",
199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); 202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
200 printk(" * SLCL: 0x%x\n", 203 pr_reg(" * SLCL: 0x%x\n",
201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); 204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
202 printk(" * FIFOCON: 0x%x\n", 205 pr_reg(" * FIFOCON: 0x%x\n",
203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); 206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
204 printk(" * SRXFSTS: 0x%x\n", 207 pr_reg(" * SRXFSTS: 0x%x\n",
205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); 208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
206 printk(" * SAMPLE RX FIFO: 0x%x\n", 209 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); 210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
208 printk(" * WR FIFO DATA: 0x%x\n", 211 pr_reg(" * WR FIFO DATA: 0x%x\n",
209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); 212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
210 printk(" * RD FIFO ONLY: 0x%x\n", 213 pr_reg(" * RD FIFO ONLY: 0x%x\n",
211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
212 printk(" * RD FIFO ONLY IDX: 0x%x\n", 215 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); 216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
214 printk(" * FIFO IGNORE: 0x%x\n", 217 pr_reg(" * FIFO IGNORE: 0x%x\n",
215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); 218 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
216 printk(" * IRFSM: 0x%x\n", 219 pr_reg(" * IRFSM: 0x%x\n",
217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); 220 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
218 221
219 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); 222 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
220 printk("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); 223 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
221 printk("* Contents = "); 224 pr_reg("* Contents = ");
222 for (i = 0; i < fifo_len; i++) 225 for (i = 0; i < fifo_len; i++)
223 printk("%02x ", 226 printk(KERN_CONT "%02x ",
224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
225 printk("\n"); 228 printk(KERN_CONT "\n");
226} 229}
227 230
228/* detect hardware features */ 231/* detect hardware features */
@@ -362,8 +365,10 @@ static void nvt_cir_regs_init(struct nvt_dev *nvt)
362 * Enable TX and RX, specify carrier on = low, off = high, and set 365 * Enable TX and RX, specify carrier on = low, off = high, and set
363 * sample period (currently 50us) 366 * sample period (currently 50us)
364 */ 367 */
365 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | CIR_IRCON_RXINV | 368 nvt_cir_reg_write(nvt,
366 CIR_IRCON_SAMPLE_PERIOD_SEL, CIR_IRCON); 369 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
370 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
371 CIR_IRCON);
367 372
368 /* clear hardware rx and tx fifos */ 373 /* clear hardware rx and tx fifos */
369 nvt_clear_cir_fifo(nvt); 374 nvt_clear_cir_fifo(nvt);
@@ -425,7 +430,8 @@ static void nvt_enable_wake(struct nvt_dev *nvt)
425 430
426 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | 431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
427 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | 432 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
428 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, CIR_WAKE_IRCON); 433 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
434 CIR_WAKE_IRCON);
429 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); 435 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
430 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); 436 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
431} 437}
@@ -560,10 +566,10 @@ static void nvt_dump_rx_buf(struct nvt_dev *nvt)
560{ 566{
561 int i; 567 int i;
562 568
563 printk("%s (len %d): ", __func__, nvt->pkts); 569 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
564 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) 570 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
565 printk("0x%02x ", nvt->buf[i]); 571 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
566 printk("\n"); 572 printk(KERN_CONT "\n");
567} 573}
568 574
569/* 575/*
diff --git a/drivers/media/IR/nuvoton-cir.h b/drivers/media/IR/nuvoton-cir.h
index 12bfe899fd1a..62dc53017c8e 100644
--- a/drivers/media/IR/nuvoton-cir.h
+++ b/drivers/media/IR/nuvoton-cir.h
@@ -26,7 +26,7 @@
26 */ 26 */
27 27
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29#include <asm/ioctl.h> 29#include <linux/ioctl.h>
30 30
31/* platform driver name to register */ 31/* platform driver name to register */
32#define NVT_DRIVER_NAME "nuvoton-cir" 32#define NVT_DRIVER_NAME "nuvoton-cir"