diff options
author | Miaoqing Pan <miaoqing@qca.qualcomm.com> | 2014-11-06 00:22:23 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2014-11-11 16:24:18 -0500 |
commit | 4e6ce4dc7ce71d0886908d55129d5d6482a27ff9 (patch) | |
tree | 6f6dbb1181866103987a897801bb615223900072 | |
parent | 0cd75b19899fd86b51a6480fb8c00dcd85a54591 (diff) |
ath9k: Fix RTC_DERIVED_CLK usage
Based on the reference clock, which could be 25MHz or 40MHz,
AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
But, when a chip reset is done, processing the initvals
sets the register back to the default value.
Fix this by moving the code in ath9k_hw_init_pll() to
ar9003_hw_override_ini(). Also, do this override for AR9531.
Cc: stable@vger.kernel.org
Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 13 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 13 |
2 files changed, 13 insertions, 13 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 697c4ae90af0..1e8ea5e4d4ca 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) | |||
664 | ah->enabled_cals |= TX_CL_CAL; | 664 | ah->enabled_cals |= TX_CL_CAL; |
665 | else | 665 | else |
666 | ah->enabled_cals &= ~TX_CL_CAL; | 666 | ah->enabled_cals &= ~TX_CL_CAL; |
667 | |||
668 | if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { | ||
669 | if (ah->is_clk_25mhz) { | ||
670 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); | ||
671 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); | ||
672 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); | ||
673 | } else { | ||
674 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); | ||
675 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); | ||
676 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); | ||
677 | } | ||
678 | udelay(100); | ||
679 | } | ||
667 | } | 680 | } |
668 | 681 | ||
669 | static void ar9003_hw_prog_ini(struct ath_hw *ah, | 682 | static void ar9003_hw_prog_ini(struct ath_hw *ah, |
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 8be4b1453394..2ad605760e21 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -861,19 +861,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
861 | udelay(RTC_PLL_SETTLE_DELAY); | 861 | udelay(RTC_PLL_SETTLE_DELAY); |
862 | 862 | ||
863 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | 863 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
864 | |||
865 | if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { | ||
866 | if (ah->is_clk_25mhz) { | ||
867 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); | ||
868 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); | ||
869 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); | ||
870 | } else { | ||
871 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); | ||
872 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); | ||
873 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); | ||
874 | } | ||
875 | udelay(100); | ||
876 | } | ||
877 | } | 864 | } |
878 | 865 | ||
879 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, | 866 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |