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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2013-09-04 12:31:14 -0400
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2013-09-29 15:05:37 -0400
commit4db7634336156254b179b66f6a9fe90d75c44ee4 (patch)
treec42fa620768936cae5af8291a01404a0574095d6
parenteb6b036dde364c528807f53ee8c8e5c9b0e46c34 (diff)
ARM: nomadik: remove mtu initalization from .init_time
Nomadik clock initialization is properly done in clk-nomadik since patch "clk: nomadik: set all timers to use 2.4 MHz TIMCLK". Therefore, this patch removes now redundant mtu initialization from .init_time callback. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--arch/arm/mach-nomadik/cpu-8815.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 13e0df9c11ce..0fcb14966d5a 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -113,36 +113,10 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
113 writel(1, srcbase + 0x18); 113 writel(1, srcbase + 0x18);
114} 114}
115 115
116/* Initial value for SRC control register: all timers use MXTAL/8 source */
117#define SRC_CR_INIT_MASK 0x00007fff
118#define SRC_CR_INIT_VAL 0x2aaa8000
119
120static void __init cpu8815_timer_init_of(void) 116static void __init cpu8815_timer_init_of(void)
121{ 117{
122 struct device_node *mtu;
123 void __iomem *base;
124 int irq;
125 u32 src_cr;
126
127 /* We need this to be up now */ 118 /* We need this to be up now */
128 nomadik_clk_init(); 119 nomadik_clk_init();
129
130 mtu = of_find_node_by_path("/mtu@101e2000");
131 if (!mtu)
132 return;
133 base = of_iomap(mtu, 0);
134 if (WARN_ON(!base))
135 return;
136 irq = irq_of_parse_and_map(mtu, 0);
137
138 pr_info("Remapped MTU @ %p, irq: %d\n", base, irq);
139
140 /* Configure timer sources in "system reset controller" ctrl reg */
141 src_cr = readl(base);
142 src_cr &= SRC_CR_INIT_MASK;
143 src_cr |= SRC_CR_INIT_VAL;
144 writel(src_cr, base);
145
146 clocksource_of_init(); 120 clocksource_of_init();
147} 121}
148 122