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authorDavid S. Miller <davem@davemloft.net>2013-02-05 14:54:49 -0500
committerDavid S. Miller <davem@davemloft.net>2013-02-05 14:54:49 -0500
commit4d9e01da87caa9bc63c3284ab38e0dd53eeab6ae (patch)
tree82ba7d69dde189b2b58b7d1b80fc13f40a4641ff
parentca2eb5679f8ddffff60156af42595df44a315ef0 (diff)
parentc560451c2009b94820460e06d3f7c258f7234948 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== This series contains updates to e1000e and ixgbe. Majority of the patches are against e1000e, where Bruce makes several cosmetic #define moves into header files. In addition, Bruce does a cleanup of braces to resolve checkpatch warnings (when using the strict option). Ixgbe patches contain several fixes as well as updating the copyright. The fixes from Josh Hay, resolved a possible NULL pointer dereference and resolved Smatch warnings by fixing return values and memcpy parameters. Alex provides 2 fixes, the first is to replace rmb() with read_barrier_depends() in the Tx cleanup. The second fixes an MTU warning when using SR-IOV which corrects the fact that we were using 1522 to test for the max frame size in ixgbe_change_mtu and 1518 in ixgbe_set_vf_lpe. The difference was the addition of VLAN_HLEN, which we only need to add in the case of computing a buffer size, but not a filter size. Lastly, a patch from Emil which is based on a community patch from Aurélien Guillaume which adds functions needed for reading SFF-8472 diagnostic data from SFP modules. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.c63
-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.h95
-rw-r--r--drivers/net/ethernet/intel/e1000e/82571.c16
-rw-r--r--drivers/net/ethernet/intel/e1000e/82571.h58
-rw-r--r--drivers/net/ethernet/intel/e1000e/defines.h38
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h207
-rw-r--r--drivers/net/ethernet/intel/e1000e/ethtool.c6
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h347
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.c127
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.h268
-rw-r--r--drivers/net/ethernet/intel/e1000e/mac.h74
-rw-r--r--drivers/net/ethernet/intel/e1000e/manage.c13
-rw-r--r--drivers/net/ethernet/intel/e1000e/manage.h72
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c15
-rw-r--r--drivers/net/ethernet/intel/e1000e/nvm.h47
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.c43
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.h242
-rw-r--r--drivers/net/ethernet/intel/e1000e/regs.h252
-rw-r--r--drivers/net/ethernet/intel/ixgbe/Makefile2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe.h4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c47
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c3
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c9
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c11
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c8
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c18
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h11
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.c2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_type.h3
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c3
47 files changed, 1228 insertions, 910 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index a00457abce69..e0991388664c 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -32,69 +32,6 @@
32 32
33#include "e1000.h" 33#include "e1000.h"
34 34
35#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
36#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
37#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
38#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
39
40#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
41#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
42#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
43
44#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
45#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
46#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
47
48#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
49#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
50
51#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
52#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
53
54#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
55#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
56
57/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
58#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
59#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
60#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
61#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
62#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
63
64/* PHY Specific Control Register 2 (Page 0, Register 26) */
65#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
66 /* 1=Reverse Auto-Negotiation */
67
68/* MAC Specific Control Register (Page 2, Register 21) */
69/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
70#define GG82563_MSCR_TX_CLK_MASK 0x0007
71#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
72#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
73#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
74
75#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
76
77/* DSP Distance Register (Page 5, Register 26) */
78#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
79 1 = 50-80M
80 2 = 80-110M
81 3 = 110-140M
82 4 = >140M
83 */
84
85/* Kumeran Mode Control Register (Page 193, Register 16) */
86#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
87
88/* Max number of times Kumeran read/write should be validated */
89#define GG82563_MAX_KMRN_RETRY 0x5
90
91/* Power Management Control Register (Page 193, Register 20) */
92#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
94
95/* In-Band Control Register (Page 194, Register 18) */
96#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
97
98/* A table for the GG82563 cable length where the range is defined 35/* A table for the GG82563 cable length where the range is defined
99 * with a lower bound at "index" and the upper bound at 36 * with a lower bound at "index" and the upper bound at
100 * "index + 5". 37 * "index + 5".
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.h b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
new file mode 100644
index 000000000000..90d363b2d280
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
@@ -0,0 +1,95 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_80003ES2LAN_H_
30#define _E1000E_80003ES2LAN_H_
31
32#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
33#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
34#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
35#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
36
37#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
38#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
39#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
40
41#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
42#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
43#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
44
45#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
46#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
47
48#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
49#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
50
51#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
52#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
53
54/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
55#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
56#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
57#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
58#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
59#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
60
61/* PHY Specific Control Register 2 (Page 0, Register 26) */
62#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
63
64/* MAC Specific Control Register (Page 2, Register 21) */
65/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
66#define GG82563_MSCR_TX_CLK_MASK 0x0007
67#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
68#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
69#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
70
71#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
72
73/* DSP Distance Register (Page 5, Register 26)
74 * 0 = <50M
75 * 1 = 50-80M
76 * 2 = 80-100M
77 * 3 = 110-140M
78 * 4 = >140M
79 */
80#define GG82563_DSPD_CABLE_LENGTH 0x0007
81
82/* Kumeran Mode Control Register (Page 193, Register 16) */
83#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
84
85/* Max number of times Kumeran read/write should be validated */
86#define GG82563_MAX_KMRN_RETRY 0x5
87
88/* Power Management Control Register (Page 193, Register 20) */
89/* 1=Enable SERDES Electrical Idle */
90#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
91
92/* In-Band Control Register (Page 194, Register 18) */
93#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
94
95#endif
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index cf86090edd3b..2faffbde179e 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -44,21 +44,6 @@
44 44
45#include "e1000.h" 45#include "e1000.h"
46 46
47#define ID_LED_RESERVED_F746 0xF746
48#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
49 (ID_LED_OFF1_ON2 << 8) | \
50 (ID_LED_DEF1_DEF2 << 4) | \
51 (ID_LED_DEF1_DEF2))
52
53#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
54#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
55#define E1000_BASE1000T_STATUS 10
56#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
57#define E1000_RECEIVE_ERROR_COUNTER 21
58#define E1000_RECEIVE_ERROR_MAX 0xFFFF
59
60#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
61
62static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 47static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
63static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 48static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
64static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 49static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
@@ -1549,7 +1534,6 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1549 rxcw = er32(RXCW); 1534 rxcw = er32(RXCW);
1550 1535
1551 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1536 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1552
1553 /* Receiver is synchronized with no invalid bits. */ 1537 /* Receiver is synchronized with no invalid bits. */
1554 switch (mac->serdes_link_state) { 1538 switch (mac->serdes_link_state) {
1555 case e1000_serdes_link_autoneg_complete: 1539 case e1000_serdes_link_autoneg_complete:
diff --git a/drivers/net/ethernet/intel/e1000e/82571.h b/drivers/net/ethernet/intel/e1000e/82571.h
new file mode 100644
index 000000000000..85cb1a3b7cd4
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/82571.h
@@ -0,0 +1,58 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_82571_H_
30#define _E1000E_82571_H_
31
32#define ID_LED_RESERVED_F746 0xF746
33#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
34 (ID_LED_OFF1_ON2 << 8) | \
35 (ID_LED_DEF1_DEF2 << 4) | \
36 (ID_LED_DEF1_DEF2))
37
38#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
39#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
40
41/* Intr Throttling - RW */
42#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
43
44#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
45#define E1000_EIAC_MASK_82574 0x01F00000
46
47/* Manageability Operation Mode mask */
48#define E1000_NVM_INIT_CTRL2_MNGM 0x6000
49
50#define E1000_BASE1000T_STATUS 10
51#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
52#define E1000_RECEIVE_ERROR_COUNTER 21
53#define E1000_RECEIVE_ERROR_MAX 0xFFFF
54bool e1000_check_phy_82574(struct e1000_hw *hw);
55bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
56void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
57
58#endif
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index 615b900c0152..fc3a4fe1ac71 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -606,8 +606,6 @@
606#define NVM_ALT_MAC_ADDR_PTR 0x0037 606#define NVM_ALT_MAC_ADDR_PTR 0x0037
607#define NVM_CHECKSUM_REG 0x003F 607#define NVM_CHECKSUM_REG 0x003F
608 608
609#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
610
611#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 609#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
612#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 610#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
613 611
@@ -751,38 +749,6 @@
751/* BME1000 PHY Specific Control Register */ 749/* BME1000 PHY Specific Control Register */
752#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 750#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
753 751
754/* PHY Low Power Idle Control */
755#define I82579_LPI_CTRL PHY_REG(772, 20)
756#define I82579_LPI_CTRL_100_ENABLE 0x2000
757#define I82579_LPI_CTRL_1000_ENABLE 0x4000
758#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
759#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
760
761/* Extended Management Interface (EMI) Registers */
762#define I82579_EMI_ADDR 0x10
763#define I82579_EMI_DATA 0x11
764#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
765#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
766#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
767#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
768#define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */
769#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
770#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
771#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
772#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
773#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */
774#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
775#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
776#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
777#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
778
779#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
780#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
781
782#define PHY_PAGE_SHIFT 5
783#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
784 ((reg) & MAX_PHY_REG_ADDRESS))
785
786/* Bits... 752/* Bits...
787 * 15-5: page 753 * 15-5: page
788 * 4-0: register offset 754 * 4-0: register offset
@@ -829,8 +795,4 @@
829/* SerDes Control */ 795/* SerDes Control */
830#define E1000_GEN_POLL_TIMEOUT 640 796#define E1000_GEN_POLL_TIMEOUT 640
831 797
832/* FW Semaphore */
833#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
834#define E1000_FWSM_WLOCK_MAC_SHIFT 7
835
836#endif /* _E1000_DEFINES_H_ */ 798#endif /* _E1000_DEFINES_H_ */
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 4b0bd9c225cc..fcc758138b8a 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -95,70 +95,6 @@ struct e1000_info;
95 95
96#define DEFAULT_JUMBO 9234 96#define DEFAULT_JUMBO 9234
97 97
98/* BM/HV Specific Registers */
99#define BM_PORT_CTRL_PAGE 769
100
101#define PHY_UPPER_SHIFT 21
102#define BM_PHY_REG(page, reg) \
103 (((reg) & MAX_PHY_REG_ADDRESS) |\
104 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
105 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
106
107/* PHY Wakeup Registers and defines */
108#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
109#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
110#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
111#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
112#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
113#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
114#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
115#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
116#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
117#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
118
119#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
120#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
121#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
122#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
123#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
124#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
125#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
126
127#define HV_STATS_PAGE 778
128#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
129#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
130#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
131#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
132#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
133#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
134#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
135#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
136#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
137#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
138#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
139#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
140#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
141#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
142
143#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
144
145/* BM PHY Copper Specific Status */
146#define BM_CS_STATUS 17
147#define BM_CS_STATUS_LINK_UP 0x0400
148#define BM_CS_STATUS_RESOLVED 0x0800
149#define BM_CS_STATUS_SPEED_MASK 0xC000
150#define BM_CS_STATUS_SPEED_1000 0x8000
151
152/* 82577 Mobile Phy Status Register */
153#define HV_M_STATUS 26
154#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
155#define HV_M_STATUS_SPEED_MASK 0x0300
156#define HV_M_STATUS_SPEED_1000 0x0200
157#define HV_M_STATUS_LINK_UP 0x0040
158
159#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
160#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
161
162/* Time to wait before putting the device into D3 if there's no link (in ms). */ 98/* Time to wait before putting the device into D3 if there's no link (in ms). */
163#define LINK_TIMEOUT 100 99#define LINK_TIMEOUT 100
164 100
@@ -574,137 +510,6 @@ extern const struct e1000_info e1000_pch2_info;
574extern const struct e1000_info e1000_pch_lpt_info; 510extern const struct e1000_info e1000_pch_lpt_info;
575extern const struct e1000_info e1000_es2_info; 511extern const struct e1000_info e1000_es2_info;
576 512
577extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
578 u32 pba_num_size);
579
580extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
581
582extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
583extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
584
585extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
586extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
587 bool state);
588extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
589extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
590extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
591extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
592extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
593extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
594extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
595
596extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
597extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
598extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
599extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
600extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
601extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
602extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
603extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
604extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
605extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
606extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
607extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
608extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
609extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
610extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
611extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
612extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
613extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
614extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
615extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
616extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
617extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
618extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
619 u8 *mc_addr_list,
620 u32 mc_addr_count);
621extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
622extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
623extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
624extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
625extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
626extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
627extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
628extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
629extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
630extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
631extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
632extern void e1000e_reset_adaptive(struct e1000_hw *hw);
633extern void e1000e_update_adaptive(struct e1000_hw *hw);
634
635extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
636extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
637extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
638extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
639extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
640extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
641extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
642extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
643extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
644extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
645 u16 *data);
646extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
647extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
648extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
649extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
650 u16 data);
651extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
652extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
653extern s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
654extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
655extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
656extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
657extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
658extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
659extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
660extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
661extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
662extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
663extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
664 u16 *phy_reg);
665extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
666 u16 *phy_reg);
667extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
668extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
669extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
670extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
671extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
672 u16 data);
673extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
674extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
675 u16 *data);
676extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
677 u32 usec_interval, bool *success);
678extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
679extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
680extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
681extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
682extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
683extern s32 e1000e_check_downshift(struct e1000_hw *hw);
684extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
685extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
686 u16 *data);
687extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
688 u16 *data);
689extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
690extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
691 u16 data);
692extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
693 u16 data);
694extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
695extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
696extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
697extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
698extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
699extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
700
701extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
702extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
703extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
704extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
705extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
706extern bool e1000_check_phy_82574(struct e1000_hw *hw);
707extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
708extern void e1000e_ptp_init(struct e1000_adapter *adapter); 513extern void e1000e_ptp_init(struct e1000_adapter *adapter);
709extern void e1000e_ptp_remove(struct e1000_adapter *adapter); 514extern void e1000e_ptp_remove(struct e1000_adapter *adapter);
710 515
@@ -733,15 +538,7 @@ static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
733 return hw->phy.ops.write_reg_locked(hw, offset, data); 538 return hw->phy.ops.write_reg_locked(hw, offset, data);
734} 539}
735 540
736extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
737extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
738extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
739extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
740extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
741extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
742extern void e1000e_release_nvm(struct e1000_hw *hw);
743extern void e1000e_reload_nvm_generic(struct e1000_hw *hw); 541extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
744extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
745 542
746static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 543static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
747{ 544{
@@ -776,10 +573,6 @@ static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
776 return hw->phy.ops.get_info(hw); 573 return hw->phy.ops.get_info(hw);
777} 574}
778 575
779extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
780extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
781extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
782
783static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 576static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
784{ 577{
785 return readl(hw->hw_addr + reg); 578 return readl(hw->hw_addr + reg);
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index c6c3e921686d..2c1813737f6d 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -130,7 +130,6 @@ static int e1000_get_settings(struct net_device *netdev,
130 u32 speed; 130 u32 speed;
131 131
132 if (hw->phy.media_type == e1000_media_type_copper) { 132 if (hw->phy.media_type == e1000_media_type_copper) {
133
134 ecmd->supported = (SUPPORTED_10baseT_Half | 133 ecmd->supported = (SUPPORTED_10baseT_Half |
135 SUPPORTED_10baseT_Full | 134 SUPPORTED_10baseT_Full |
136 SUPPORTED_100baseT_Half | 135 SUPPORTED_100baseT_Half |
@@ -328,12 +327,12 @@ static int e1000_set_settings(struct net_device *netdev,
328 } 327 }
329 328
330 /* reset the link */ 329 /* reset the link */
331
332 if (netif_running(adapter->netdev)) { 330 if (netif_running(adapter->netdev)) {
333 e1000e_down(adapter); 331 e1000e_down(adapter);
334 e1000e_up(adapter); 332 e1000e_up(adapter);
335 } else 333 } else {
336 e1000e_reset(adapter); 334 e1000e_reset(adapter);
335 }
337 336
338 clear_bit(__E1000_RESETTING, &adapter->state); 337 clear_bit(__E1000_RESETTING, &adapter->state);
339 return 0; 338 return 0;
@@ -1355,7 +1354,6 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1355 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg); 1354 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg);
1356 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1); 1355 e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1);
1357 /* Enable loopback on the PHY */ 1356 /* Enable loopback on the PHY */
1358#define I82577_PHY_LBK_CTRL 19
1359 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001); 1357 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001);
1360 break; 1358 break;
1361 default: 1359 default:
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index f32b19af9a72..1e6b889aee87 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -29,347 +29,11 @@
29#ifndef _E1000_HW_H_ 29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_ 30#define _E1000_HW_H_
31 31
32#include "regs.h"
32#include "defines.h" 33#include "defines.h"
33 34
34struct e1000_hw; 35struct e1000_hw;
35 36
36enum e1e_registers {
37 E1000_CTRL = 0x00000, /* Device Control - RW */
38 E1000_STATUS = 0x00008, /* Device Status - RO */
39 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
40 E1000_EERD = 0x00014, /* EEPROM Read - RW */
41 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
42 E1000_FLA = 0x0001C, /* Flash Access - RW */
43 E1000_MDIC = 0x00020, /* MDI Control - RW */
44 E1000_SCTL = 0x00024, /* SerDes Control - RW */
45 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
46 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
47 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
48 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
49 E1000_FCT = 0x00030, /* Flow Control Type - RW */
50 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
51 E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
52 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
53 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
54 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
55 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
56 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
57 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
58 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
59 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
60 E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
61 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
62#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
63 E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
64 E1000_RCTL = 0x00100, /* Rx Control - RW */
65 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
66 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
67 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
68 E1000_TCTL = 0x00400, /* Tx Control - RW */
69 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
70 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
71 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
72 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
73 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
74 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
75 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
76#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
77 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
78 E1000_PBS = 0x01008, /* Packet Buffer Size */
79 E1000_PBECCSTS = 0x0100C, /* Packet Buffer ECC Status - RW */
80 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
81 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
82 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
83 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
84 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
85 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
86 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
87 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
88/* Convenience macros
89 *
90 * Note: "_n" is the queue number of the register to be written to.
91 *
92 * Example usage:
93 * E1000_RDBAL(current_rx_queue)
94 */
95 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
96#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
97 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
98#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
99 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
100#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
101 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
102#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
103 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
104#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
105 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
106 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
107#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
108 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
109
110 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
111 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
112#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
113 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
114#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
115 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
116#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
117 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
118#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
119 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
120#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
121 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
122 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
123#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
124 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
125 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
126#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
127 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
128 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
129 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
130 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
131 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
132 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
133 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
134 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
135 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
136 E1000_COLC = 0x04028, /* Collision Count - R/clr */
137 E1000_DC = 0x04030, /* Defer Count - R/clr */
138 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
139 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
140 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
141 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
142 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
143 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
144 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
145 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
146 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
147 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
148 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
149 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
150 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
151 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
152 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
153 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
154 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
155 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
156 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
157 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
158 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
159 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
160 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
161 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
162 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
163 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
164 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
165 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
166 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
167 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
168 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
169 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
170 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
171 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
172 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
173 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
174 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
175 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
176 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
177 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
178 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
179 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
180 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
181 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
182 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
183 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
184 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
185 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
186 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
187 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
188 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
189 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
190 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
191 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
192 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
193 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
194 E1000_PCS_LCTL = 0x04208, /* PCS Link Control - RW */
195 E1000_PCS_LSTAT = 0x0420C, /* PCS Link Status - RO */
196 E1000_PCS_ANADV = 0x04218, /* AN advertisement - RW */
197 E1000_PCS_LPAB = 0x0421C, /* Link Partner Ability - RW */
198 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
199 E1000_RFCTL = 0x05008, /* Receive Filter Control */
200 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
201 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
202#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
203#define E1000_RA (E1000_RAL(0))
204 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
205#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
206 E1000_SHRAL_PCH_LPT_BASE = 0x05408,
207#define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
208 E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
209#define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
210 E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
211#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
212 E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
213#define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
214 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
215 E1000_WUC = 0x05800, /* Wakeup Control - RW */
216 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
217 E1000_WUS = 0x05810, /* Wakeup Status - RO */
218 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
219 E1000_MANC = 0x05820, /* Management Control - RW */
220 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
221 E1000_HOST_IF = 0x08800, /* Host Interface */
222
223 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
224 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
225 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
226#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
227 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
228 E1000_GCR = 0x05B00, /* PCI-Ex Control */
229 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
230 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
231 E1000_SWSM = 0x05B50, /* SW Semaphore */
232 E1000_FWSM = 0x05B54, /* FW Semaphore */
233 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
234 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
235#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
236 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
237#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
238 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
239 E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
240#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
241#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
242 E1000_HICR = 0x08F00, /* Host Interface Control */
243 E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
244 E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
245 E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
246 E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
247 E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
248 E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
249 E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
250 E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
251 E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
252 E1000_RXMTRL = 0x0B634, /* Timesync Rx EtherType and Msg Type - RW */
253 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
254};
255
256#define E1000_MAX_PHY_ADDR 4
257
258/* IGP01E1000 Specific Registers */
259#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
260#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
261#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
262#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
263#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
264#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
265#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
266#define IGP_PAGE_SHIFT 5
267#define PHY_REG_MASK 0x1F
268
269#define BM_WUC_PAGE 800
270#define BM_WUC_ADDRESS_OPCODE 0x11
271#define BM_WUC_DATA_OPCODE 0x12
272#define BM_WUC_ENABLE_PAGE 769
273#define BM_WUC_ENABLE_REG 17
274#define BM_WUC_ENABLE_BIT (1 << 2)
275#define BM_WUC_HOST_WU_BIT (1 << 4)
276#define BM_WUC_ME_WU_BIT (1 << 5)
277
278#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
279#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
280#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
281
282#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
283#define IGP01E1000_PHY_POLARITY_MASK 0x0078
284
285#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
286#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
287
288#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
289
290#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
291#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
292#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
293
294#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
295
296#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
297#define IGP01E1000_PSSR_MDIX 0x0800
298#define IGP01E1000_PSSR_SPEED_MASK 0xC000
299#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
300
301#define IGP02E1000_PHY_CHANNEL_NUM 4
302#define IGP02E1000_PHY_AGC_A 0x11B1
303#define IGP02E1000_PHY_AGC_B 0x12B1
304#define IGP02E1000_PHY_AGC_C 0x14B1
305#define IGP02E1000_PHY_AGC_D 0x18B1
306
307#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
308#define IGP02E1000_AGC_LENGTH_MASK 0x7F
309#define IGP02E1000_AGC_RANGE 15
310
311/* manage.c */
312#define E1000_VFTA_ENTRY_SHIFT 5
313#define E1000_VFTA_ENTRY_MASK 0x7F
314#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
315
316#define E1000_HICR_EN 0x01 /* Enable bit - RO */
317/* Driver sets this bit when done to put command in RAM */
318#define E1000_HICR_C 0x02
319#define E1000_HICR_FW_RESET_ENABLE 0x40
320#define E1000_HICR_FW_RESET 0x80
321
322#define E1000_FWSM_MODE_MASK 0xE
323#define E1000_FWSM_MODE_SHIFT 1
324
325#define E1000_MNG_IAMT_MODE 0x3
326#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
327#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
328#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
329#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
330#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
331#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
332
333/* nvm.c */
334#define E1000_STM_OPCODE 0xDB00
335
336#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
337#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
338#define E1000_KMRNCTRLSTA_REN 0x00200000
339#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
340#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
341#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
342#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
343#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
344#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
345#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
346#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
347#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
348
349#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
350#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
351#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
352#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
353
354/* IFE PHY Extended Status Control */
355#define IFE_PESC_POLARITY_REVERSED 0x0100
356
357/* IFE PHY Special Control */
358#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
359#define IFE_PSC_FORCE_POLARITY 0x0020
360
361/* IFE PHY Special Control and LED Control */
362#define IFE_PSCL_PROBE_MODE 0x0020
363#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
364#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
365
366/* IFE PHY MDIX Control */
367#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
368#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
369#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
370
371#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
372
373#define E1000_DEV_ID_82571EB_COPPER 0x105E 37#define E1000_DEV_ID_82571EB_COPPER 0x105E
374#define E1000_DEV_ID_82571EB_FIBER 0x105F 38#define E1000_DEV_ID_82571EB_FIBER 0x105F
375#define E1000_DEV_ID_82571EB_SERDES 0x1060 39#define E1000_DEV_ID_82571EB_SERDES 0x1060
@@ -776,6 +440,11 @@ struct e1000_host_mng_command_info {
776 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 440 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
777}; 441};
778 442
443#include "mac.h"
444#include "phy.h"
445#include "nvm.h"
446#include "manage.h"
447
779/* Function pointers for the MAC. */ 448/* Function pointers for the MAC. */
780struct e1000_mac_operations { 449struct e1000_mac_operations {
781 s32 (*id_led_init)(struct e1000_hw *); 450 s32 (*id_led_init)(struct e1000_hw *);
@@ -1005,4 +674,8 @@ struct e1000_hw {
1005 } dev_spec; 674 } dev_spec;
1006}; 675};
1007 676
677#include "82571.h"
678#include "80003es2lan.h"
679#include "ich8lan.h"
680
1008#endif 681#endif
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index a019b46f30e2..dff7bff8b8e0 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -57,132 +57,6 @@
57 57
58#include "e1000.h" 58#include "e1000.h"
59 59
60#define ICH_FLASH_GFPREG 0x0000
61#define ICH_FLASH_HSFSTS 0x0004
62#define ICH_FLASH_HSFCTL 0x0006
63#define ICH_FLASH_FADDR 0x0008
64#define ICH_FLASH_FDATA0 0x0010
65#define ICH_FLASH_PR0 0x0074
66
67#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72
73#define ICH_CYCLE_READ 0
74#define ICH_CYCLE_WRITE 2
75#define ICH_CYCLE_ERASE 3
76
77#define FLASH_GFPREG_BASE_MASK 0x1FFF
78#define FLASH_SECTOR_ADDR_SHIFT 12
79
80#define ICH_FLASH_SEG_SIZE_256 256
81#define ICH_FLASH_SEG_SIZE_4K 4096
82#define ICH_FLASH_SEG_SIZE_8K 8192
83#define ICH_FLASH_SEG_SIZE_64K 65536
84
85
86#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87/* FW established a valid mode */
88#define E1000_ICH_FWSM_FW_VALID 0x00008000
89
90#define E1000_ICH_MNG_IAMT_MODE 0x2
91
92#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
93 (ID_LED_DEF1_OFF2 << 8) | \
94 (ID_LED_DEF1_ON2 << 4) | \
95 (ID_LED_DEF1_DEF2))
96
97#define E1000_ICH_NVM_SIG_WORD 0x13
98#define E1000_ICH_NVM_SIG_MASK 0xC000
99#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
100#define E1000_ICH_NVM_SIG_VALUE 0x80
101
102#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
103
104#define E1000_FEXTNVM_SW_CONFIG 1
105#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
106
107#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
108#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
109
110#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
111#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
112#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
113
114#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
115
116#define E1000_ICH_RAR_ENTRIES 7
117#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
118#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
119
120#define PHY_PAGE_SHIFT 5
121#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
122 ((reg) & MAX_PHY_REG_ADDRESS))
123#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
124#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
125
126#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
127#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
128#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
129
130#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
131
132#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
133
134/* SMBus Control Phy Register */
135#define CV_SMB_CTRL PHY_REG(769, 23)
136#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
137
138/* SMBus Address Phy Register */
139#define HV_SMB_ADDR PHY_REG(768, 26)
140#define HV_SMB_ADDR_MASK 0x007F
141#define HV_SMB_ADDR_PEC_EN 0x0200
142#define HV_SMB_ADDR_VALID 0x0080
143#define HV_SMB_ADDR_FREQ_MASK 0x1100
144#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
145#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
146
147/* PHY Power Management Control */
148#define HV_PM_CTRL PHY_REG(770, 17)
149#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
150
151/* Intel Rapid Start Technology Support */
152#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
153#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
154#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
155#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
156#define I217_CGFREG PHY_REG(772, 29)
157#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
158#define I217_MEMPWR PHY_REG(772, 26)
159#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
160
161/* Strapping Option Register - RO */
162#define E1000_STRAP 0x0000C
163#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
164#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
165#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
166#define E1000_STRAP_SMT_FREQ_SHIFT 12
167
168/* OEM Bits Phy Register */
169#define HV_OEM_BITS PHY_REG(768, 25)
170#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
171#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
172#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
173
174#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
175#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
176
177/* KMRN Mode Control */
178#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
179#define HV_KMRN_MDIO_SLOW 0x0400
180
181/* KMRN FIFO Control and Status */
182#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
183#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
184#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
185
186/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 60/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
187/* Offset 04h HSFSTS */ 61/* Offset 04h HSFSTS */
188union ich8_hws_flash_status { 62union ich8_hws_flash_status {
@@ -4117,7 +3991,6 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4117 * The SMBus release must also be disabled on LCD reset. 3991 * The SMBus release must also be disabled on LCD reset.
4118 */ 3992 */
4119 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 3993 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4120
4121 /* Enable proxy to reset only on power good. */ 3994 /* Enable proxy to reset only on power good. */
4122 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 3995 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4123 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 3996 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
new file mode 100644
index 000000000000..b6d3174d7d2d
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -0,0 +1,268 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_ICH8LAN_H_
30#define _E1000E_ICH8LAN_H_
31
32#define ICH_FLASH_GFPREG 0x0000
33#define ICH_FLASH_HSFSTS 0x0004
34#define ICH_FLASH_HSFCTL 0x0006
35#define ICH_FLASH_FADDR 0x0008
36#define ICH_FLASH_FDATA0 0x0010
37#define ICH_FLASH_PR0 0x0074
38
39/* Requires up to 10 seconds when MNG might be accessing part. */
40#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
41#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
42#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
43#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
44#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
45
46#define ICH_CYCLE_READ 0
47#define ICH_CYCLE_WRITE 2
48#define ICH_CYCLE_ERASE 3
49
50#define FLASH_GFPREG_BASE_MASK 0x1FFF
51#define FLASH_SECTOR_ADDR_SHIFT 12
52
53#define ICH_FLASH_SEG_SIZE_256 256
54#define ICH_FLASH_SEG_SIZE_4K 4096
55#define ICH_FLASH_SEG_SIZE_8K 8192
56#define ICH_FLASH_SEG_SIZE_64K 65536
57
58#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
59/* FW established a valid mode */
60#define E1000_ICH_FWSM_FW_VALID 0x00008000
61#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
62#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
63
64#define E1000_ICH_MNG_IAMT_MODE 0x2
65
66#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
67#define E1000_FWSM_WLOCK_MAC_SHIFT 7
68
69/* Shared Receive Address Registers */
70#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
71#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
72
73#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
74 (ID_LED_OFF1_OFF2 << 8) | \
75 (ID_LED_OFF1_ON2 << 4) | \
76 (ID_LED_DEF1_DEF2))
77
78#define E1000_ICH_NVM_SIG_WORD 0x13
79#define E1000_ICH_NVM_SIG_MASK 0xC000
80#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
81#define E1000_ICH_NVM_SIG_VALUE 0x80
82
83#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
84
85#define E1000_FEXTNVM_SW_CONFIG 1
86#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
87
88#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
89#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
90
91#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
92#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
93#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
94
95#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
96
97#define E1000_ICH_RAR_ENTRIES 7
98#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
99#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
100
101#define PHY_PAGE_SHIFT 5
102#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
103 ((reg) & MAX_PHY_REG_ADDRESS))
104#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
105#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
106
107#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
108#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
109#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
110
111/* PHY Wakeup Registers and defines */
112#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
113#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
114#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
115#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
116#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
117#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
118#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
119#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
120#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
121#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
122
123#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
124#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
125#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
126#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
127#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
128#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
129#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
130
131#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
132#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
133#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
134#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
135#define HV_STATS_PAGE 778
136/* Half-duplex collision counts */
137#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
138#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
139#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
140#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
141#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
142#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
143#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
144#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
145#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
146#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
147#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
148#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
149#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
150#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
151
152#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
153
154#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
155#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
156
157/* SMBus Control Phy Register */
158#define CV_SMB_CTRL PHY_REG(769, 23)
159#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
160
161/* SMBus Address Phy Register */
162#define HV_SMB_ADDR PHY_REG(768, 26)
163#define HV_SMB_ADDR_MASK 0x007F
164#define HV_SMB_ADDR_PEC_EN 0x0200
165#define HV_SMB_ADDR_VALID 0x0080
166#define HV_SMB_ADDR_FREQ_MASK 0x1100
167#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
168#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
169
170/* Strapping Option Register - RO */
171#define E1000_STRAP 0x0000C
172#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
173#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
174#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
175#define E1000_STRAP_SMT_FREQ_SHIFT 12
176
177/* OEM Bits Phy Register */
178#define HV_OEM_BITS PHY_REG(768, 25)
179#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
180#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
181#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
182
183/* KMRN Mode Control */
184#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
185#define HV_KMRN_MDIO_SLOW 0x0400
186
187/* KMRN FIFO Control and Status */
188#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
189#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
190#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
191
192/* PHY Power Management Control */
193#define HV_PM_CTRL PHY_REG(770, 17)
194#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
195
196#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
197
198/* PHY Low Power Idle Control */
199#define I82579_LPI_CTRL PHY_REG(772, 20)
200#define I82579_LPI_CTRL_100_ENABLE 0x2000
201#define I82579_LPI_CTRL_1000_ENABLE 0x4000
202#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
203#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
204
205/* Extended Management Interface (EMI) Registers */
206#define I82579_EMI_ADDR 0x10
207#define I82579_EMI_DATA 0x11
208#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
209#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
210#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
211#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
212#define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */
213#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
214#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
215#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
216#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
217#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
218#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
219#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
220#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
221#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
222
223#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
224#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
225
226/* Intel Rapid Start Technology Support */
227#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
228#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
229#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
230#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
231#define I217_CGFREG PHY_REG(772, 29)
232#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
233#define I217_MEMPWR PHY_REG(772, 26)
234#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
235
236/* Receive Address Initial CRC Calculation */
237#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
238
239/* Latency Tolerance Reporting */
240#define E1000_LTRV 0x000F8
241#define E1000_LTRV_SCALE_MAX 5
242#define E1000_LTRV_SCALE_FACTOR 5
243#define E1000_LTRV_REQ_SHIFT 15
244#define E1000_LTRV_NOSNOOP_SHIFT 16
245#define E1000_LTRV_SEND (1 << 30)
246
247/* Proprietary Latency Tolerance Reporting PCI Capability */
248#define E1000_PCI_LTR_CAP_LPT 0xA8
249
250/* OBFF Control & Threshold Defines */
251#define E1000_SVCR_OFF_EN 0x00000001
252#define E1000_SVCR_OFF_MASKINT 0x00001000
253#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000
254#define E1000_SVCR_OFF_TIMER_SHIFT 16
255#define E1000_SVT_OFF_HWM_MASK 0x0000001F
256
257void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
258void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
259 bool state);
260void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
261void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
262void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
263void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
264s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
265void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
266s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
267s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
268#endif /* _E1000E_ICH8LAN_H_ */
diff --git a/drivers/net/ethernet/intel/e1000e/mac.h b/drivers/net/ethernet/intel/e1000e/mac.h
new file mode 100644
index 000000000000..a61fee404ebe
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/mac.h
@@ -0,0 +1,74 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_MAC_H_
30#define _E1000E_MAC_H_
31
32s32 e1000e_blink_led_generic(struct e1000_hw *hw);
33s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
34s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
35s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
36s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
37s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
38s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
39s32 e1000e_force_mac_fc(struct e1000_hw *hw);
40s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
41s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
42void e1000_set_lan_id_single_port(struct e1000_hw *hw);
43s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
44s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
45 u16 *duplex);
46s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
47 u16 *speed, u16 *duplex);
48s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
49s32 e1000e_led_on_generic(struct e1000_hw *hw);
50s32 e1000e_led_off_generic(struct e1000_hw *hw);
51void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
52 u8 *mc_addr_list, u32 mc_addr_count);
53s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
54s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
55s32 e1000e_setup_led_generic(struct e1000_hw *hw);
56s32 e1000e_setup_link_generic(struct e1000_hw *hw);
57s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw);
58s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);
59
60void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
61void e1000_clear_vfta_generic(struct e1000_hw *hw);
62void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
63void e1000e_put_hw_semaphore(struct e1000_hw *hw);
64s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
65void e1000e_reset_adaptive(struct e1000_hw *hw);
66void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
67void e1000e_update_adaptive(struct e1000_hw *hw);
68void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
69
70void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
71void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
72void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
73
74#endif
diff --git a/drivers/net/ethernet/intel/e1000e/manage.c b/drivers/net/ethernet/intel/e1000e/manage.c
index 4dae0dbda837..e4b0f1ef92f6 100644
--- a/drivers/net/ethernet/intel/e1000e/manage.c
+++ b/drivers/net/ethernet/intel/e1000e/manage.c
@@ -28,19 +28,6 @@
28 28
29#include "e1000.h" 29#include "e1000.h"
30 30
31enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37};
38
39#define E1000_FACTPS_MNGCG 0x20000000
40
41/* Intel(R) Active Management Technology signature */
42#define E1000_IAMT_SIGNATURE 0x544D4149
43
44/** 31/**
45 * e1000_calculate_checksum - Calculate checksum for buffer 32 * e1000_calculate_checksum - Calculate checksum for buffer
46 * @buffer: pointer to EEPROM 33 * @buffer: pointer to EEPROM
diff --git a/drivers/net/ethernet/intel/e1000e/manage.h b/drivers/net/ethernet/intel/e1000e/manage.h
new file mode 100644
index 000000000000..326897c29ea8
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/manage.h
@@ -0,0 +1,72 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_MANAGE_H_
30#define _E1000E_MANAGE_H_
31
32bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
33bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
34s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
35bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
36
37enum e1000_mng_mode {
38 e1000_mng_mode_none = 0,
39 e1000_mng_mode_asf,
40 e1000_mng_mode_pt,
41 e1000_mng_mode_ipmi,
42 e1000_mng_mode_host_if_only
43};
44
45#define E1000_FACTPS_MNGCG 0x20000000
46
47#define E1000_FWSM_MODE_MASK 0xE
48#define E1000_FWSM_MODE_SHIFT 1
49
50#define E1000_MNG_IAMT_MODE 0x3
51#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
52#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
53#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
54#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
55#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
56#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
57
58#define E1000_VFTA_ENTRY_SHIFT 5
59#define E1000_VFTA_ENTRY_MASK 0x7F
60#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
61
62#define E1000_HICR_EN 0x01 /* Enable bit - RO */
63/* Driver sets this bit when done to put command in RAM */
64#define E1000_HICR_C 0x02
65#define E1000_HICR_SV 0x04 /* Status Validity */
66#define E1000_HICR_FW_RESET_ENABLE 0x40
67#define E1000_HICR_FW_RESET 0x80
68
69/* Intel(R) Active Management Technology signature */
70#define E1000_IAMT_SIGNATURE 0x544D4149
71
72#endif
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index e0eb5dddf3ea..3f7dbd1cdb0f 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -86,20 +86,7 @@ struct e1000_reg_info {
86 char *name; 86 char *name;
87}; 87};
88 88
89#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
90#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
91#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
92#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
93#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
94
95#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
96#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
97#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
98#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
99#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
100
101static const struct e1000_reg_info e1000_reg_info_tbl[] = { 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
102
103 /* General Registers */ 90 /* General Registers */
104 {E1000_CTRL, "CTRL"}, 91 {E1000_CTRL, "CTRL"},
105 {E1000_STATUS, "STATUS"}, 92 {E1000_STATUS, "STATUS"},
@@ -2024,7 +2011,6 @@ static void e1000_configure_msix(struct e1000_adapter *adapter)
2024 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; 2011 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2025 2012
2026 /* Auto-Mask Other interrupts upon ICR read */ 2013 /* Auto-Mask Other interrupts upon ICR read */
2027#define E1000_EIAC_MASK_82574 0x01F00000
2028 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); 2014 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2029 ctrl_ext |= E1000_CTRL_EXT_EIAME; 2015 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2030 ew32(CTRL_EXT, ctrl_ext); 2016 ew32(CTRL_EXT, ctrl_ext);
@@ -6407,7 +6393,6 @@ static void e1000_io_resume(struct pci_dev *pdev)
6407 */ 6393 */
6408 if (!(adapter->flags & FLAG_HAS_AMT)) 6394 if (!(adapter->flags & FLAG_HAS_AMT))
6409 e1000e_get_hw_control(adapter); 6395 e1000e_get_hw_control(adapter);
6410
6411} 6396}
6412 6397
6413static void e1000_print_device_info(struct e1000_adapter *adapter) 6398static void e1000_print_device_info(struct e1000_adapter *adapter)
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.h b/drivers/net/ethernet/intel/e1000e/nvm.h
new file mode 100644
index 000000000000..45fc69561627
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/nvm.h
@@ -0,0 +1,47 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_NVM_H_
30#define _E1000E_NVM_H_
31
32s32 e1000e_acquire_nvm(struct e1000_hw *hw);
33
34s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
35s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
36s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
37 u32 pba_num_size);
38s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
39s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
40s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
41s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
42s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
43void e1000e_release_nvm(struct e1000_hw *hw);
44
45#define E1000_STM_OPCODE 0xDB00
46
47#endif
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index ae656f16c9fd..0930c136aa31 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -53,48 +53,6 @@ static const u16 e1000_igp_2_cable_length_table[] = {
53#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 53#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
54 ARRAY_SIZE(e1000_igp_2_cable_length_table) 54 ARRAY_SIZE(e1000_igp_2_cable_length_table)
55 55
56#define BM_PHY_REG_PAGE(offset) \
57 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
58#define BM_PHY_REG_NUM(offset) \
59 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
60 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
61 ~MAX_PHY_REG_ADDRESS)))
62
63#define HV_INTC_FC_PAGE_START 768
64#define I82578_ADDR_REG 29
65#define I82577_ADDR_REG 16
66#define I82577_CFG_REG 22
67#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
68#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
69#define I82577_CTRL_REG 23
70
71/* 82577 specific PHY registers */
72#define I82577_PHY_CTRL_2 18
73#define I82577_PHY_STATUS_2 26
74#define I82577_PHY_DIAG_STATUS 31
75
76/* I82577 PHY Status 2 */
77#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
78#define I82577_PHY_STATUS2_MDIX 0x0800
79#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
80#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
81
82/* I82577 PHY Control 2 */
83#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
84#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
85#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
86
87/* I82577 PHY Diagnostics Status */
88#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
89#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
90
91/* BM PHY Copper Specific Control 1 */
92#define BM_CS_CTRL1 16
93
94#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
95#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
96#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
97
98/** 56/**
99 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 57 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
100 * @hw: pointer to the HW structure 58 * @hw: pointer to the HW structure
@@ -2516,7 +2474,6 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2516 hw->phy.addr = 1; 2474 hw->phy.addr = 1;
2517 2475
2518 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2476 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2519
2520 /* Page is shifted left, PHY expects (page x 32) */ 2477 /* Page is shifted left, PHY expects (page x 32) */
2521 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2478 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2522 page); 2479 page);
diff --git a/drivers/net/ethernet/intel/e1000e/phy.h b/drivers/net/ethernet/intel/e1000e/phy.h
new file mode 100644
index 000000000000..f4f71b9991e3
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/phy.h
@@ -0,0 +1,242 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_PHY_H_
30#define _E1000E_PHY_H_
31
32s32 e1000e_check_downshift(struct e1000_hw *hw);
33s32 e1000_check_polarity_m88(struct e1000_hw *hw);
34s32 e1000_check_polarity_igp(struct e1000_hw *hw);
35s32 e1000_check_polarity_ife(struct e1000_hw *hw);
36s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
37s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
38s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
39s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
40s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
41s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
42s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
43s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
44s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
45s32 e1000e_get_phy_id(struct e1000_hw *hw);
46s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
47s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
48s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
49s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
50void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
51s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
52s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
53s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
54s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
55s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
56s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
57s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
58s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
59s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
60s32 e1000e_setup_copper_link(struct e1000_hw *hw);
61s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
62s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
63s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
64s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
65s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
66s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
67 u32 usec_interval, bool *success);
68s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
69enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
70s32 e1000e_determine_phy_address(struct e1000_hw *hw);
71s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
72s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
73s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
74s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
75s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
76s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
77void e1000_power_up_phy_copper(struct e1000_hw *hw);
78void e1000_power_down_phy_copper(struct e1000_hw *hw);
79s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
80s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
81s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
82s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
83s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
84s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
85s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
86s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
87s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
88s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
89s32 e1000_check_polarity_82577(struct e1000_hw *hw);
90s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
91s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
92s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
93
94#define E1000_MAX_PHY_ADDR 8
95
96/* IGP01E1000 Specific Registers */
97#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
98#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
99#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
100#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
101#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
102#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
103#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
104#define IGP_PAGE_SHIFT 5
105#define PHY_REG_MASK 0x1F
106
107/* BM/HV Specific Registers */
108#define BM_PORT_CTRL_PAGE 769
109#define BM_WUC_PAGE 800
110#define BM_WUC_ADDRESS_OPCODE 0x11
111#define BM_WUC_DATA_OPCODE 0x12
112#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
113#define BM_WUC_ENABLE_REG 17
114#define BM_WUC_ENABLE_BIT (1 << 2)
115#define BM_WUC_HOST_WU_BIT (1 << 4)
116#define BM_WUC_ME_WU_BIT (1 << 5)
117
118#define PHY_UPPER_SHIFT 21
119#define BM_PHY_REG(page, reg) \
120 (((reg) & MAX_PHY_REG_ADDRESS) |\
121 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
122 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
123#define BM_PHY_REG_PAGE(offset) \
124 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
125#define BM_PHY_REG_NUM(offset) \
126 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
127 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
128 ~MAX_PHY_REG_ADDRESS)))
129
130#define HV_INTC_FC_PAGE_START 768
131#define I82578_ADDR_REG 29
132#define I82577_ADDR_REG 16
133#define I82577_CFG_REG 22
134#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
135#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
136#define I82577_CTRL_REG 23
137
138/* 82577 specific PHY registers */
139#define I82577_PHY_CTRL_2 18
140#define I82577_PHY_LBK_CTRL 19
141#define I82577_PHY_STATUS_2 26
142#define I82577_PHY_DIAG_STATUS 31
143
144/* I82577 PHY Status 2 */
145#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
146#define I82577_PHY_STATUS2_MDIX 0x0800
147#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
148#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
149
150/* I82577 PHY Control 2 */
151#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
152#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
153#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
154
155/* I82577 PHY Diagnostics Status */
156#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
157#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
158
159/* BM PHY Copper Specific Control 1 */
160#define BM_CS_CTRL1 16
161
162/* BM PHY Copper Specific Status */
163#define BM_CS_STATUS 17
164#define BM_CS_STATUS_LINK_UP 0x0400
165#define BM_CS_STATUS_RESOLVED 0x0800
166#define BM_CS_STATUS_SPEED_MASK 0xC000
167#define BM_CS_STATUS_SPEED_1000 0x8000
168
169/* 82577 Mobile Phy Status Register */
170#define HV_M_STATUS 26
171#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
172#define HV_M_STATUS_SPEED_MASK 0x0300
173#define HV_M_STATUS_SPEED_1000 0x0200
174#define HV_M_STATUS_LINK_UP 0x0040
175
176#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
177#define IGP01E1000_PHY_POLARITY_MASK 0x0078
178
179#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
180#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
181
182#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
183
184#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
185#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
186#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
187
188#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
189
190#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
191#define IGP01E1000_PSSR_MDIX 0x0800
192#define IGP01E1000_PSSR_SPEED_MASK 0xC000
193#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
194
195#define IGP02E1000_PHY_CHANNEL_NUM 4
196#define IGP02E1000_PHY_AGC_A 0x11B1
197#define IGP02E1000_PHY_AGC_B 0x12B1
198#define IGP02E1000_PHY_AGC_C 0x14B1
199#define IGP02E1000_PHY_AGC_D 0x18B1
200
201#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
202#define IGP02E1000_AGC_LENGTH_MASK 0x7F
203#define IGP02E1000_AGC_RANGE 15
204
205#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
206
207#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
208#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
209#define E1000_KMRNCTRLSTA_REN 0x00200000
210#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
211#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
212#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
213#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
214#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
215#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
216#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
217#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
218#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
219
220#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
221#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
222#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
223#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
224
225/* IFE PHY Extended Status Control */
226#define IFE_PESC_POLARITY_REVERSED 0x0100
227
228/* IFE PHY Special Control */
229#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
230#define IFE_PSC_FORCE_POLARITY 0x0020
231
232/* IFE PHY Special Control and LED Control */
233#define IFE_PSCL_PROBE_MODE 0x0020
234#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
235#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
236
237/* IFE PHY MDIX Control */
238#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
239#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
240#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
241
242#endif
diff --git a/drivers/net/ethernet/intel/e1000e/regs.h b/drivers/net/ethernet/intel/e1000e/regs.h
new file mode 100644
index 000000000000..794fe1497666
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/regs.h
@@ -0,0 +1,252 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_REGS_H_
30#define _E1000E_REGS_H_
31
32#define E1000_CTRL 0x00000 /* Device Control - RW */
33#define E1000_STATUS 0x00008 /* Device Status - RO */
34#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
35#define E1000_EERD 0x00014 /* EEPROM Read - RW */
36#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
37#define E1000_FLA 0x0001C /* Flash Access - RW */
38#define E1000_MDIC 0x00020 /* MDI Control - RW */
39#define E1000_SCTL 0x00024 /* SerDes Control - RW */
40#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
41#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
42#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
43#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
44#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
45#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
46#define E1000_FCT 0x00030 /* Flow Control Type - RW */
47#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
48#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
49#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
50#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
51#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
52#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
53#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
54#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
55#define E1000_SVCR 0x000F0
56#define E1000_SVT 0x000F4
57#define E1000_LPIC 0x000FC /* Low Power IDLE control */
58#define E1000_RCTL 0x00100 /* Rx Control - RW */
59#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
60#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
61#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
62#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
63#define E1000_TCTL 0x00400 /* Tx Control - RW */
64#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
65#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
66#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
67#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
68#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
69#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
70#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
71#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
72#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
73#define E1000_PBS 0x01008 /* Packet Buffer Size */
74#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
75#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
76#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
77#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
78#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
79#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
80#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
81#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
82#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
83#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
84#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
85#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
86#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
87/* Split and Replication Rx Control - RW */
88#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
89#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
90/* Convenience macros
91 *
92 * Note: "_n" is the queue number of the register to be written to.
93 *
94 * Example usage:
95 * E1000_RDBAL_REG(current_rx_queue)
96 */
97#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
98 (0x0C000 + ((_n) * 0x40)))
99#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
100 (0x0C004 + ((_n) * 0x40)))
101#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
102 (0x0C008 + ((_n) * 0x40)))
103#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
104 (0x0C010 + ((_n) * 0x40)))
105#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
106 (0x0C018 + ((_n) * 0x40)))
107#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
108 (0x0C028 + ((_n) * 0x40)))
109#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
110 (0x0E000 + ((_n) * 0x40)))
111#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
112 (0x0E004 + ((_n) * 0x40)))
113#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
114 (0x0E008 + ((_n) * 0x40)))
115#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
116 (0x0E010 + ((_n) * 0x40)))
117#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
118 (0x0E018 + ((_n) * 0x40)))
119#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
120 (0x0E028 + ((_n) * 0x40)))
121#define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
122#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
123#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
124 (0x054E0 + ((_i - 16) * 8)))
125#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
126 (0x054E4 + ((_i - 16) * 8)))
127#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
128#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
129#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
130#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
131#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
132#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
133#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
134#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
135#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
136#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
137#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
138#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
139#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
140#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
141#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
142#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
143#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
144#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
145#define E1000_COLC 0x04028 /* Collision Count - R/clr */
146#define E1000_DC 0x04030 /* Defer Count - R/clr */
147#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
148#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
149#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
150#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
151#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
152#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
153#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
154#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
155#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
156#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
157#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
158#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
159#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
160#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
161#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
162#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
163#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
164#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
165#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
166#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
167#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
168#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
169#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
170#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
171#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
172#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
173#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
174#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
175#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
176#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
177#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
178#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
179#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
180#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
181#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
182#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
183#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
184#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
185#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
186#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
187#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
188#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
189#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
190#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
191#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
192#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
193#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
194#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
195#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
196#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
197#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
198#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
199#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
200#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
201#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
202#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
203#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
204
205#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
206#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
207#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
208#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
209#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
210#define E1000_RFCTL 0x05008 /* Receive Filter Control */
211#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
212#define E1000_RA 0x05400 /* Receive Address - RW Array */
213#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
214#define E1000_WUC 0x05800 /* Wakeup Control - RW */
215#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
216#define E1000_WUS 0x05810 /* Wakeup Status - RO */
217#define E1000_MANC 0x05820 /* Management Control - RW */
218#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
219#define E1000_HOST_IF 0x08800 /* Host Interface */
220
221#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
222#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
223/* Management Decision Filters */
224#define E1000_MDEF(_n) (0x05890 + (4 * (_n)))
225#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
226#define E1000_GCR 0x05B00 /* PCI-Ex Control */
227#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
228#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
229#define E1000_SWSM 0x05B50 /* SW Semaphore */
230#define E1000_FWSM 0x05B54 /* FW Semaphore */
231/* Driver-only SW semaphore (not used by BOOT agents) */
232#define E1000_SWSM2 0x05B58
233#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
234#define E1000_HICR 0x08F00 /* Host Interface Control */
235
236/* RSS registers */
237#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
238#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
239#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
240#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
241#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
242#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
243#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
244#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
245#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
246#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
247#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
248#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
249#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
250#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
251
252#endif
diff --git a/drivers/net/ethernet/intel/ixgbe/Makefile b/drivers/net/ethernet/intel/ixgbe/Makefile
index 687c83d1bdab..be2989e60009 100644
--- a/drivers/net/ethernet/intel/ixgbe/Makefile
+++ b/drivers/net/ethernet/intel/ixgbe/Makefile
@@ -1,7 +1,7 @@
1################################################################################ 1################################################################################
2# 2#
3# Intel 10 Gigabit PCI Express Linux driver 3# Intel 10 Gigabit PCI Express Linux driver
4# Copyright(c) 1999 - 2012 Intel Corporation. 4# Copyright(c) 1999 - 2013 Intel Corporation.
5# 5#
6# This program is free software; you can redistribute it and/or modify it 6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License, 7# under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index 8371ae4265fe..d268c7b222c7 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -92,8 +92,6 @@
92 */ 92 */
93#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 93#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
94 94
95#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
96
97/* How many Rx Buffers do we bundle into one write to the hardware ? */ 95/* How many Rx Buffers do we bundle into one write to the hardware ? */
98#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 96#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
99 97
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
index 7fd3833c7ecf..d0113fc97b6f 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -1003,15 +1003,16 @@ static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1003} 1003}
1004 1004
1005/** 1005/**
1006 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1006 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1007 * @hw: pointer to hardware structure 1007 * @hw: pointer to hardware structure
1008 * @byte_offset: EEPROM byte offset to read 1008 * @dev_addr: address to read from
1009 * @byte_offset: byte offset to read from dev_addr
1009 * @eeprom_data: value read 1010 * @eeprom_data: value read
1010 * 1011 *
1011 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1012 * Performs 8 byte read operation to SFP module's data over I2C interface.
1012 **/ 1013 **/
1013static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1014static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
1014 u8 *eeprom_data) 1015 u8 byte_offset, u8 *eeprom_data)
1015{ 1016{
1016 s32 status = 0; 1017 s32 status = 0;
1017 u16 sfp_addr = 0; 1018 u16 sfp_addr = 0;
@@ -1025,7 +1026,7 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1025 * 0xC30D. These registers are used to talk to the SFP+ 1026 * 0xC30D. These registers are used to talk to the SFP+
1026 * module's EEPROM through the SDA/SCL (I2C) interface. 1027 * module's EEPROM through the SDA/SCL (I2C) interface.
1027 */ 1028 */
1028 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1029 sfp_addr = (dev_addr << 8) + byte_offset;
1029 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1030 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1030 hw->phy.ops.write_reg(hw, 1031 hw->phy.ops.write_reg(hw,
1031 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1032 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
@@ -1057,7 +1058,6 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1057 *eeprom_data = (u8)(sfp_data >> 8); 1058 *eeprom_data = (u8)(sfp_data >> 8);
1058 } else { 1059 } else {
1059 status = IXGBE_ERR_PHY; 1060 status = IXGBE_ERR_PHY;
1060 goto out;
1061 } 1061 }
1062 1062
1063out: 1063out:
@@ -1065,6 +1065,36 @@ out:
1065} 1065}
1066 1066
1067/** 1067/**
1068 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1069 * @hw: pointer to hardware structure
1070 * @byte_offset: EEPROM byte offset to read
1071 * @eeprom_data: value read
1072 *
1073 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1074 **/
1075static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1076 u8 *eeprom_data)
1077{
1078 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1079 byte_offset, eeprom_data);
1080}
1081
1082/**
1083 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1084 * @hw: pointer to hardware structure
1085 * @byte_offset: byte offset at address 0xA2
1086 * @eeprom_data: value read
1087 *
1088 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1089 **/
1090static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1091 u8 *sff8472_data)
1092{
1093 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1094 byte_offset, sff8472_data);
1095}
1096
1097/**
1068 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1098 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1069 * @hw: pointer to hardware structure 1099 * @hw: pointer to hardware structure
1070 * 1100 *
@@ -1297,6 +1327,7 @@ static struct ixgbe_phy_operations phy_ops_82598 = {
1297 .write_reg = &ixgbe_write_phy_reg_generic, 1327 .write_reg = &ixgbe_write_phy_reg_generic,
1298 .setup_link = &ixgbe_setup_phy_link_generic, 1328 .setup_link = &ixgbe_setup_phy_link_generic,
1299 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1329 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1330 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
1300 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1331 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1301 .check_overtemp = &ixgbe_tn_check_overtemp, 1332 .check_overtemp = &ixgbe_tn_check_overtemp,
1302}; 1333};
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
index 335046175950..203a00c24330 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -2241,6 +2241,7 @@ static struct ixgbe_phy_operations phy_ops_82599 = {
2241 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2241 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2242 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2242 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2243 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2243 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2244 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2244 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2245 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2245 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2246 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2246 .check_overtemp = &ixgbe_tn_check_overtemp, 2247 .check_overtemp = &ixgbe_tn_check_overtemp,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 5e68afdd502a..99e472ebaa75 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
index f7a0970a251c..bc3948ead6e0 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
index 9bc17c0cb972..1f2c805684dd 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h
index 1f4108ee154b..1634de8b627f 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
index 87592b458c9c..ac780770863d 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h
index ba835708fcac..3164f5453b8f 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
index 4eac80d01857..05e23b80b5e3 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.h
index 4dec47faeb00..a4ef07631d1e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
index c261333438bf..f3d68f9696ba 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -449,7 +449,6 @@ static u8 ixgbe_dcbnl_getcap(struct net_device *netdev, int capid, u8 *cap)
449static int ixgbe_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num) 449static int ixgbe_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num)
450{ 450{
451 struct ixgbe_adapter *adapter = netdev_priv(netdev); 451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
452 u8 rval = 0;
453 452
454 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 453 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
455 switch (tcid) { 454 switch (tcid) {
@@ -460,14 +459,14 @@ static int ixgbe_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num)
460 *num = adapter->dcb_cfg.num_tcs.pfc_tcs; 459 *num = adapter->dcb_cfg.num_tcs.pfc_tcs;
461 break; 460 break;
462 default: 461 default:
463 rval = -EINVAL; 462 return -EINVAL;
464 break; 463 break;
465 } 464 }
466 } else { 465 } else {
467 rval = -EINVAL; 466 return -EINVAL;
468 } 467 }
469 468
470 return rval; 469 return 0;
471} 470}
472 471
473static int ixgbe_dcbnl_setnumtcs(struct net_device *netdev, int tcid, u8 num) 472static int ixgbe_dcbnl_setnumtcs(struct net_device *netdev, int tcid, u8 num)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
index 3504686d3af5..c5933f6dceee 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
index 216203ece6ed..db6735931d66 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -1040,6 +1040,9 @@ static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1040 p = (char *) adapter + 1040 p = (char *) adapter +
1041 ixgbe_gstrings_stats[i].stat_offset; 1041 ixgbe_gstrings_stats[i].stat_offset;
1042 break; 1042 break;
1043 default:
1044 data[i] = 0;
1045 continue;
1043 } 1046 }
1044 1047
1045 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1048 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
@@ -1096,8 +1099,10 @@ static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1096 1099
1097 switch (stringset) { 1100 switch (stringset) {
1098 case ETH_SS_TEST: 1101 case ETH_SS_TEST:
1099 memcpy(data, *ixgbe_gstrings_test, 1102 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1100 IXGBE_TEST_LEN * ETH_GSTRING_LEN); 1103 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1104 data += ETH_GSTRING_LEN;
1105 }
1101 break; 1106 break;
1102 case ETH_SS_STATS: 1107 case ETH_SS_STATS:
1103 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1108 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
index 496836765df8..c116884d7d35 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h
index bf724da99375..3a02759b5e95 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
index 8c74f739011d..9ffa3309e54d 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index ac41361f932f..396e280c4373 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -66,7 +66,7 @@ static char ixgbe_default_device_descr[] =
66#define DRV_VERSION "3.11.33-k" 66#define DRV_VERSION "3.11.33-k"
67const char ixgbe_driver_version[] = DRV_VERSION; 67const char ixgbe_driver_version[] = DRV_VERSION;
68static const char ixgbe_copyright[] = 68static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2012 Intel Corporation."; 69 "Copyright (c) 1999-2013 Intel Corporation.";
70 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = { 71static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info, 72 [board_82598] = &ixgbe_82598_info,
@@ -838,7 +838,7 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
838 break; 838 break;
839 839
840 /* prevent any other reads prior to eop_desc */ 840 /* prevent any other reads prior to eop_desc */
841 rmb(); 841 read_barrier_depends();
842 842
843 /* if DD is not set pending work has not been completed */ 843 /* if DD is not set pending work has not been completed */
844 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 844 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
@@ -4869,7 +4869,7 @@ static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4869 */ 4869 */
4870 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 4870 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4871 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 4871 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4872 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) 4872 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4873 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 4873 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4874 4874
4875 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 4875 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
index 1f3e32b576a5..d4a64e665398 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h
index 42dd65e6ac97..e44ff47659b5 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
index f4b2c0d662dd..eb534a071fde 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -1204,6 +1204,22 @@ s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1204} 1204}
1205 1205
1206/** 1206/**
1207 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1208 * @hw: pointer to hardware structure
1209 * @byte_offset: byte offset at address 0xA2
1210 * @eeprom_data: value read
1211 *
1212 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1213 **/
1214s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1215 u8 *sff8472_data)
1216{
1217 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1218 IXGBE_I2C_EEPROM_DEV_ADDR2,
1219 sff8472_data);
1220}
1221
1222/**
1207 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1223 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1208 * @hw: pointer to hardware structure 1224 * @hw: pointer to hardware structure
1209 * @byte_offset: EEPROM byte offset to write 1225 * @byte_offset: EEPROM byte offset to write
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
index 51b0a91f62bc..886a3431cf5b 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -30,6 +30,7 @@
30 30
31#include "ixgbe_type.h" 31#include "ixgbe_type.h"
32#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 32#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
33#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
33 34
34/* EEPROM byte offsets */ 35/* EEPROM byte offsets */
35#define IXGBE_SFF_IDENTIFIER 0x0 36#define IXGBE_SFF_IDENTIFIER 0x0
@@ -41,6 +42,8 @@
41#define IXGBE_SFF_10GBE_COMP_CODES 0x3 42#define IXGBE_SFF_10GBE_COMP_CODES 0x3
42#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 43#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
43#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 44#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
45#define IXGBE_SFF_SFF_8472_SWAP 0x5C
46#define IXGBE_SFF_SFF_8472_COMP 0x5E
44 47
45/* Bitmasks */ 48/* Bitmasks */
46#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 49#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
@@ -51,6 +54,7 @@
51#define IXGBE_SFF_1GBASET_CAPABLE 0x8 54#define IXGBE_SFF_1GBASET_CAPABLE 0x8
52#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 55#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
53#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 56#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
57#define IXGBE_SFF_ADDRESSING_MODE 0x4
54#define IXGBE_I2C_EEPROM_READ_MASK 0x100 58#define IXGBE_I2C_EEPROM_READ_MASK 0x100
55#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 59#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
56#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 60#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
@@ -88,6 +92,9 @@
88#define IXGBE_TN_LASI_STATUS_REG 0x9005 92#define IXGBE_TN_LASI_STATUS_REG 0x9005
89#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 93#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
90 94
95/* SFP+ SFF-8472 Compliance code */
96#define IXGBE_SFF_SFF_8472_UNSUP 0x00
97
91s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 98s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
92s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 99s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
93s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 100s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
@@ -125,6 +132,8 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
125 u8 dev_addr, u8 data); 132 u8 dev_addr, u8 data);
126s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 133s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
127 u8 *eeprom_data); 134 u8 *eeprom_data);
135s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
136 u8 *sff8472_data);
128s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 137s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
129 u8 eeprom_data); 138 u8 eeprom_data);
130#endif /* _IXGBE_PHY_H_ */ 139#endif /* _IXGBE_PHY_H_ */
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
index 53d204759711..331987d6815c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index ee3507f0ea53..d44b4d21268c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.h
index 008f9cea68d1..4713f9fc7f46 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.c
index 16ddf14e8ba4..d118def16f35 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index 0bdcc88cbf50..6652e96c352d 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -2874,6 +2874,7 @@ struct ixgbe_phy_operations {
2874 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 2874 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2875 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 2875 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2876 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 2876 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2877 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
2877 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 2878 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2878 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 2879 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2879 s32 (*check_overtemp)(struct ixgbe_hw *); 2880 s32 (*check_overtemp)(struct ixgbe_hw *);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
index 2fa58437a42f..66c5e946284e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation. 4 Copyright(c) 1999 - 2013 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -878,6 +878,7 @@ static struct ixgbe_phy_operations phy_ops_X540 = {
878 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 878 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
879 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 879 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
880 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 880 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
881 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
881 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 882 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
882 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 883 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
883 .check_overtemp = &ixgbe_tn_check_overtemp, 884 .check_overtemp = &ixgbe_tn_check_overtemp,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 08:30:25 -0400