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authorLendacky, Thomas <Thomas.Lendacky@amd.com>2014-06-05 10:15:12 -0400
committerDavid S. Miller <davem@davemloft.net>2014-06-05 18:26:51 -0400
commit4d874b30b14674284d72f92485e991b984b0b5e1 (patch)
tree4e4ef44c633d27ad816f398ba7ae3e26d3d35dea
parentc5aa9e3b815645e3aad08444c91ca6b237eeea01 (diff)
amd-xgbe: Initial AMD 10GbE phylib driver
This patch provides the initial phylib driver in support of the AMD 10GbE device. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/phy/amd-xgbe-phy.c1357
1 files changed, 1357 insertions, 0 deletions
diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
new file mode 100644
index 000000000000..d4b1c81610dd
--- /dev/null
+++ b/drivers/net/phy/amd-xgbe-phy.c
@@ -0,0 +1,1357 @@
1/*
2 * AMD 10Gb Ethernet PHY driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 *
25 * License 2: Modified BSD
26 *
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53#include <linux/kernel.h>
54#include <linux/device.h>
55#include <linux/platform_device.h>
56#include <linux/string.h>
57#include <linux/errno.h>
58#include <linux/unistd.h>
59#include <linux/slab.h>
60#include <linux/interrupt.h>
61#include <linux/init.h>
62#include <linux/delay.h>
63#include <linux/netdevice.h>
64#include <linux/etherdevice.h>
65#include <linux/skbuff.h>
66#include <linux/mm.h>
67#include <linux/module.h>
68#include <linux/mii.h>
69#include <linux/ethtool.h>
70#include <linux/phy.h>
71#include <linux/mdio.h>
72#include <linux/io.h>
73#include <linux/of.h>
74#include <linux/of_platform.h>
75#include <linux/of_device.h>
76#include <linux/uaccess.h>
77#include <asm/irq.h>
78
79
80MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
81MODULE_LICENSE("Dual BSD/GPL");
82MODULE_VERSION("1.0.0-a");
83MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
84
85#define XGBE_PHY_ID 0x000162d0
86#define XGBE_PHY_MASK 0xfffffff0
87
88#define XGBE_AN_INT_CMPLT 0x01
89#define XGBE_AN_INC_LINK 0x02
90#define XGBE_AN_PG_RCV 0x04
91
92#define XNP_MCF_NULL_MESSAGE 0x001
93#define XNP_ACK_PROCESSED (1 << 12)
94#define XNP_MP_FORMATTED (1 << 13)
95#define XNP_NP_EXCHANGE (1 << 15)
96
97#ifndef MDIO_PMA_10GBR_PMD_CTRL
98#define MDIO_PMA_10GBR_PMD_CTRL 0x0096
99#endif
100#ifndef MDIO_PMA_10GBR_FEC_CTRL
101#define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
102#endif
103#ifndef MDIO_AN_XNP
104#define MDIO_AN_XNP 0x0016
105#endif
106
107#ifndef MDIO_AN_INTMASK
108#define MDIO_AN_INTMASK 0x8001
109#endif
110#ifndef MDIO_AN_INT
111#define MDIO_AN_INT 0x8002
112#endif
113
114#ifndef MDIO_CTRL1_SPEED1G
115#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
116#endif
117
118/* SerDes integration register offsets */
119#define SIR0_STATUS 0x0040
120#define SIR1_SPEED 0x0000
121
122/* SerDes integration register entry bit positions and sizes */
123#define SIR0_STATUS_RX_READY_INDEX 0
124#define SIR0_STATUS_RX_READY_WIDTH 1
125#define SIR0_STATUS_TX_READY_INDEX 8
126#define SIR0_STATUS_TX_READY_WIDTH 1
127#define SIR1_SPEED_DATARATE_INDEX 4
128#define SIR1_SPEED_DATARATE_WIDTH 2
129#define SIR1_SPEED_PI_SPD_SEL_INDEX 12
130#define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
131#define SIR1_SPEED_PLLSEL_INDEX 3
132#define SIR1_SPEED_PLLSEL_WIDTH 1
133#define SIR1_SPEED_RATECHANGE_INDEX 6
134#define SIR1_SPEED_RATECHANGE_WIDTH 1
135#define SIR1_SPEED_TXAMP_INDEX 8
136#define SIR1_SPEED_TXAMP_WIDTH 4
137#define SIR1_SPEED_WORDMODE_INDEX 0
138#define SIR1_SPEED_WORDMODE_WIDTH 3
139
140#define SPEED_10000_CDR 0x7
141#define SPEED_10000_PLL 0x1
142#define SPEED_10000_RATE 0x0
143#define SPEED_10000_TXAMP 0xa
144#define SPEED_10000_WORD 0x7
145
146#define SPEED_2500_CDR 0x2
147#define SPEED_2500_PLL 0x0
148#define SPEED_2500_RATE 0x2
149#define SPEED_2500_TXAMP 0xf
150#define SPEED_2500_WORD 0x1
151
152#define SPEED_1000_CDR 0x2
153#define SPEED_1000_PLL 0x0
154#define SPEED_1000_RATE 0x3
155#define SPEED_1000_TXAMP 0xf
156#define SPEED_1000_WORD 0x1
157
158
159/* SerDes RxTx register offsets */
160#define RXTX_REG20 0x0050
161#define RXTX_REG114 0x01c8
162
163/* SerDes RxTx register entry bit positions and sizes */
164#define RXTX_REG20_BLWC_ENA_INDEX 2
165#define RXTX_REG20_BLWC_ENA_WIDTH 1
166#define RXTX_REG114_PQ_REG_INDEX 9
167#define RXTX_REG114_PQ_REG_WIDTH 7
168
169#define RXTX_10000_BLWC 0
170#define RXTX_10000_PQ 0x1e
171
172#define RXTX_2500_BLWC 1
173#define RXTX_2500_PQ 0xa
174
175#define RXTX_1000_BLWC 1
176#define RXTX_1000_PQ 0xa
177
178/* Bit setting and getting macros
179 * The get macro will extract the current bit field value from within
180 * the variable
181 *
182 * The set macro will clear the current bit field value within the
183 * variable and then set the bit field of the variable to the
184 * specified value
185 */
186#define GET_BITS(_var, _index, _width) \
187 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
188
189#define SET_BITS(_var, _index, _width, _val) \
190do { \
191 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
192 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
193} while (0)
194
195/* Macros for reading or writing SerDes integration registers
196 * The ioread macros will get bit fields or full values using the
197 * register definitions formed using the input names
198 *
199 * The iowrite macros will set bit fields or full values using the
200 * register definitions formed using the input names
201 */
202#define XSIR0_IOREAD(_priv, _reg) \
203 ioread16((_priv)->sir0_regs + _reg)
204
205#define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
206 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
207 _reg##_##_field##_INDEX, \
208 _reg##_##_field##_WIDTH)
209
210#define XSIR0_IOWRITE(_priv, _reg, _val) \
211 iowrite16((_val), (_priv)->sir0_regs + _reg)
212
213#define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
214do { \
215 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
216 SET_BITS(reg_val, \
217 _reg##_##_field##_INDEX, \
218 _reg##_##_field##_WIDTH, (_val)); \
219 XSIR0_IOWRITE((_priv), _reg, reg_val); \
220} while (0)
221
222#define XSIR1_IOREAD(_priv, _reg) \
223 ioread16((_priv)->sir1_regs + _reg)
224
225#define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
226 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
227 _reg##_##_field##_INDEX, \
228 _reg##_##_field##_WIDTH)
229
230#define XSIR1_IOWRITE(_priv, _reg, _val) \
231 iowrite16((_val), (_priv)->sir1_regs + _reg)
232
233#define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
234do { \
235 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
236 SET_BITS(reg_val, \
237 _reg##_##_field##_INDEX, \
238 _reg##_##_field##_WIDTH, (_val)); \
239 XSIR1_IOWRITE((_priv), _reg, reg_val); \
240} while (0)
241
242
243/* Macros for reading or writing SerDes RxTx registers
244 * The ioread macros will get bit fields or full values using the
245 * register definitions formed using the input names
246 *
247 * The iowrite macros will set bit fields or full values using the
248 * register definitions formed using the input names
249 */
250#define XRXTX_IOREAD(_priv, _reg) \
251 ioread16((_priv)->rxtx_regs + _reg)
252
253#define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
254 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
255 _reg##_##_field##_INDEX, \
256 _reg##_##_field##_WIDTH)
257
258#define XRXTX_IOWRITE(_priv, _reg, _val) \
259 iowrite16((_val), (_priv)->rxtx_regs + _reg)
260
261#define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
262do { \
263 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
264 SET_BITS(reg_val, \
265 _reg##_##_field##_INDEX, \
266 _reg##_##_field##_WIDTH, (_val)); \
267 XRXTX_IOWRITE((_priv), _reg, reg_val); \
268} while (0)
269
270
271enum amd_xgbe_phy_an {
272 AMD_XGBE_AN_READY = 0,
273 AMD_XGBE_AN_START,
274 AMD_XGBE_AN_EVENT,
275 AMD_XGBE_AN_PAGE_RECEIVED,
276 AMD_XGBE_AN_INCOMPAT_LINK,
277 AMD_XGBE_AN_COMPLETE,
278 AMD_XGBE_AN_NO_LINK,
279 AMD_XGBE_AN_EXIT,
280 AMD_XGBE_AN_ERROR,
281};
282
283enum amd_xgbe_phy_rx {
284 AMD_XGBE_RX_READY = 0,
285 AMD_XGBE_RX_BPA,
286 AMD_XGBE_RX_XNP,
287 AMD_XGBE_RX_COMPLETE,
288};
289
290enum amd_xgbe_phy_mode {
291 AMD_XGBE_MODE_KR,
292 AMD_XGBE_MODE_KX,
293};
294
295struct amd_xgbe_phy_priv {
296 struct platform_device *pdev;
297 struct device *dev;
298
299 struct phy_device *phydev;
300
301 /* SerDes related mmio resources */
302 struct resource *rxtx_res;
303 struct resource *sir0_res;
304 struct resource *sir1_res;
305
306 /* SerDes related mmio registers */
307 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
308 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
309 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
310
311 /* Maintain link status for re-starting auto-negotiation */
312 unsigned int link;
313 enum amd_xgbe_phy_mode mode;
314
315 /* Auto-negotiation state machine support */
316 struct mutex an_mutex;
317 enum amd_xgbe_phy_an an_result;
318 enum amd_xgbe_phy_an an_state;
319 enum amd_xgbe_phy_rx kr_state;
320 enum amd_xgbe_phy_rx kx_state;
321 struct work_struct an_work;
322 struct workqueue_struct *an_workqueue;
323};
324
325static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
326{
327 int ret;
328
329 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
330 if (ret < 0)
331 return ret;
332
333 ret |= 0x02;
334 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
335
336 return 0;
337}
338
339static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
340{
341 int ret;
342
343 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
344 if (ret < 0)
345 return ret;
346
347 ret &= ~0x02;
348 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
349
350 return 0;
351}
352
353static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
354{
355 int ret;
356
357 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
358 if (ret < 0)
359 return ret;
360
361 ret |= MDIO_CTRL1_LPOWER;
362 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
363
364 usleep_range(75, 100);
365
366 ret &= ~MDIO_CTRL1_LPOWER;
367 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
368
369 return 0;
370}
371
372static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
373{
374 struct amd_xgbe_phy_priv *priv = phydev->priv;
375
376 /* Assert Rx and Tx ratechange */
377 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
378}
379
380static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
381{
382 struct amd_xgbe_phy_priv *priv = phydev->priv;
383
384 /* Release Rx and Tx ratechange */
385 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
386
387 /* Wait for Rx and Tx ready */
388 while (!XSIR0_IOREAD_BITS(priv, SIR0_STATUS, RX_READY) &&
389 !XSIR0_IOREAD_BITS(priv, SIR0_STATUS, TX_READY))
390 usleep_range(10, 20);
391}
392
393static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
394{
395 struct amd_xgbe_phy_priv *priv = phydev->priv;
396 int ret;
397
398 /* Enable KR training */
399 ret = amd_xgbe_an_enable_kr_training(phydev);
400 if (ret < 0)
401 return ret;
402
403 /* Set PCS to KR/10G speed */
404 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
405 if (ret < 0)
406 return ret;
407
408 ret &= ~MDIO_PCS_CTRL2_TYPE;
409 ret |= MDIO_PCS_CTRL2_10GBR;
410 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
411
412 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
413 if (ret < 0)
414 return ret;
415
416 ret &= ~MDIO_CTRL1_SPEEDSEL;
417 ret |= MDIO_CTRL1_SPEED10G;
418 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
419
420 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
421 if (ret < 0)
422 return ret;
423
424 /* Set SerDes to 10G speed */
425 amd_xgbe_phy_serdes_start_ratechange(phydev);
426
427 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
428 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
429 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
430 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
431 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
432
433 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
434 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
435
436 amd_xgbe_phy_serdes_complete_ratechange(phydev);
437
438 priv->mode = AMD_XGBE_MODE_KR;
439
440 return 0;
441}
442
443static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
444{
445 struct amd_xgbe_phy_priv *priv = phydev->priv;
446 int ret;
447
448 /* Disable KR training */
449 ret = amd_xgbe_an_disable_kr_training(phydev);
450 if (ret < 0)
451 return ret;
452
453 /* Set PCS to KX/1G speed */
454 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
455 if (ret < 0)
456 return ret;
457
458 ret &= ~MDIO_PCS_CTRL2_TYPE;
459 ret |= MDIO_PCS_CTRL2_10GBX;
460 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
461
462 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
463 if (ret < 0)
464 return ret;
465
466 ret &= ~MDIO_CTRL1_SPEEDSEL;
467 ret |= MDIO_CTRL1_SPEED1G;
468 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
469
470 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
471 if (ret < 0)
472 return ret;
473
474 /* Set SerDes to 2.5G speed */
475 amd_xgbe_phy_serdes_start_ratechange(phydev);
476
477 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
478 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
479 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
480 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
481 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
482
483 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
484 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
485
486 amd_xgbe_phy_serdes_complete_ratechange(phydev);
487
488 priv->mode = AMD_XGBE_MODE_KX;
489
490 return 0;
491}
492
493static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
494{
495 struct amd_xgbe_phy_priv *priv = phydev->priv;
496 int ret;
497
498 /* Disable KR training */
499 ret = amd_xgbe_an_disable_kr_training(phydev);
500 if (ret < 0)
501 return ret;
502
503 /* Set PCS to KX/1G speed */
504 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
505 if (ret < 0)
506 return ret;
507
508 ret &= ~MDIO_PCS_CTRL2_TYPE;
509 ret |= MDIO_PCS_CTRL2_10GBX;
510 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
511
512 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
513 if (ret < 0)
514 return ret;
515
516 ret &= ~MDIO_CTRL1_SPEEDSEL;
517 ret |= MDIO_CTRL1_SPEED1G;
518 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
519
520 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
521 if (ret < 0)
522 return ret;
523
524 /* Set SerDes to 1G speed */
525 amd_xgbe_phy_serdes_start_ratechange(phydev);
526
527 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
528 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
529 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
530 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
531 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
532
533 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
534 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
535
536 amd_xgbe_phy_serdes_complete_ratechange(phydev);
537
538 priv->mode = AMD_XGBE_MODE_KX;
539
540 return 0;
541}
542
543static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
544{
545 struct amd_xgbe_phy_priv *priv = phydev->priv;
546 int ret;
547
548 /* If we are in KR switch to KX, and vice-versa */
549 if (priv->mode == AMD_XGBE_MODE_KR)
550 ret = amd_xgbe_phy_gmii_mode(phydev);
551 else
552 ret = amd_xgbe_phy_xgmii_mode(phydev);
553
554 return ret;
555}
556
557static enum amd_xgbe_phy_an amd_xgbe_an_switch_mode(struct phy_device *phydev)
558{
559 int ret;
560
561 ret = amd_xgbe_phy_switch_mode(phydev);
562 if (ret < 0)
563 return AMD_XGBE_AN_ERROR;
564
565 return AMD_XGBE_AN_START;
566}
567
568static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
569 enum amd_xgbe_phy_rx *state)
570{
571 struct amd_xgbe_phy_priv *priv = phydev->priv;
572 int ad_reg, lp_reg, ret;
573
574 *state = AMD_XGBE_RX_COMPLETE;
575
576 /* If we're in KX mode then we're done */
577 if (priv->mode == AMD_XGBE_MODE_KX)
578 return AMD_XGBE_AN_EVENT;
579
580 /* Enable/Disable FEC */
581 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
582 if (ad_reg < 0)
583 return AMD_XGBE_AN_ERROR;
584
585 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
586 if (lp_reg < 0)
587 return AMD_XGBE_AN_ERROR;
588
589 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
590 if (ret < 0)
591 return AMD_XGBE_AN_ERROR;
592
593 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
594 ret |= 0x01;
595 else
596 ret &= ~0x01;
597
598 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
599
600 /* Start KR training */
601 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
602 if (ret < 0)
603 return AMD_XGBE_AN_ERROR;
604
605 ret |= 0x01;
606 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
607
608 return AMD_XGBE_AN_EVENT;
609}
610
611static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
612 enum amd_xgbe_phy_rx *state)
613{
614 u16 msg;
615
616 *state = AMD_XGBE_RX_XNP;
617
618 msg = XNP_MCF_NULL_MESSAGE;
619 msg |= XNP_MP_FORMATTED;
620
621 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
622 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
623 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
624
625 return AMD_XGBE_AN_EVENT;
626}
627
628static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
629 enum amd_xgbe_phy_rx *state)
630{
631 struct amd_xgbe_phy_priv *priv = phydev->priv;
632 unsigned int link_support;
633 int ret, ad_reg, lp_reg;
634
635 /* Read Base Ability register 2 first */
636 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
637 if (ret < 0)
638 return AMD_XGBE_AN_ERROR;
639
640 /* Check for a supported mode, otherwise restart in a different one */
641 link_support = (priv->mode == AMD_XGBE_MODE_KR) ? 0x80 : 0x20;
642 if (!(ret & link_support))
643 return amd_xgbe_an_switch_mode(phydev);
644
645 /* Check Extended Next Page support */
646 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
647 if (ad_reg < 0)
648 return AMD_XGBE_AN_ERROR;
649
650 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
651 if (lp_reg < 0)
652 return AMD_XGBE_AN_ERROR;
653
654 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
655 amd_xgbe_an_tx_xnp(phydev, state) :
656 amd_xgbe_an_tx_training(phydev, state);
657}
658
659static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
660 enum amd_xgbe_phy_rx *state)
661{
662 int ad_reg, lp_reg;
663
664 /* Check Extended Next Page support */
665 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
666 if (ad_reg < 0)
667 return AMD_XGBE_AN_ERROR;
668
669 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
670 if (lp_reg < 0)
671 return AMD_XGBE_AN_ERROR;
672
673 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
674 amd_xgbe_an_tx_xnp(phydev, state) :
675 amd_xgbe_an_tx_training(phydev, state);
676}
677
678static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
679{
680 struct amd_xgbe_phy_priv *priv = phydev->priv;
681 int ret;
682
683 /* Be sure we aren't looping trying to negotiate */
684 if (priv->mode == AMD_XGBE_MODE_KR) {
685 if (priv->kr_state != AMD_XGBE_RX_READY)
686 return AMD_XGBE_AN_NO_LINK;
687 priv->kr_state = AMD_XGBE_RX_BPA;
688 } else {
689 if (priv->kx_state != AMD_XGBE_RX_READY)
690 return AMD_XGBE_AN_NO_LINK;
691 priv->kx_state = AMD_XGBE_RX_BPA;
692 }
693
694 /* Set up Advertisement register 3 first */
695 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
696 if (ret < 0)
697 return AMD_XGBE_AN_ERROR;
698
699 if (phydev->supported & SUPPORTED_10000baseR_FEC)
700 ret |= 0xc000;
701 else
702 ret &= ~0xc000;
703
704 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
705
706 /* Set up Advertisement register 2 next */
707 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
708 if (ret < 0)
709 return AMD_XGBE_AN_ERROR;
710
711 if (phydev->supported & SUPPORTED_10000baseKR_Full)
712 ret |= 0x80;
713 else
714 ret &= ~0x80;
715
716 if (phydev->supported & SUPPORTED_1000baseKX_Full)
717 ret |= 0x20;
718 else
719 ret &= ~0x20;
720
721 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
722
723 /* Set up Advertisement register 1 last */
724 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
725 if (ret < 0)
726 return AMD_XGBE_AN_ERROR;
727
728 if (phydev->supported & SUPPORTED_Pause)
729 ret |= 0x400;
730 else
731 ret &= ~0x400;
732
733 if (phydev->supported & SUPPORTED_Asym_Pause)
734 ret |= 0x800;
735 else
736 ret &= ~0x800;
737
738 /* We don't intend to perform XNP */
739 ret &= ~XNP_NP_EXCHANGE;
740
741 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
742
743 /* Enable and start auto-negotiation */
744 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
745
746 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
747 if (ret < 0)
748 return AMD_XGBE_AN_ERROR;
749
750 ret |= MDIO_AN_CTRL1_ENABLE;
751 ret |= MDIO_AN_CTRL1_RESTART;
752 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
753
754 return AMD_XGBE_AN_EVENT;
755}
756
757static enum amd_xgbe_phy_an amd_xgbe_an_event(struct phy_device *phydev)
758{
759 enum amd_xgbe_phy_an new_state;
760 int ret;
761
762 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
763 if (ret < 0)
764 return AMD_XGBE_AN_ERROR;
765
766 new_state = AMD_XGBE_AN_EVENT;
767 if (ret & XGBE_AN_PG_RCV)
768 new_state = AMD_XGBE_AN_PAGE_RECEIVED;
769 else if (ret & XGBE_AN_INC_LINK)
770 new_state = AMD_XGBE_AN_INCOMPAT_LINK;
771 else if (ret & XGBE_AN_INT_CMPLT)
772 new_state = AMD_XGBE_AN_COMPLETE;
773
774 if (new_state != AMD_XGBE_AN_EVENT)
775 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
776
777 return new_state;
778}
779
780static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
781{
782 struct amd_xgbe_phy_priv *priv = phydev->priv;
783 enum amd_xgbe_phy_rx *state;
784 int ret;
785
786 state = (priv->mode == AMD_XGBE_MODE_KR) ? &priv->kr_state
787 : &priv->kx_state;
788
789 switch (*state) {
790 case AMD_XGBE_RX_BPA:
791 ret = amd_xgbe_an_rx_bpa(phydev, state);
792 break;
793
794 case AMD_XGBE_RX_XNP:
795 ret = amd_xgbe_an_rx_xnp(phydev, state);
796 break;
797
798 default:
799 ret = AMD_XGBE_AN_ERROR;
800 }
801
802 return ret;
803}
804
805static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
806{
807 return amd_xgbe_an_switch_mode(phydev);
808}
809
810static void amd_xgbe_an_state_machine(struct work_struct *work)
811{
812 struct amd_xgbe_phy_priv *priv = container_of(work,
813 struct amd_xgbe_phy_priv,
814 an_work);
815 struct phy_device *phydev = priv->phydev;
816 enum amd_xgbe_phy_an cur_state;
817 int sleep;
818
819 while (1) {
820 mutex_lock(&priv->an_mutex);
821
822 cur_state = priv->an_state;
823
824 switch (priv->an_state) {
825 case AMD_XGBE_AN_START:
826 priv->an_state = amd_xgbe_an_start(phydev);
827 break;
828
829 case AMD_XGBE_AN_EVENT:
830 priv->an_state = amd_xgbe_an_event(phydev);
831 break;
832
833 case AMD_XGBE_AN_PAGE_RECEIVED:
834 priv->an_state = amd_xgbe_an_page_received(phydev);
835 break;
836
837 case AMD_XGBE_AN_INCOMPAT_LINK:
838 priv->an_state = amd_xgbe_an_incompat_link(phydev);
839 break;
840
841 case AMD_XGBE_AN_COMPLETE:
842 case AMD_XGBE_AN_NO_LINK:
843 case AMD_XGBE_AN_EXIT:
844 goto exit_unlock;
845
846 default:
847 priv->an_state = AMD_XGBE_AN_ERROR;
848 }
849
850 if (priv->an_state == AMD_XGBE_AN_ERROR) {
851 netdev_err(phydev->attached_dev,
852 "error during auto-negotiation, state=%u\n",
853 cur_state);
854 goto exit_unlock;
855 }
856
857 sleep = (priv->an_state == AMD_XGBE_AN_EVENT) ? 1 : 0;
858
859 mutex_unlock(&priv->an_mutex);
860
861 if (sleep)
862 usleep_range(20, 50);
863 }
864
865exit_unlock:
866 priv->an_result = priv->an_state;
867 priv->an_state = AMD_XGBE_AN_READY;
868
869 mutex_unlock(&priv->an_mutex);
870}
871
872static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
873{
874 int count, ret;
875
876 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
877 if (ret < 0)
878 return ret;
879
880 ret |= MDIO_CTRL1_RESET;
881 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
882
883 count = 50;
884 do {
885 msleep(20);
886 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
887 if (ret < 0)
888 return ret;
889 } while ((ret & MDIO_CTRL1_RESET) && --count);
890
891 if (ret & MDIO_CTRL1_RESET)
892 return -ETIMEDOUT;
893
894 return 0;
895}
896
897static int amd_xgbe_phy_config_init(struct phy_device *phydev)
898{
899 /* Initialize supported features */
900 phydev->supported = SUPPORTED_Autoneg;
901 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
902 phydev->supported |= SUPPORTED_Backplane;
903 phydev->supported |= SUPPORTED_1000baseKX_Full |
904 SUPPORTED_2500baseX_Full;
905 phydev->supported |= SUPPORTED_10000baseKR_Full |
906 SUPPORTED_10000baseR_FEC;
907 phydev->advertising = phydev->supported;
908
909 /* Turn off and clear interrupts */
910 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
911 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
912
913 return 0;
914}
915
916static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
917{
918 int ret;
919
920 /* Disable auto-negotiation */
921 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
922 if (ret < 0)
923 return ret;
924
925 ret &= ~MDIO_AN_CTRL1_ENABLE;
926 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
927
928 /* Validate/Set specified speed */
929 switch (phydev->speed) {
930 case SPEED_10000:
931 ret = amd_xgbe_phy_xgmii_mode(phydev);
932 break;
933
934 case SPEED_2500:
935 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
936 break;
937
938 case SPEED_1000:
939 ret = amd_xgbe_phy_gmii_mode(phydev);
940 break;
941
942 default:
943 ret = -EINVAL;
944 }
945
946 if (ret < 0)
947 return ret;
948
949 /* Validate duplex mode */
950 if (phydev->duplex != DUPLEX_FULL)
951 return -EINVAL;
952
953 phydev->pause = 0;
954 phydev->asym_pause = 0;
955
956 return 0;
957}
958
959static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
960{
961 struct amd_xgbe_phy_priv *priv = phydev->priv;
962 u32 mmd_mask = phydev->c45_ids.devices_in_package;
963 int ret;
964
965 if (phydev->autoneg != AUTONEG_ENABLE)
966 return amd_xgbe_phy_setup_forced(phydev);
967
968 /* Make sure we have the AN MMD present */
969 if (!(mmd_mask & MDIO_DEVS_AN))
970 return -EINVAL;
971
972 /* Get the current speed mode */
973 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
974 if (ret < 0)
975 return ret;
976
977 /* Start/Restart the auto-negotiation state machine */
978 mutex_lock(&priv->an_mutex);
979 priv->an_result = AMD_XGBE_AN_READY;
980 priv->an_state = AMD_XGBE_AN_START;
981 priv->kr_state = AMD_XGBE_RX_READY;
982 priv->kx_state = AMD_XGBE_RX_READY;
983 mutex_unlock(&priv->an_mutex);
984
985 queue_work(priv->an_workqueue, &priv->an_work);
986
987 return 0;
988}
989
990static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
991{
992 struct amd_xgbe_phy_priv *priv = phydev->priv;
993 enum amd_xgbe_phy_an state;
994
995 mutex_lock(&priv->an_mutex);
996 state = priv->an_result;
997 mutex_unlock(&priv->an_mutex);
998
999 return (state == AMD_XGBE_AN_COMPLETE);
1000}
1001
1002static int amd_xgbe_phy_update_link(struct phy_device *phydev)
1003{
1004 struct amd_xgbe_phy_priv *priv = phydev->priv;
1005 enum amd_xgbe_phy_an state;
1006 unsigned int check_again, autoneg;
1007 int ret;
1008
1009 /* If we're doing auto-negotiation don't report link down */
1010 mutex_lock(&priv->an_mutex);
1011 state = priv->an_state;
1012 mutex_unlock(&priv->an_mutex);
1013
1014 if (state != AMD_XGBE_AN_READY) {
1015 phydev->link = 1;
1016 return 0;
1017 }
1018
1019 /* Since the device can be in the wrong mode when a link is
1020 * (re-)established (cable connected after the interface is
1021 * up, etc.), the link status may report no link. If there
1022 * is no link, try switching modes and checking the status
1023 * again.
1024 */
1025 check_again = 1;
1026again:
1027 /* Link status is latched low, so read once to clear
1028 * and then read again to get current state
1029 */
1030 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1031 if (ret < 0)
1032 return ret;
1033
1034 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1035 if (ret < 0)
1036 return ret;
1037
1038 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1039
1040 if (!phydev->link) {
1041 ret = amd_xgbe_phy_switch_mode(phydev);
1042 if (check_again) {
1043 check_again = 0;
1044 goto again;
1045 }
1046 }
1047
1048 autoneg = (phydev->link && !priv->link) ? 1 : 0;
1049 priv->link = phydev->link;
1050 if (autoneg) {
1051 /* Link is (back) up, re-start auto-negotiation */
1052 ret = amd_xgbe_phy_config_aneg(phydev);
1053 if (ret < 0)
1054 return ret;
1055 }
1056
1057 return 0;
1058}
1059
1060static int amd_xgbe_phy_read_status(struct phy_device *phydev)
1061{
1062 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1063 int ret, mode, ad_ret, lp_ret;
1064
1065 ret = amd_xgbe_phy_update_link(phydev);
1066 if (ret)
1067 return ret;
1068
1069 mode = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
1070 if (mode < 0)
1071 return mode;
1072 mode &= MDIO_PCS_CTRL2_TYPE;
1073
1074 if (phydev->autoneg == AUTONEG_ENABLE) {
1075 if (!(mmd_mask & MDIO_DEVS_AN))
1076 return -EINVAL;
1077
1078 if (!amd_xgbe_phy_aneg_done(phydev))
1079 return 0;
1080
1081 /* Compare Advertisement and Link Partner register 1 */
1082 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1083 if (ad_ret < 0)
1084 return ad_ret;
1085 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
1086 if (lp_ret < 0)
1087 return lp_ret;
1088
1089 ad_ret &= lp_ret;
1090 phydev->pause = (ad_ret & 0x400) ? 1 : 0;
1091 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
1092
1093 /* Compare Advertisement and Link Partner register 2 */
1094 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
1095 MDIO_AN_ADVERTISE + 1);
1096 if (ad_ret < 0)
1097 return ad_ret;
1098 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1099 if (lp_ret < 0)
1100 return lp_ret;
1101
1102 ad_ret &= lp_ret;
1103 if (ad_ret & 0x80) {
1104 phydev->speed = SPEED_10000;
1105 if (mode != MDIO_PCS_CTRL2_10GBR) {
1106 ret = amd_xgbe_phy_xgmii_mode(phydev);
1107 if (ret < 0)
1108 return ret;
1109 }
1110 } else {
1111 phydev->speed = SPEED_1000;
1112 if (mode == MDIO_PCS_CTRL2_10GBR) {
1113 ret = amd_xgbe_phy_gmii_mode(phydev);
1114 if (ret < 0)
1115 return ret;
1116 }
1117 }
1118
1119 phydev->duplex = DUPLEX_FULL;
1120 } else {
1121 phydev->speed = (mode == MDIO_PCS_CTRL2_10GBR) ? SPEED_10000
1122 : SPEED_1000;
1123 phydev->duplex = DUPLEX_FULL;
1124 phydev->pause = 0;
1125 phydev->asym_pause = 0;
1126 }
1127
1128 return 0;
1129}
1130
1131static int amd_xgbe_phy_suspend(struct phy_device *phydev)
1132{
1133 int ret;
1134
1135 mutex_lock(&phydev->lock);
1136
1137 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1138 if (ret < 0)
1139 goto unlock;
1140
1141 ret |= MDIO_CTRL1_LPOWER;
1142 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1143
1144 ret = 0;
1145
1146unlock:
1147 mutex_unlock(&phydev->lock);
1148
1149 return ret;
1150}
1151
1152static int amd_xgbe_phy_resume(struct phy_device *phydev)
1153{
1154 int ret;
1155
1156 mutex_lock(&phydev->lock);
1157
1158 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1159 if (ret < 0)
1160 goto unlock;
1161
1162 ret &= ~MDIO_CTRL1_LPOWER;
1163 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1164
1165 ret = 0;
1166
1167unlock:
1168 mutex_unlock(&phydev->lock);
1169
1170 return ret;
1171}
1172
1173static int amd_xgbe_phy_probe(struct phy_device *phydev)
1174{
1175 struct amd_xgbe_phy_priv *priv;
1176 struct platform_device *pdev;
1177 struct device *dev;
1178 char *wq_name;
1179 int ret;
1180
1181 if (!phydev->dev.of_node)
1182 return -EINVAL;
1183
1184 pdev = of_find_device_by_node(phydev->dev.of_node);
1185 if (!pdev)
1186 return -EINVAL;
1187 dev = &pdev->dev;
1188
1189 wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
1190 if (!wq_name) {
1191 ret = -ENOMEM;
1192 goto err_pdev;
1193 }
1194
1195 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1196 if (!priv) {
1197 ret = -ENOMEM;
1198 goto err_name;
1199 }
1200
1201 priv->pdev = pdev;
1202 priv->dev = dev;
1203 priv->phydev = phydev;
1204
1205 /* Get the device mmio areas */
1206 priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
1208 if (IS_ERR(priv->rxtx_regs)) {
1209 dev_err(dev, "rxtx ioremap failed\n");
1210 ret = PTR_ERR(priv->rxtx_regs);
1211 goto err_priv;
1212 }
1213
1214 priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1215 priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
1216 if (IS_ERR(priv->sir0_regs)) {
1217 dev_err(dev, "sir0 ioremap failed\n");
1218 ret = PTR_ERR(priv->sir0_regs);
1219 goto err_rxtx;
1220 }
1221
1222 priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1223 priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
1224 if (IS_ERR(priv->sir1_regs)) {
1225 dev_err(dev, "sir1 ioremap failed\n");
1226 ret = PTR_ERR(priv->sir1_regs);
1227 goto err_sir0;
1228 }
1229
1230 priv->link = 1;
1231
1232 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
1233 if (ret < 0)
1234 goto err_sir1;
1235 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
1236 priv->mode = AMD_XGBE_MODE_KR;
1237 else
1238 priv->mode = AMD_XGBE_MODE_KX;
1239
1240 mutex_init(&priv->an_mutex);
1241 INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
1242 priv->an_workqueue = create_singlethread_workqueue(wq_name);
1243 if (!priv->an_workqueue) {
1244 ret = -ENOMEM;
1245 goto err_sir1;
1246 }
1247
1248 phydev->priv = priv;
1249
1250 kfree(wq_name);
1251 of_dev_put(pdev);
1252
1253 return 0;
1254
1255err_sir1:
1256 devm_iounmap(dev, priv->sir1_regs);
1257 devm_release_mem_region(dev, priv->sir1_res->start,
1258 resource_size(priv->sir1_res));
1259
1260err_sir0:
1261 devm_iounmap(dev, priv->sir0_regs);
1262 devm_release_mem_region(dev, priv->sir0_res->start,
1263 resource_size(priv->sir0_res));
1264
1265err_rxtx:
1266 devm_iounmap(dev, priv->rxtx_regs);
1267 devm_release_mem_region(dev, priv->rxtx_res->start,
1268 resource_size(priv->rxtx_res));
1269
1270err_priv:
1271 devm_kfree(dev, priv);
1272
1273err_name:
1274 kfree(wq_name);
1275
1276err_pdev:
1277 of_dev_put(pdev);
1278
1279 return ret;
1280}
1281
1282static void amd_xgbe_phy_remove(struct phy_device *phydev)
1283{
1284 struct amd_xgbe_phy_priv *priv = phydev->priv;
1285 struct device *dev = priv->dev;
1286
1287 /* Stop any in process auto-negotiation */
1288 mutex_lock(&priv->an_mutex);
1289 priv->an_state = AMD_XGBE_AN_EXIT;
1290 mutex_unlock(&priv->an_mutex);
1291
1292 flush_workqueue(priv->an_workqueue);
1293 destroy_workqueue(priv->an_workqueue);
1294
1295 /* Release resources */
1296 devm_iounmap(dev, priv->sir1_regs);
1297 devm_release_mem_region(dev, priv->sir1_res->start,
1298 resource_size(priv->sir1_res));
1299
1300 devm_iounmap(dev, priv->sir0_regs);
1301 devm_release_mem_region(dev, priv->sir0_res->start,
1302 resource_size(priv->sir0_res));
1303
1304 devm_iounmap(dev, priv->rxtx_regs);
1305 devm_release_mem_region(dev, priv->rxtx_res->start,
1306 resource_size(priv->rxtx_res));
1307
1308 devm_kfree(dev, priv);
1309}
1310
1311static int amd_xgbe_match_phy_device(struct phy_device *phydev)
1312{
1313 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
1314}
1315
1316static struct phy_driver amd_xgbe_phy_driver[] = {
1317 {
1318 .phy_id = XGBE_PHY_ID,
1319 .phy_id_mask = XGBE_PHY_MASK,
1320 .name = "AMD XGBE PHY",
1321 .features = 0,
1322 .probe = amd_xgbe_phy_probe,
1323 .remove = amd_xgbe_phy_remove,
1324 .soft_reset = amd_xgbe_phy_soft_reset,
1325 .config_init = amd_xgbe_phy_config_init,
1326 .suspend = amd_xgbe_phy_suspend,
1327 .resume = amd_xgbe_phy_resume,
1328 .config_aneg = amd_xgbe_phy_config_aneg,
1329 .aneg_done = amd_xgbe_phy_aneg_done,
1330 .read_status = amd_xgbe_phy_read_status,
1331 .match_phy_device = amd_xgbe_match_phy_device,
1332 .driver = {
1333 .owner = THIS_MODULE,
1334 },
1335 },
1336};
1337
1338static int __init amd_xgbe_phy_init(void)
1339{
1340 return phy_drivers_register(amd_xgbe_phy_driver,
1341 ARRAY_SIZE(amd_xgbe_phy_driver));
1342}
1343
1344static void __exit amd_xgbe_phy_exit(void)
1345{
1346 phy_drivers_unregister(amd_xgbe_phy_driver,
1347 ARRAY_SIZE(amd_xgbe_phy_driver));
1348}
1349
1350module_init(amd_xgbe_phy_init);
1351module_exit(amd_xgbe_phy_exit);
1352
1353static struct mdio_device_id amd_xgbe_phy_ids[] = {
1354 { XGBE_PHY_ID, XGBE_PHY_MASK },
1355 { }
1356};
1357MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 15:37:15 -0500