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authorFabio Estevam <fabio.estevam@freescale.com>2014-07-07 09:04:52 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 04:49:44 -0400
commit4c03527eb77ca267e60a2ea2e86497aab3bf7ea9 (patch)
tree4a336a9a3e2bf5bcb7938a5073b9b841f22f0bc4
parentea336fa8eeb4b00f746983e3f24bc99e1547fb58 (diff)
ARM: imx6: Align ssi nodes between mx6 variants
Since commit 98ea6ad2edd2 (ARM: dts: imx6: use imx51-ssi) the mx6 ssi is compatible with imx51, so align all the mx6 variant ssi compatible strings as: compatible = "fsl,<imx6-soc>-ssi", "fsl,imx51-ssi"; Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi9
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi9
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi6
3 files changed, 9 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d7c97d95c525..c701af958006 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -274,8 +274,7 @@
274 274
275 ssi1: ssi@02028000 { 275 ssi1: ssi@02028000 {
276 compatible = "fsl,imx6q-ssi", 276 compatible = "fsl,imx6q-ssi",
277 "fsl,imx51-ssi", 277 "fsl,imx51-ssi";
278 "fsl,imx21-ssi";
279 reg = <0x02028000 0x4000>; 278 reg = <0x02028000 0x4000>;
280 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; 280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
@@ -288,8 +287,7 @@
288 287
289 ssi2: ssi@0202c000 { 288 ssi2: ssi@0202c000 {
290 compatible = "fsl,imx6q-ssi", 289 compatible = "fsl,imx6q-ssi",
291 "fsl,imx51-ssi", 290 "fsl,imx51-ssi";
292 "fsl,imx21-ssi";
293 reg = <0x0202c000 0x4000>; 291 reg = <0x0202c000 0x4000>;
294 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; 293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
@@ -302,8 +300,7 @@
302 300
303 ssi3: ssi@02030000 { 301 ssi3: ssi@02030000 {
304 compatible = "fsl,imx6q-ssi", 302 compatible = "fsl,imx6q-ssi",
305 "fsl,imx51-ssi", 303 "fsl,imx51-ssi";
306 "fsl,imx21-ssi";
307 reg = <0x02030000 0x4000>; 304 reg = <0x02030000 0x4000>;
308 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; 306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 0467ac064e9d..c75800ca8b35 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -227,8 +227,7 @@
227 227
228 ssi1: ssi@02028000 { 228 ssi1: ssi@02028000 {
229 compatible = "fsl,imx6sl-ssi", 229 compatible = "fsl,imx6sl-ssi",
230 "fsl,imx51-ssi", 230 "fsl,imx51-ssi";
231 "fsl,imx21-ssi";
232 reg = <0x02028000 0x4000>; 231 reg = <0x02028000 0x4000>;
233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6SL_CLK_SSI1>; 233 clocks = <&clks IMX6SL_CLK_SSI1>;
@@ -241,8 +240,7 @@
241 240
242 ssi2: ssi@0202c000 { 241 ssi2: ssi@0202c000 {
243 compatible = "fsl,imx6sl-ssi", 242 compatible = "fsl,imx6sl-ssi",
244 "fsl,imx51-ssi", 243 "fsl,imx51-ssi";
245 "fsl,imx21-ssi";
246 reg = <0x0202c000 0x4000>; 244 reg = <0x0202c000 0x4000>;
247 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 245 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clks IMX6SL_CLK_SSI2>; 246 clocks = <&clks IMX6SL_CLK_SSI2>;
@@ -255,8 +253,7 @@
255 253
256 ssi3: ssi@02030000 { 254 ssi3: ssi@02030000 {
257 compatible = "fsl,imx6sl-ssi", 255 compatible = "fsl,imx6sl-ssi",
258 "fsl,imx51-ssi", 256 "fsl,imx51-ssi";
259 "fsl,imx21-ssi";
260 reg = <0x02030000 0x4000>; 257 reg = <0x02030000 0x4000>;
261 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 258 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clks IMX6SL_CLK_SSI3>; 259 clocks = <&clks IMX6SL_CLK_SSI3>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 0c5094adedfa..f4b9da65bc0f 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -298,7 +298,7 @@
298 }; 298 };
299 299
300 ssi1: ssi@02028000 { 300 ssi1: ssi@02028000 {
301 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; 301 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
302 reg = <0x02028000 0x4000>; 302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
@@ -311,7 +311,7 @@
311 }; 311 };
312 312
313 ssi2: ssi@0202c000 { 313 ssi2: ssi@0202c000 {
314 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; 314 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
315 reg = <0x0202c000 0x4000>; 315 reg = <0x0202c000 0x4000>;
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 317 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
@@ -324,7 +324,7 @@
324 }; 324 };
325 325
326 ssi3: ssi@02030000 { 326 ssi3: ssi@02030000 {
327 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; 327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02030000 0x4000>; 328 reg = <0x02030000 0x4000>;
329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 330 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 22:52:10 -0400