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authorLinus Torvalds <torvalds@linux-foundation.org>2012-06-28 14:26:42 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-06-28 14:26:42 -0400
commit4a9c46978d9a7e8f2b41f757eb24bd190b1a3b7b (patch)
treebd36a6b474bc61050ecb80fd961e7ea04f403202
parentef726227e74fa59900efe3223136a53f01b245a8 (diff)
parent2266b058d3ab9dfc545305d68e754ad9c9a639a0 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Nearly all intel, one missing license header in nouveau, nothing majorly earth shattering." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: Revert "drm/i915: allow PCH PWM override on IVB" drm/nouveau: add license header to prime. drm/i915: Fix eDP blank screen after S3 resume on HP desktops drm/i915: rip out the PM_IIR WARN
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c1
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c16
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_prime.c23
4 files changed, 27 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1fe0edda955..ed3224c37423 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
412 */ 412 */
413 413
414 spin_lock_irqsave(&dev_priv->rps_lock, flags); 414 spin_lock_irqsave(&dev_priv->rps_lock, flags);
415 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
416 dev_priv->pm_iir |= pm_iir; 415 dev_priv->pm_iir |= pm_iir;
417 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 416 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
418 POSTING_READ(GEN6_PMIMR); 417 POSTING_READ(GEN6_PMIMR);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0ede02a99d91..a748e5cabe14 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -740,8 +740,11 @@ static void i915_restore_display(struct drm_device *dev)
740 if (HAS_PCH_SPLIT(dev)) { 740 if (HAS_PCH_SPLIT(dev)) {
741 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 741 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
742 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 742 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
743 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 743 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
744 * otherwise we get blank eDP screen after S3 on some machines
745 */
744 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); 746 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
747 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
745 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 748 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
746 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 749 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
747 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 750 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a7c727d0c105..a8538ac0299d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6921,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
6921 POSTING_READ(vga_reg); 6921 POSTING_READ(vga_reg);
6922} 6922}
6923 6923
6924static void ivb_pch_pwm_override(struct drm_device *dev)
6925{
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927
6928 /*
6929 * IVB has CPU eDP backlight regs too, set things up to let the
6930 * PCH regs control the backlight
6931 */
6932 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6933 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6934 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6935}
6936
6937void intel_modeset_init_hw(struct drm_device *dev) 6924void intel_modeset_init_hw(struct drm_device *dev)
6938{ 6925{
6939 struct drm_i915_private *dev_priv = dev->dev_private; 6926 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6950,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
6950 gen6_enable_rps(dev_priv); 6937 gen6_enable_rps(dev_priv);
6951 gen6_update_ring_freq(dev_priv); 6938 gen6_update_ring_freq(dev_priv);
6952 } 6939 }
6953
6954 if (IS_IVYBRIDGE(dev))
6955 ivb_pch_pwm_override(dev);
6956} 6940}
6957 6941
6958void intel_modeset_init(struct drm_device *dev) 6942void intel_modeset_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index a89240e5fb29..a25cf2cb931f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -1,3 +1,26 @@
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Dave Airlie
23 */
1 24
2#include "drmP.h" 25#include "drmP.h"
3#include "drm.h" 26#include "drm.h"