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authorHauke Mehrtens <hauke@hauke-m.de>2012-01-30 18:03:35 -0500
committerJohn W. Linville <linville@tuxdriver.com>2012-02-06 14:53:04 -0500
commit49dc9577155576b10ff79f0c1486c816b01f58bf (patch)
treec193e6110c54234ab5ed3d816cc2dc15df165f37
parentd1a7a8e1d367e34e5adce91f48cae07dc08d9e6c (diff)
bcma: add PCIe host controller
Some SoCs have a PCIe host controller to make it possible to attach some other devices to it, like an other Wifi card. This code was tested with an Netgear WNDR3400 (bcm4716 based), but should work with all bcma based SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--arch/mips/pci/pci-bcm47xx.c49
-rw-r--r--drivers/bcma/bcma_private.h1
-rw-r--r--drivers/bcma/driver_pci.c38
-rw-r--r--drivers/bcma/driver_pci_host.c576
-rw-r--r--include/linux/bcma/bcma_driver_pci.h38
-rw-r--r--include/linux/bcma/bcma_regs.h27
6 files changed, 690 insertions, 39 deletions
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index 400535a955d0..c682468010c5 100644
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -25,6 +25,7 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/pci.h> 26#include <linux/pci.h>
27#include <linux/ssb/ssb.h> 27#include <linux/ssb/ssb.h>
28#include <linux/bcma/bcma.h>
28#include <bcm47xx.h> 29#include <bcm47xx.h>
29 30
30int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 31int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
32 return 0; 33 return 0;
33} 34}
34 35
35int pcibios_plat_dev_init(struct pci_dev *dev)
36{
37#ifdef CONFIG_BCM47XX_SSB 36#ifdef CONFIG_BCM47XX_SSB
37static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev)
38{
38 int res; 39 int res;
39 u8 slot, pin; 40 u8 slot, pin;
40 41
41 if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
42 return 0;
43
44 res = ssb_pcibios_plat_dev_init(dev); 42 res = ssb_pcibios_plat_dev_init(dev);
45 if (res < 0) { 43 if (res < 0) {
46 printk(KERN_ALERT "PCI: Failed to init device %s\n", 44 printk(KERN_ALERT "PCI: Failed to init device %s\n",
@@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
60 } 58 }
61 59
62 dev->irq = res; 60 dev->irq = res;
61 return 0;
62}
63#endif 63#endif
64
65#ifdef CONFIG_BCM47XX_BCMA
66static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
67{
68 int res;
69
70 res = bcma_core_pci_plat_dev_init(dev);
71 if (res < 0) {
72 printk(KERN_ALERT "PCI: Failed to init device %s\n",
73 pci_name(dev));
74 return res;
75 }
76
77 res = bcma_core_pci_pcibios_map_irq(dev);
78
79 /* IRQ-0 and IRQ-1 are software interrupts. */
80 if (res < 2) {
81 printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
82 pci_name(dev));
83 return res;
84 }
85
86 dev->irq = res;
64 return 0; 87 return 0;
65} 88}
89#endif
90
91int pcibios_plat_dev_init(struct pci_dev *dev)
92{
93#ifdef CONFIG_BCM47XX_SSB
94 if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
95 return bcm47xx_pcibios_plat_dev_init_ssb(dev);
96 else
97#endif
98#ifdef CONFIG_BCM47XX_BCMA
99 if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA)
100 return bcm47xx_pcibios_plat_dev_init_bcma(dev);
101 else
102#endif
103 return 0;
104}
diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h
index 63c5242159f2..b81755bb4798 100644
--- a/drivers/bcma/bcma_private.h
+++ b/drivers/bcma/bcma_private.h
@@ -52,6 +52,7 @@ extern void __exit bcma_host_pci_exit(void);
52u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); 52u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
53 53
54#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE 54#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
55bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
55void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); 56void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
56#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ 57#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
57 58
diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c
index 155d953dba74..4d38ae179b48 100644
--- a/drivers/bcma/driver_pci.c
+++ b/drivers/bcma/driver_pci.c
@@ -2,7 +2,7 @@
2 * Broadcom specific AMBA 2 * Broadcom specific AMBA
3 * PCI Core 3 * PCI Core
4 * 4 *
5 * Copyright 2005, Broadcom Corporation 5 * Copyright 2005, 2011, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> 7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8 * 8 *
@@ -179,47 +179,19 @@ static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
179 bcma_pcicore_serdes_workaround(pc); 179 bcma_pcicore_serdes_workaround(pc);
180} 180}
181 181
182static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
183{
184 struct bcma_bus *bus = pc->core->bus;
185 u16 chipid_top;
186
187 chipid_top = (bus->chipinfo.id & 0xFF00);
188 if (chipid_top != 0x4700 &&
189 chipid_top != 0x5300)
190 return false;
191
192#ifdef CONFIG_SSB_DRIVER_PCICORE
193 if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
194 return false;
195#endif /* CONFIG_SSB_DRIVER_PCICORE */
196
197#if 0
198 /* TODO: on BCMA we use address from EROM instead of magic formula */
199 u32 tmp;
200 return !mips_busprobe32(tmp, (bus->mmio +
201 (pc->core->core_index * BCMA_CORE_SIZE)));
202#endif
203
204 return true;
205}
206
207void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) 182void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
208{ 183{
209 if (pc->setup_done) 184 if (pc->setup_done)
210 return; 185 return;
211 186
212 if (bcma_core_pci_is_in_hostmode(pc)) {
213#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE 187#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
188 pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
189 if (pc->hostmode)
214 bcma_core_pci_hostmode_init(pc); 190 bcma_core_pci_hostmode_init(pc);
215#else
216 pr_err("Driver compiled without support for hostmode PCI\n");
217#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ 191#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
218 } else {
219 bcma_core_pci_clientmode_init(pc);
220 }
221 192
222 pc->setup_done = true; 193 if (!pc->hostmode)
194 bcma_core_pci_clientmode_init(pc);
223} 195}
224 196
225int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, 197int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c
index 99e040b607a2..4e20bcfa7ec5 100644
--- a/drivers/bcma/driver_pci_host.c
+++ b/drivers/bcma/driver_pci_host.c
@@ -2,13 +2,587 @@
2 * Broadcom specific AMBA 2 * Broadcom specific AMBA
3 * PCI Core in hostmode 3 * PCI Core in hostmode
4 * 4 *
5 * Copyright 2005 - 2011, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8 *
5 * Licensed under the GNU/GPL. See COPYING for details. 9 * Licensed under the GNU/GPL. See COPYING for details.
6 */ 10 */
7 11
8#include "bcma_private.h" 12#include "bcma_private.h"
13#include <linux/export.h>
9#include <linux/bcma/bcma.h> 14#include <linux/bcma/bcma.h>
15#include <asm/paccess.h>
16
17/* Probe a 32bit value on the bus and catch bus exceptions.
18 * Returns nonzero on a bus exception.
19 * This is MIPS specific */
20#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
21
22/* Assume one-hot slot wiring */
23#define BCMA_PCI_SLOT_MAX 16
24#define PCI_CONFIG_SPACE_SIZE 256
25
26bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
27{
28 struct bcma_bus *bus = pc->core->bus;
29 u16 chipid_top;
30 u32 tmp;
31
32 chipid_top = (bus->chipinfo.id & 0xFF00);
33 if (chipid_top != 0x4700 &&
34 chipid_top != 0x5300)
35 return false;
36
37 if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
38 pr_info("This PCI core is disabled and not working\n");
39 return false;
40 }
41
42 bcma_core_enable(pc->core, 0);
43
44 return !mips_busprobe32(tmp, pc->core->io_addr);
45}
46
47static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
48{
49 pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
50 pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
51 return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
52}
53
54static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
55 u32 data)
56{
57 pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
58 pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
59 pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
60}
61
62static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
63 unsigned int func, unsigned int off)
64{
65 u32 addr = 0;
66
67 /* Issue config commands only when the data link is up (atleast
68 * one external pcie device is present).
69 */
70 if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
71 & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
72 goto out;
73
74 /* Type 0 transaction */
75 /* Slide the PCI window to the appropriate slot */
76 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
77 /* Calculate the address */
78 addr = pc->host_controller->host_cfg_addr;
79 addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
80 addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
81 addr |= (off & ~3);
82
83out:
84 return addr;
85}
86
87static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
88 unsigned int func, unsigned int off,
89 void *buf, int len)
90{
91 int err = -EINVAL;
92 u32 addr, val;
93 void __iomem *mmio = 0;
94
95 WARN_ON(!pc->hostmode);
96 if (unlikely(len != 1 && len != 2 && len != 4))
97 goto out;
98 if (dev == 0) {
99 /* we support only two functions on device 0 */
100 if (func > 1)
101 return -EINVAL;
102
103 /* accesses to config registers with offsets >= 256
104 * requires indirect access.
105 */
106 if (off >= PCI_CONFIG_SPACE_SIZE) {
107 addr = (func << 12);
108 addr |= (off & 0x0FFF);
109 val = bcma_pcie_read_config(pc, addr);
110 } else {
111 addr = BCMA_CORE_PCI_PCICFG0;
112 addr |= (func << 8);
113 addr |= (off & 0xfc);
114 val = pcicore_read32(pc, addr);
115 }
116 } else {
117 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
118 if (unlikely(!addr))
119 goto out;
120 err = -ENOMEM;
121 mmio = ioremap_nocache(addr, len);
122 if (!mmio)
123 goto out;
124
125 if (mips_busprobe32(val, mmio)) {
126 val = 0xffffffff;
127 goto unmap;
128 }
129
130 val = readl(mmio);
131 }
132 val >>= (8 * (off & 3));
133
134 switch (len) {
135 case 1:
136 *((u8 *)buf) = (u8)val;
137 break;
138 case 2:
139 *((u16 *)buf) = (u16)val;
140 break;
141 case 4:
142 *((u32 *)buf) = (u32)val;
143 break;
144 }
145 err = 0;
146unmap:
147 if (mmio)
148 iounmap(mmio);
149out:
150 return err;
151}
152
153static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
154 unsigned int func, unsigned int off,
155 const void *buf, int len)
156{
157 int err = -EINVAL;
158 u32 addr = 0, val = 0;
159 void __iomem *mmio = 0;
160 u16 chipid = pc->core->bus->chipinfo.id;
161
162 WARN_ON(!pc->hostmode);
163 if (unlikely(len != 1 && len != 2 && len != 4))
164 goto out;
165 if (dev == 0) {
166 /* accesses to config registers with offsets >= 256
167 * requires indirect access.
168 */
169 if (off < PCI_CONFIG_SPACE_SIZE) {
170 addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
171 addr |= (func << 8);
172 addr |= (off & 0xfc);
173 mmio = ioremap_nocache(addr, len);
174 if (!mmio)
175 goto out;
176 }
177 } else {
178 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
179 if (unlikely(!addr))
180 goto out;
181 err = -ENOMEM;
182 mmio = ioremap_nocache(addr, len);
183 if (!mmio)
184 goto out;
185
186 if (mips_busprobe32(val, mmio)) {
187 val = 0xffffffff;
188 goto unmap;
189 }
190 }
191
192 switch (len) {
193 case 1:
194 val = readl(mmio);
195 val &= ~(0xFF << (8 * (off & 3)));
196 val |= *((const u8 *)buf) << (8 * (off & 3));
197 break;
198 case 2:
199 val = readl(mmio);
200 val &= ~(0xFFFF << (8 * (off & 3)));
201 val |= *((const u16 *)buf) << (8 * (off & 3));
202 break;
203 case 4:
204 val = *((const u32 *)buf);
205 break;
206 }
207 if (dev == 0 && !addr) {
208 /* accesses to config registers with offsets >= 256
209 * requires indirect access.
210 */
211 addr = (func << 12);
212 addr |= (off & 0x0FFF);
213 bcma_pcie_write_config(pc, addr, val);
214 } else {
215 writel(val, mmio);
216
217 if (chipid == 0x4716 || chipid == 0x4748)
218 readl(mmio);
219 }
220
221 err = 0;
222unmap:
223 if (mmio)
224 iounmap(mmio);
225out:
226 return err;
227}
228
229static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
230 unsigned int devfn,
231 int reg, int size, u32 *val)
232{
233 unsigned long flags;
234 int err;
235 struct bcma_drv_pci *pc;
236 struct bcma_drv_pci_host *pc_host;
237
238 pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
239 pc = pc_host->pdev;
240
241 spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
242 err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
243 PCI_FUNC(devfn), reg, val, size);
244 spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
245
246 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
247}
248
249static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
250 unsigned int devfn,
251 int reg, int size, u32 val)
252{
253 unsigned long flags;
254 int err;
255 struct bcma_drv_pci *pc;
256 struct bcma_drv_pci_host *pc_host;
257
258 pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
259 pc = pc_host->pdev;
260
261 spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
262 err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
263 PCI_FUNC(devfn), reg, &val, size);
264 spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
265
266 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
267}
268
269/* return cap_offset if requested capability exists in the PCI config space */
270static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
271 unsigned int dev,
272 unsigned int func, u8 req_cap_id,
273 unsigned char *buf, u32 *buflen)
274{
275 u8 cap_id;
276 u8 cap_ptr = 0;
277 u32 bufsize;
278 u8 byte_val;
279
280 /* check for Header type 0 */
281 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
282 sizeof(u8));
283 if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
284 return cap_ptr;
285
286 /* check if the capability pointer field exists */
287 bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
288 sizeof(u8));
289 if (!(byte_val & PCI_STATUS_CAP_LIST))
290 return cap_ptr;
291
292 /* check if the capability pointer is 0x00 */
293 bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
294 sizeof(u8));
295 if (cap_ptr == 0x00)
296 return cap_ptr;
297
298 /* loop thr'u the capability list and see if the requested capabilty
299 * exists */
300 bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
301 while (cap_id != req_cap_id) {
302 bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
303 sizeof(u8));
304 if (cap_ptr == 0x00)
305 return cap_ptr;
306 bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
307 sizeof(u8));
308 }
309
310 /* found the caller requested capability */
311 if ((buf != NULL) && (buflen != NULL)) {
312 u8 cap_data;
313
314 bufsize = *buflen;
315 if (!bufsize)
316 return cap_ptr;
317
318 *buflen = 0;
319
320 /* copy the cpability data excluding cap ID and next ptr */
321 cap_data = cap_ptr + 2;
322 if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
323 bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
324 *buflen = bufsize;
325 while (bufsize--) {
326 bcma_extpci_read_config(pc, dev, func, cap_data, buf,
327 sizeof(u8));
328 cap_data++;
329 buf++;
330 }
331 }
332
333 return cap_ptr;
334}
335
336/* If the root port is capable of returning Config Request
337 * Retry Status (CRS) Completion Status to software then
338 * enable the feature.
339 */
340static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
341{
342 u8 cap_ptr, root_ctrl, root_cap, dev;
343 u16 val16;
344 int i;
345
346 cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
347 NULL);
348 root_cap = cap_ptr + PCI_EXP_RTCAP;
349 bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
350 if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
351 /* Enable CRS software visibility */
352 root_ctrl = cap_ptr + PCI_EXP_RTCTL;
353 val16 = PCI_EXP_RTCTL_CRSSVE;
354 bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
355 sizeof(u16));
356
357 /* Initiate a configuration request to read the vendor id
358 * field of the device function's config space header after
359 * 100 ms wait time from the end of Reset. If the device is
360 * not done with its internal initialization, it must at
361 * least return a completion TLP, with a completion status
362 * of "Configuration Request Retry Status (CRS)". The root
363 * complex must complete the request to the host by returning
364 * a read-data value of 0001h for the Vendor ID field and
365 * all 1s for any additional bytes included in the request.
366 * Poll using the config reads for max wait time of 1 sec or
367 * until we receive the successful completion status. Repeat
368 * the procedure for all the devices.
369 */
370 for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
371 for (i = 0; i < 100000; i++) {
372 bcma_extpci_read_config(pc, dev, 0,
373 PCI_VENDOR_ID, &val16,
374 sizeof(val16));
375 if (val16 != 0x1)
376 break;
377 udelay(10);
378 }
379 if (val16 == 0x1)
380 pr_err("PCI: Broken device in slot %d\n", dev);
381 }
382 }
383}
10 384
11void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) 385void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
12{ 386{
13 pr_err("No support for PCI core in hostmode yet\n"); 387 struct bcma_bus *bus = pc->core->bus;
388 struct bcma_drv_pci_host *pc_host;
389 u32 tmp;
390 u32 pci_membase_1G;
391 unsigned long io_map_base;
392
393 pr_info("PCIEcore in host mode found\n");
394
395 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
396 if (!pc_host) {
397 pr_err("can not allocate memory");
398 return;
399 }
400
401 pc->host_controller = pc_host;
402 pc_host->pci_controller.io_resource = &pc_host->io_resource;
403 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
404 pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
405 pc_host->pdev = pc;
406
407 pci_membase_1G = BCMA_SOC_PCI_DMA;
408 pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
409
410 pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
411 pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
412
413 pc_host->mem_resource.name = "BCMA PCIcore external memory",
414 pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
415 pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
416 pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
417
418 pc_host->io_resource.name = "BCMA PCIcore external I/O",
419 pc_host->io_resource.start = 0x100;
420 pc_host->io_resource.end = 0x7FF;
421 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
422
423 /* Reset RC */
424 udelay(3000);
425 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
426 udelay(1000);
427 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
428 BCMA_CORE_PCI_CTL_RST_OE);
429
430 /* 64 MB I/O access window. On 4716, use
431 * sbtopcie0 to access the device registers. We
432 * can't use address match 2 (1 GB window) region
433 * as mips can't generate 64-bit address on the
434 * backplane.
435 */
436 if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
437 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
438 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
439 BCMA_SOC_PCI_MEM_SZ - 1;
440 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
441 BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
442 } else if (bus->chipinfo.id == 0x5300) {
443 tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
444 tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
445 tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
446 if (pc->core->core_unit == 0) {
447 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
448 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
449 BCMA_SOC_PCI_MEM_SZ - 1;
450 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
451 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
452 tmp | BCMA_SOC_PCI_MEM);
453 } else if (pc->core->core_unit == 1) {
454 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
455 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
456 BCMA_SOC_PCI_MEM_SZ - 1;
457 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
458 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
459 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
460 tmp | BCMA_SOC_PCI1_MEM);
461 }
462 } else
463 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
464 BCMA_CORE_PCI_SBTOPCI_IO);
465
466 /* 64 MB configuration access window */
467 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
468
469 /* 1 GB memory access window */
470 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
471 BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
472
473
474 /* As per PCI Express Base Spec 1.1 we need to wait for
475 * at least 100 ms from the end of a reset (cold/warm/hot)
476 * before issuing configuration requests to PCI Express
477 * devices.
478 */
479 udelay(100000);
480
481 bcma_core_pci_enable_crs(pc);
482
483 /* Enable PCI bridge BAR0 memory & master access */
484 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
485 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
486
487 /* Enable PCI interrupts */
488 pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
489
490 /* Ok, ready to run, register it to the system.
491 * The following needs change, if we want to port hostmode
492 * to non-MIPS platform. */
493 io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM,
494 0x04000000);
495 pc_host->pci_controller.io_map_base = io_map_base;
496 set_io_port_base(pc_host->pci_controller.io_map_base);
497 /* Give some time to the PCI controller to configure itself with the new
498 * values. Not waiting at this point causes crashes of the machine. */
499 mdelay(10);
500 register_pci_controller(&pc_host->pci_controller);
501 return;
502}
503
504/* Early PCI fixup for a device on the PCI-core bridge. */
505static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
506{
507 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
508 /* This is not a device on the PCI-core bridge. */
509 return;
510 }
511 if (PCI_SLOT(dev->devfn) != 0)
512 return;
513
514 pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
515
516 /* Enable PCI bridge bus mastering and memory space */
517 pci_set_master(dev);
518 if (pcibios_enable_device(dev, ~0) < 0) {
519 pr_err("PCI: BCMA bridge enable failed\n");
520 return;
521 }
522
523 /* Enable PCI bridge BAR1 prefetch and burst */
524 pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
525}
526DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
527
528/* Early PCI fixup for all PCI-cores to set the correct memory address. */
529static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
530{
531 struct resource *res;
532 int pos;
533
534 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
535 /* This is not a device on the PCI-core bridge. */
536 return;
537 }
538 if (PCI_SLOT(dev->devfn) == 0)
539 return;
540
541 pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
542
543 for (pos = 0; pos < 6; pos++) {
544 res = &dev->resource[pos];
545 if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
546 pci_assign_resource(dev, pos);
547 }
548}
549DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
550
551/* This function is called when doing a pci_enable_device().
552 * We must first check if the device is a device on the PCI-core bridge. */
553int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
554{
555 struct bcma_drv_pci_host *pc_host;
556
557 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
558 /* This is not a device on the PCI-core bridge. */
559 return -ENODEV;
560 }
561 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
562 pci_ops);
563
564 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
565
566 /* Fix up interrupt lines */
567 dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
568 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
569
570 return 0;
571}
572EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
573
574/* PCI device IRQ mapping. */
575int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
576{
577 struct bcma_drv_pci_host *pc_host;
578
579 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
580 /* This is not a device on the PCI-core bridge. */
581 return -ENODEV;
582 }
583
584 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
585 pci_ops);
586 return bcma_core_mips_irq(pc_host->pdev->core) + 2;
14} 587}
588EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
index 679d4cab4547..46c71e27d31f 100644
--- a/include/linux/bcma/bcma_driver_pci.h
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -160,9 +160,44 @@ struct pci_dev;
160/* PCIcore specific boardflags */ 160/* PCIcore specific boardflags */
161#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 161#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
162 162
163/* PCIE Config space accessing MACROS */
164#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
165#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
166#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
167#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
168
169#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
170#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
171#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
172#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
173
174/* PCIE Root Capability Register bits (Host mode only) */
175#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
176
177struct bcma_drv_pci;
178
179#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
180struct bcma_drv_pci_host {
181 struct bcma_drv_pci *pdev;
182
183 u32 host_cfg_addr;
184 spinlock_t cfgspace_lock;
185
186 struct pci_controller pci_controller;
187 struct pci_ops pci_ops;
188 struct resource mem_resource;
189 struct resource io_resource;
190};
191#endif
192
163struct bcma_drv_pci { 193struct bcma_drv_pci {
164 struct bcma_device *core; 194 struct bcma_device *core;
165 u8 setup_done:1; 195 u8 setup_done:1;
196 u8 hostmode:1;
197
198#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
199 struct bcma_drv_pci_host *host_controller;
200#endif
166}; 201};
167 202
168/* Register access */ 203/* Register access */
@@ -173,4 +208,7 @@ extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
173extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, 208extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
174 struct bcma_device *core, bool enable); 209 struct bcma_device *core, bool enable);
175 210
211extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
212extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
213
176#endif /* LINUX_BCMA_DRIVER_PCI_H_ */ 214#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
index 9faae2ae02e8..5a71d5719640 100644
--- a/include/linux/bcma/bcma_regs.h
+++ b/include/linux/bcma/bcma_regs.h
@@ -56,4 +56,31 @@
56#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ 56#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
57#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ 57#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
58 58
59/* SiliconBackplane Address Map.
60 * All regions may not exist on all chips.
61 */
62#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
63#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
64#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
65#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
66#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
67#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
68
69
70#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
71#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
72#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
73#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
74 * (2 ZettaBytes), low 32 bits
75 */
76#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
77 * (2 ZettaBytes), high 32 bits
78 */
79
80#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
81#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
82#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
83 * (2 ZettaBytes), high 32 bits
84 */
85
59#endif /* LINUX_BCMA_REGS_H_ */ 86#endif /* LINUX_BCMA_REGS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 14:00:18 -0500