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authorSascha Hauer <s.hauer@pengutronix.de>2009-05-27 12:26:51 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2009-08-07 06:11:10 -0400
commit494f22dddc6308b9c35984118ff4cb1681ad8e48 (patch)
treeab25d0a6c119e18e899456ba4142c8641d775760
parent8afaada2dc9247ffcd2982be824cd290ace18f55 (diff)
MXC gpio interrupt support: move register definitions to .c file
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/plat-mxc/gpio.c17
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h14
4 files changed, 17 insertions, 42 deletions
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index b70715720350..f0315edb3eb9 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
29static struct mxc_gpio_port *mxc_gpio_ports; 29static struct mxc_gpio_port *mxc_gpio_ports;
30static int gpio_table_size; 30static int gpio_table_size;
31 31
32#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
33
34#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
35#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
36#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
37#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47#define GPIO_INT_NONE 0x4
48
32/* Note: This driver assumes 32 GPIOs are handled in one register */ 49/* Note: This driver assumes 32 GPIOs are handled in one register */
33 50
34static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) 51static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index ee60d64728c9..1b2890a5c452 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -134,20 +134,6 @@
134#define GPIO_INT_PORTD 62 134#define GPIO_INT_PORTD 62
135#define WDT_INT 63 135#define WDT_INT 63
136 136
137/* gpio and gpio based interrupt handling */
138#define GPIO_DR 0x1C
139#define GPIO_GDIR 0x00
140#define GPIO_PSR 0x24
141#define GPIO_ICR1 0x28
142#define GPIO_ICR2 0x2C
143#define GPIO_IMR 0x30
144#define GPIO_ISR 0x34
145#define GPIO_INT_LOW_LEV 0x3
146#define GPIO_INT_HIGH_LEV 0x2
147#define GPIO_INT_RISE_EDGE 0x0
148#define GPIO_INT_FALL_EDGE 0x1
149#define GPIO_INT_NONE 0x4
150
151/* DMA */ 137/* DMA */
152#define DMA_REQ_UART3_T 2 138#define DMA_REQ_UART3_T 2
153#define DMA_REQ_UART3_R 3 139#define DMA_REQ_UART3_R 3
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index 5982ae5a00d9..db5d921e0fe6 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -150,20 +150,6 @@
150#define MXC_INT_GPIO 8 150#define MXC_INT_GPIO 8
151#define MXC_INT_CSPI3 6 151#define MXC_INT_CSPI3 6
152 152
153/* gpio and gpio based interrupt handling */
154#define GPIO_DR 0x1C
155#define GPIO_GDIR 0x00
156#define GPIO_PSR 0x24
157#define GPIO_ICR1 0x28
158#define GPIO_ICR2 0x2C
159#define GPIO_IMR 0x30
160#define GPIO_ISR 0x34
161#define GPIO_INT_LOW_LEV 0x3
162#define GPIO_INT_HIGH_LEV 0x2
163#define GPIO_INT_RISE_EDGE 0x0
164#define GPIO_INT_FALL_EDGE 0x1
165#define GPIO_INT_NONE 0x4
166
167/* fixed DMA request numbers */ 153/* fixed DMA request numbers */
168#define DMA_REQ_CSI_RX 31 154#define DMA_REQ_CSI_RX 31
169#define DMA_REQ_CSI_STAT 30 155#define DMA_REQ_CSI_STAT 30
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 16f68e8f4cf2..009f4440276b 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -259,20 +259,6 @@
259#define SYSTEM_REV_MIN CHIP_REV_1_0 259#define SYSTEM_REV_MIN CHIP_REV_1_0
260#define SYSTEM_REV_NUM 3 260#define SYSTEM_REV_NUM 3
261 261
262/* gpio and gpio based interrupt handling */
263#define GPIO_DR 0x00
264#define GPIO_GDIR 0x04
265#define GPIO_PSR 0x08
266#define GPIO_ICR1 0x0C
267#define GPIO_ICR2 0x10
268#define GPIO_IMR 0x14
269#define GPIO_ISR 0x18
270#define GPIO_INT_LOW_LEV 0x0
271#define GPIO_INT_HIGH_LEV 0x1
272#define GPIO_INT_RISE_EDGE 0x2
273#define GPIO_INT_FALL_EDGE 0x3
274#define GPIO_INT_NONE 0x4
275
276/* Mandatory defines used globally */ 262/* Mandatory defines used globally */
277 263
278#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 264#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)