diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-03-18 14:32:08 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-03-18 14:32:08 -0400 |
commit | 4907cdca7210c5895311bddcf05a4c85b67d8566 (patch) | |
tree | 64d3f2f0b019bb514425fa27b9aa3ec13cddf61f | |
parent | 9a15c944f76cffa5581959cefe709c7c4ea26994 (diff) | |
parent | e724f080f5dd03881bc6d378750c37f7374cae7e (diff) |
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull another kvm fix from Paolo Bonzini:
"A fix for a PowerPC bug that was introduced during the 3.14 merge
window"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: PPC: Book3S HV: Fix register usage when loading/saving VRSAVE
KVM: PPC: Book3S HV: Remove bogus duplicate code
-rw-r--r-- | arch/powerpc/kvm/book3s_hv_rmhandlers.S | 71 |
1 files changed, 2 insertions, 69 deletions
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index e66d4ec04d95..818dce344e82 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S | |||
@@ -1504,73 +1504,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |||
1504 | 1: addi r8,r8,16 | 1504 | 1: addi r8,r8,16 |
1505 | .endr | 1505 | .endr |
1506 | 1506 | ||
1507 | /* Save DEC */ | ||
1508 | mfspr r5,SPRN_DEC | ||
1509 | mftb r6 | ||
1510 | extsw r5,r5 | ||
1511 | add r5,r5,r6 | ||
1512 | std r5,VCPU_DEC_EXPIRES(r9) | ||
1513 | |||
1514 | BEGIN_FTR_SECTION | ||
1515 | b 8f | ||
1516 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | ||
1517 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ | ||
1518 | mfmsr r8 | ||
1519 | li r0, 1 | ||
1520 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | ||
1521 | mtmsrd r8 | ||
1522 | |||
1523 | /* Save POWER8-specific registers */ | ||
1524 | mfspr r5, SPRN_IAMR | ||
1525 | mfspr r6, SPRN_PSPB | ||
1526 | mfspr r7, SPRN_FSCR | ||
1527 | std r5, VCPU_IAMR(r9) | ||
1528 | stw r6, VCPU_PSPB(r9) | ||
1529 | std r7, VCPU_FSCR(r9) | ||
1530 | mfspr r5, SPRN_IC | ||
1531 | mfspr r6, SPRN_VTB | ||
1532 | mfspr r7, SPRN_TAR | ||
1533 | std r5, VCPU_IC(r9) | ||
1534 | std r6, VCPU_VTB(r9) | ||
1535 | std r7, VCPU_TAR(r9) | ||
1536 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | ||
1537 | mfspr r5, SPRN_TFHAR | ||
1538 | mfspr r6, SPRN_TFIAR | ||
1539 | mfspr r7, SPRN_TEXASR | ||
1540 | std r5, VCPU_TFHAR(r9) | ||
1541 | std r6, VCPU_TFIAR(r9) | ||
1542 | std r7, VCPU_TEXASR(r9) | ||
1543 | #endif | ||
1544 | mfspr r8, SPRN_EBBHR | ||
1545 | std r8, VCPU_EBBHR(r9) | ||
1546 | mfspr r5, SPRN_EBBRR | ||
1547 | mfspr r6, SPRN_BESCR | ||
1548 | mfspr r7, SPRN_CSIGR | ||
1549 | mfspr r8, SPRN_TACR | ||
1550 | std r5, VCPU_EBBRR(r9) | ||
1551 | std r6, VCPU_BESCR(r9) | ||
1552 | std r7, VCPU_CSIGR(r9) | ||
1553 | std r8, VCPU_TACR(r9) | ||
1554 | mfspr r5, SPRN_TCSCR | ||
1555 | mfspr r6, SPRN_ACOP | ||
1556 | mfspr r7, SPRN_PID | ||
1557 | mfspr r8, SPRN_WORT | ||
1558 | std r5, VCPU_TCSCR(r9) | ||
1559 | std r6, VCPU_ACOP(r9) | ||
1560 | stw r7, VCPU_GUEST_PID(r9) | ||
1561 | std r8, VCPU_WORT(r9) | ||
1562 | 8: | ||
1563 | |||
1564 | /* Save and reset AMR and UAMOR before turning on the MMU */ | ||
1565 | BEGIN_FTR_SECTION | ||
1566 | mfspr r5,SPRN_AMR | ||
1567 | mfspr r6,SPRN_UAMOR | ||
1568 | std r5,VCPU_AMR(r9) | ||
1569 | std r6,VCPU_UAMOR(r9) | ||
1570 | li r6,0 | ||
1571 | mtspr SPRN_AMR,r6 | ||
1572 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | ||
1573 | |||
1574 | /* Unset guest mode */ | 1507 | /* Unset guest mode */ |
1575 | li r0, KVM_GUEST_MODE_NONE | 1508 | li r0, KVM_GUEST_MODE_NONE |
1576 | stb r0, HSTATE_IN_GUEST(r13) | 1509 | stb r0, HSTATE_IN_GUEST(r13) |
@@ -2203,7 +2136,7 @@ BEGIN_FTR_SECTION | |||
2203 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | 2136 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2204 | #endif | 2137 | #endif |
2205 | mfspr r6,SPRN_VRSAVE | 2138 | mfspr r6,SPRN_VRSAVE |
2206 | stw r6,VCPU_VRSAVE(r3) | 2139 | stw r6,VCPU_VRSAVE(r31) |
2207 | mtlr r30 | 2140 | mtlr r30 |
2208 | mtmsrd r5 | 2141 | mtmsrd r5 |
2209 | isync | 2142 | isync |
@@ -2240,7 +2173,7 @@ BEGIN_FTR_SECTION | |||
2240 | bl .load_vr_state | 2173 | bl .load_vr_state |
2241 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | 2174 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2242 | #endif | 2175 | #endif |
2243 | lwz r7,VCPU_VRSAVE(r4) | 2176 | lwz r7,VCPU_VRSAVE(r31) |
2244 | mtspr SPRN_VRSAVE,r7 | 2177 | mtspr SPRN_VRSAVE,r7 |
2245 | mtlr r30 | 2178 | mtlr r30 |
2246 | mr r4,r31 | 2179 | mr r4,r31 |