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authorAfzal Mohammed <afzal@ti.com>2012-09-29 08:50:11 -0400
committerAfzal Mohammed <afzal@ti.com>2012-10-15 05:12:07 -0400
commit47f88af4ed80ac9ca593543e21ebf86a31d7e8ba (patch)
treefca2f25ddd390f1866549eba5bd9cc1502c4cef0
parentbc3668ea046be9e841eecfab04bddfa759e765d6 (diff)
mtd: nand: omap: bring in gpmc nand macros
Bring onto driver the macros defined in gpmc.h that are not necessary outside driver, helps in removing inclusion of gpmc.h too. Also remove GPMC prefix on those macros to make clear it's independence with gpmc header. Signed-off-by: Afzal Mohammed <afzal@ti.com>
-rw-r--r--drivers/mtd/nand/omap2.c21
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index abfc602c4cfc..f0a1b1d69d32 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -110,6 +110,11 @@
110#define ECC1RESULTSIZE 0x1 110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100 111#define ECCCLEAR 0x100
112#define ECC1 0x1 112#define ECC1 0x1
113#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117#define STATUS_BUFF_EMPTY 0x00000001
113 118
114/* oob info generated runtime depending on ecc algorithm and layout selected */ 119/* oob info generated runtime depending on ecc algorithm and layout selected */
115static struct nand_ecclayout omap_oobinfo; 120static struct nand_ecclayout omap_oobinfo;
@@ -269,7 +274,7 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
269 /* wait until buffer is available for write */ 274 /* wait until buffer is available for write */
270 do { 275 do {
271 status = readl(info->reg.gpmc_status) & 276 status = readl(info->reg.gpmc_status) &
272 GPMC_STATUS_BUFF_EMPTY; 277 STATUS_BUFF_EMPTY;
273 } while (!status); 278 } while (!status);
274 } 279 }
275} 280}
@@ -307,7 +312,7 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
307 /* wait until buffer is available for write */ 312 /* wait until buffer is available for write */
308 do { 313 do {
309 status = readl(info->reg.gpmc_status) & 314 status = readl(info->reg.gpmc_status) &
310 GPMC_STATUS_BUFF_EMPTY; 315 STATUS_BUFF_EMPTY;
311 } while (!status); 316 } while (!status);
312 } 317 }
313} 318}
@@ -348,7 +353,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
348 } else { 353 } else {
349 do { 354 do {
350 r_count = readl(info->reg.gpmc_prefetch_status); 355 r_count = readl(info->reg.gpmc_prefetch_status);
351 r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count); 356 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
352 r_count = r_count >> 2; 357 r_count = r_count >> 2;
353 ioread32_rep(info->nand.IO_ADDR_R, p, r_count); 358 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
354 p += r_count; 359 p += r_count;
@@ -395,7 +400,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
395 } else { 400 } else {
396 while (len) { 401 while (len) {
397 w_count = readl(info->reg.gpmc_prefetch_status); 402 w_count = readl(info->reg.gpmc_prefetch_status);
398 w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count); 403 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
399 w_count = w_count >> 1; 404 w_count = w_count >> 1;
400 for (i = 0; (i < w_count) && len; i++, len -= 2) 405 for (i = 0; (i < w_count) && len; i++, len -= 2)
401 iowrite16(*p++, info->nand.IO_ADDR_W); 406 iowrite16(*p++, info->nand.IO_ADDR_W);
@@ -407,7 +412,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
407 do { 412 do {
408 cpu_relax(); 413 cpu_relax();
409 val = readl(info->reg.gpmc_prefetch_status); 414 val = readl(info->reg.gpmc_prefetch_status);
410 val = GPMC_PREFETCH_STATUS_COUNT(val); 415 val = PREFETCH_STATUS_COUNT(val);
411 } while (val && (tim++ < limit)); 416 } while (val && (tim++ < limit));
412 417
413 /* disable and stop the PFPW engine */ 418 /* disable and stop the PFPW engine */
@@ -493,7 +498,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
493 do { 498 do {
494 cpu_relax(); 499 cpu_relax();
495 val = readl(info->reg.gpmc_prefetch_status); 500 val = readl(info->reg.gpmc_prefetch_status);
496 val = GPMC_PREFETCH_STATUS_COUNT(val); 501 val = PREFETCH_STATUS_COUNT(val);
497 } while (val && (tim++ < limit)); 502 } while (val && (tim++ < limit));
498 503
499 /* disable and stop the PFPW engine */ 504 /* disable and stop the PFPW engine */
@@ -556,7 +561,7 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
556 u32 bytes; 561 u32 bytes;
557 562
558 bytes = readl(info->reg.gpmc_prefetch_status); 563 bytes = readl(info->reg.gpmc_prefetch_status);
559 bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes); 564 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
560 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ 565 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
561 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ 566 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
562 if (this_irq == info->gpmc_irq_count) 567 if (this_irq == info->gpmc_irq_count)
@@ -682,7 +687,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
682 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 687 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
683 do { 688 do {
684 val = readl(info->reg.gpmc_prefetch_status); 689 val = readl(info->reg.gpmc_prefetch_status);
685 val = GPMC_PREFETCH_STATUS_COUNT(val); 690 val = PREFETCH_STATUS_COUNT(val);
686 cpu_relax(); 691 cpu_relax();
687 } while (val && (tim++ < limit)); 692 } while (val && (tim++ < limit));
688 693