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authorBrice Goglin <brice@myri.com>2006-08-31 01:55:24 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-09-26 20:43:52 -0400
commit46ff34633ed09f36ebc4b5c40ac37e592172df74 (patch)
treee5603dd4fe5f9331c99b2b6c61a26650509338e2
parentfe97064c2870e174a6ff4a93feb11a70c4b71cc5 (diff)
MSI: Rename PCI_CAP_ID_HT_IRQCONF into PCI_CAP_ID_HT
0x08 is the HT capability, while PCI_CAP_ID_HT_IRQCONF would be the subtype 0x80 that mpic_scan_ht_pic() uses. Rename PCI_CAP_ID_HT_IRQCONF into PCI_CAP_ID_HT. And by the way, use it in the ipath driver instead of defining its own HT_CAPABILITY_ID. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--arch/powerpc/sysdev/mpic.c2
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6110.c5
-rw-r--r--include/linux/pci_regs.h2
3 files changed, 4 insertions, 5 deletions
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index b604926401f5..723972bb5bd9 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -339,7 +339,7 @@ static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
339 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; 339 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
340 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { 340 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
341 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); 341 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
342 if (id == PCI_CAP_ID_HT_IRQCONF) { 342 if (id == PCI_CAP_ID_HT) {
343 id = readb(devbase + pos + 3); 343 id = readb(devbase + pos + 3);
344 if (id == 0x80) 344 if (id == 0x80)
345 break; 345 break;
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6110.c b/drivers/infiniband/hw/ipath/ipath_iba6110.c
index bf2455a6d562..5c9b509e40e4 100644
--- a/drivers/infiniband/hw/ipath/ipath_iba6110.c
+++ b/drivers/infiniband/hw/ipath/ipath_iba6110.c
@@ -742,7 +742,6 @@ static int ipath_setup_ht_reset(struct ipath_devdata *dd)
742 return 0; 742 return 0;
743} 743}
744 744
745#define HT_CAPABILITY_ID 0x08 /* HT capabilities not defined in kernel */
746#define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */ 745#define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
747#define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */ 746#define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
748 747
@@ -973,7 +972,7 @@ static int ipath_setup_ht_config(struct ipath_devdata *dd,
973 * do this early, before we ever enable errors or hardware errors, 972 * do this early, before we ever enable errors or hardware errors,
974 * mostly to avoid causing the chip to enter freeze mode. 973 * mostly to avoid causing the chip to enter freeze mode.
975 */ 974 */
976 pos = pci_find_capability(pdev, HT_CAPABILITY_ID); 975 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
977 if (!pos) { 976 if (!pos) {
978 ipath_dev_err(dd, "Couldn't find HyperTransport " 977 ipath_dev_err(dd, "Couldn't find HyperTransport "
979 "capability; no interrupts\n"); 978 "capability; no interrupts\n");
@@ -996,7 +995,7 @@ static int ipath_setup_ht_config(struct ipath_devdata *dd,
996 else if (cap_type == HT_INTR_DISC_CONFIG) 995 else if (cap_type == HT_INTR_DISC_CONFIG)
997 ihandler = set_int_handler(dd, pdev, pos); 996 ihandler = set_int_handler(dd, pdev, pos);
998 } while ((pos = pci_find_next_capability(pdev, pos, 997 } while ((pos = pci_find_next_capability(pdev, pos,
999 HT_CAPABILITY_ID))); 998 PCI_CAP_ID_HT)));
1000 999
1001 if (!ihandler) { 1000 if (!ihandler) {
1002 ipath_dev_err(dd, "Couldn't find interrupt handler in " 1001 ipath_dev_err(dd, "Couldn't find interrupt handler in "
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 96930cb5927c..7d0e26cba420 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -196,7 +196,7 @@
196#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 196#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
197#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 197#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
198#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 198#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
199#define PCI_CAP_ID_HT_IRQCONF 0x08 /* HyperTransport IRQ Configuration */ 199#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
200#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ 200#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */
201#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 201#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
202#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 202#define PCI_CAP_ID_EXP 0x10 /* PCI Express */