dmaengine: dw: move private definitions to regs.h

Since we don't allow user to set registers directly through private slave
configuration we may move definitions to the regs.h because they are not used
anywhere except core.c part.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

2 files changed, 29 insertions, 34 deletions

diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 00d27a9d9c27..e8f92b28ffc2 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -11,7 +11,6 @@
 
 #include <linux/interrupt.h>
 #include <linux/dmaengine.h>
-#include <linux/platform_data/dma-dw.h>
 
 #define DW_DMA_MAX_NR_CHANNELS  8
 #define DW_DMA_MAX_NR_REQUESTS  16
@@ -132,6 +131,18 @@ struct dw_dma_regs {
 /* Bitfields in DWC_PARAMS */
 #define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
 
+/* bursts size */
+enum dw_dma_msize {
+        DW_DMA_MSIZE_1,
+        DW_DMA_MSIZE_4,
+        DW_DMA_MSIZE_8,
+        DW_DMA_MSIZE_16,
+        DW_DMA_MSIZE_32,
+        DW_DMA_MSIZE_64,
+        DW_DMA_MSIZE_128,
+        DW_DMA_MSIZE_256,
+};
+
 /* Bitfields in CTL_LO */
 #define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 #define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
@@ -161,20 +172,35 @@ struct dw_dma_regs {
 #define DWC_CTLH_DONE           0x00001000
 #define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 
-/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/platform_data/dma-dw.h> */
+/* Bitfields in CFG_LO */
 #define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
 #define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 #define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 #define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 #define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
 #define DWC_CFGL_HS_SRC         (1 << 11)       /* handshake w/src */
+#define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
+#define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
+#define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
+#define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
+#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
+#define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
+#define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
+#define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
+#define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
+#define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
 #define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
 #define DWC_CFGL_RELOAD_SAR     (1 << 30)
 #define DWC_CFGL_RELOAD_DAR     (1 << 31)
 
-/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/platform_data/dma-dw.h> */
+/* Bitfields in CFG_HI */
+#define DWC_CFGH_FCMODE         (1 << 0)
+#define DWC_CFGH_FIFO_MODE      (1 << 1)
+#define DWC_CFGH_PROTCTL(x)     ((x) << 2)
 #define DWC_CFGH_DS_UPD_EN      (1 << 5)
 #define DWC_CFGH_SS_UPD_EN      (1 << 6)
+#define DWC_CFGH_SRC_PER(x)     ((x) << 7)
+#define DWC_CFGH_DST_PER(x)     ((x) << 11)
 
 /* Bitfields in SGR */
 #define DWC_SGR_SGI(x)          ((x) << 0)
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index bc411a1bf8e7..d0c97da66e22 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -56,37 +56,6 @@ struct dw_dma_platform_data {
         unsigned char   data_width[4];
 };
 
-/* bursts size */
-enum dw_dma_msize {
-        DW_DMA_MSIZE_1,
-        DW_DMA_MSIZE_4,
-        DW_DMA_MSIZE_8,
-        DW_DMA_MSIZE_16,
-        DW_DMA_MSIZE_32,
-        DW_DMA_MSIZE_64,
-        DW_DMA_MSIZE_128,
-        DW_DMA_MSIZE_256,
-};
-
-/* Platform-configurable bits in CFG_HI */
-#define DWC_CFGH_FCMODE         (1 << 0)
-#define DWC_CFGH_FIFO_MODE      (1 << 1)
-#define DWC_CFGH_PROTCTL(x)     ((x) << 2)
-#define DWC_CFGH_SRC_PER(x)     ((x) << 7)
-#define DWC_CFGH_DST_PER(x)     ((x) << 11)
-
-/* Platform-configurable bits in CFG_LO */
-#define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
-#define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
-#define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
-#define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
-#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
-#define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
-#define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
-#define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
-#define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
-#define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
-
 /* DMA API extensions */
 struct dw_cyclic_desc {
         struct dw_desc  **desc;