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authorJeff Garzik <jeff@garzik.org>2006-11-14 14:46:17 -0500
committerJeff Garzik <jeff@garzik.org>2006-12-01 22:46:00 -0500
commit46b027cc30b6f6571191826afc718fa942403fc8 (patch)
tree02cd18fd614ca42f553f1a2fab4a4893c5ad0143
parentd25614bad6eec8fb80f3ef5bffbf720ebb7d2412 (diff)
[libata] sata_promise: fix TBG mode register offset
Fixes crashes on sparc, and may correct weird behavior reported on occasions, because we were never programming this register correctly (or at all). Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/ata/sata_promise.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 72eda5160fad..9c4389b5689a 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -46,15 +46,14 @@
46#include "sata_promise.h" 46#include "sata_promise.h"
47 47
48#define DRV_NAME "sata_promise" 48#define DRV_NAME "sata_promise"
49#define DRV_VERSION "1.04" 49#define DRV_VERSION "1.05"
50 50
51 51
52enum { 52enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */ 55 PDC_TBG_MODE = 0x41C, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */ 56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 57 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 58 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */