diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-07-04 11:54:40 -0400 |
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committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-07-04 11:54:40 -0400 |
commit | 469bb638dc2a6ea87ea56256f25cc964deb3cf2b (patch) | |
tree | 882c6a76805a4f705d5a29ff58c71f93ede4b395 | |
parent | b5f9cfed12dc639cce5a8b6e741352980e05a8a9 (diff) | |
parent | 8e9ddf811ba021506d2316fcfe619faa0ab3f567 (diff) |
Merge branch 'for-3.0' into for-3.1
-rw-r--r-- | sound/soc/codecs/wm8994.c | 2 | ||||
-rw-r--r-- | sound/soc/tegra/tegra_i2s.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index dc2350e6350b..70a68fd96c46 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c | |||
@@ -1713,6 +1713,8 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, | |||
1713 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | 1713 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, |
1714 | WM8994_FLL1_ENA | WM8994_FLL1_FRAC, | 1714 | WM8994_FLL1_ENA | WM8994_FLL1_FRAC, |
1715 | reg); | 1715 | reg); |
1716 | |||
1717 | msleep(5); | ||
1716 | } | 1718 | } |
1717 | 1719 | ||
1718 | wm8994->fll[id].in = freq_in; | 1720 | wm8994->fll[id].in = freq_in; |
diff --git a/sound/soc/tegra/tegra_i2s.c b/sound/soc/tegra/tegra_i2s.c index 2e5685512db0..f36b9969cfec 100644 --- a/sound/soc/tegra/tegra_i2s.c +++ b/sound/soc/tegra/tegra_i2s.c | |||
@@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, | |||
222 | if (i2sclock % (2 * srate)) | 222 | if (i2sclock % (2 * srate)) |
223 | reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; | 223 | reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; |
224 | 224 | ||
225 | if (!i2s->clk_refs) | ||
226 | clk_enable(i2s->clk_i2s); | ||
227 | |||
225 | tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); | 228 | tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); |
226 | 229 | ||
227 | tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, | 230 | tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, |
228 | TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | | 231 | TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | |
229 | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); | 232 | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); |
230 | 233 | ||
234 | if (!i2s->clk_refs) | ||
235 | clk_disable(i2s->clk_i2s); | ||
236 | |||
231 | return 0; | 237 | return 0; |
232 | } | 238 | } |
233 | 239 | ||