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authorTony Luck <tony.luck@intel.com>2012-08-09 13:59:21 -0400
committerTony Luck <tony.luck@intel.com>2012-08-09 13:59:21 -0400
commit4670a300a2169e1e922593c5d35b0cdaee112901 (patch)
tree1cc4036d6c2a6689e1f3fbb580327f78c58469a1
parent1a65f970d10ace7a1e399f9061a65679c0ae57d0 (diff)
x86/mce: Make cmci_discover() quiet
cmci_discover() works out which machine check banks support CMCI, and which of those are shared by multiple logical processors. It uses this information to ensure that exactly one cpu is designated the owner of each bank so that when interrupts are broadcast to multiple cpus, only one of them will look in a shared bank to log the error and clear the bank. At boot time cmci_discover() performs this task silently. But during certain cpu hotplug operations it prints out a set of summary lines like this: CPU 35 MCA banks CMCI:0 CMCI:1 CMCI:3 CMCI:5 CMCI:6 CMCI:7 CMCI:8 CMCI:9 CMCI:10 CMCI:11 CPU 1 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 39 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 38 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 32 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 37 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 36 MCA banks CMCI:0 CMCI:1 CMCI:3 CPU 34 MCA banks CMCI:0 CMCI:1 CMCI:3 The value of these messages seems very low. A user might painstakingly cross-check against the data sheet for a processor to ensure that all CMCI supported banks are correctly reported, but this seems improbable. If users really wanted to do this, we should print the information at boot time too. Remove the messages. Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel.c25
1 files changed, 6 insertions, 19 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 38e49bc95ffc..59648e48a145 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -65,24 +65,15 @@ static void intel_threshold_interrupt(void)
65 mce_notify_irq(); 65 mce_notify_irq();
66} 66}
67 67
68static void print_update(char *type, int *hdr, int num)
69{
70 if (*hdr == 0)
71 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
72 *hdr = 1;
73 printk(KERN_CONT " %s:%d", type, num);
74}
75
76/* 68/*
77 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks 69 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
78 * on this CPU. Use the algorithm recommended in the SDM to discover shared 70 * on this CPU. Use the algorithm recommended in the SDM to discover shared
79 * banks. 71 * banks.
80 */ 72 */
81static void cmci_discover(int banks, int boot) 73static void cmci_discover(int banks)
82{ 74{
83 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); 75 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
84 unsigned long flags; 76 unsigned long flags;
85 int hdr = 0;
86 int i; 77 int i;
87 78
88 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 79 raw_spin_lock_irqsave(&cmci_discover_lock, flags);
@@ -96,8 +87,7 @@ static void cmci_discover(int banks, int boot)
96 87
97 /* Already owned by someone else? */ 88 /* Already owned by someone else? */
98 if (val & MCI_CTL2_CMCI_EN) { 89 if (val & MCI_CTL2_CMCI_EN) {
99 if (test_and_clear_bit(i, owned) && !boot) 90 clear_bit(i, owned);
100 print_update("SHD", &hdr, i);
101 __clear_bit(i, __get_cpu_var(mce_poll_banks)); 91 __clear_bit(i, __get_cpu_var(mce_poll_banks));
102 continue; 92 continue;
103 } 93 }
@@ -109,16 +99,13 @@ static void cmci_discover(int banks, int boot)
109 99
110 /* Did the enable bit stick? -- the bank supports CMCI */ 100 /* Did the enable bit stick? -- the bank supports CMCI */
111 if (val & MCI_CTL2_CMCI_EN) { 101 if (val & MCI_CTL2_CMCI_EN) {
112 if (!test_and_set_bit(i, owned) && !boot) 102 set_bit(i, owned);
113 print_update("CMCI", &hdr, i);
114 __clear_bit(i, __get_cpu_var(mce_poll_banks)); 103 __clear_bit(i, __get_cpu_var(mce_poll_banks));
115 } else { 104 } else {
116 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); 105 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
117 } 106 }
118 } 107 }
119 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 108 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
120 if (hdr)
121 printk(KERN_CONT "\n");
122} 109}
123 110
124/* 111/*
@@ -186,7 +173,7 @@ void cmci_rediscover(int dying)
186 continue; 173 continue;
187 /* Recheck banks in case CPUs don't all have the same */ 174 /* Recheck banks in case CPUs don't all have the same */
188 if (cmci_supported(&banks)) 175 if (cmci_supported(&banks))
189 cmci_discover(banks, 0); 176 cmci_discover(banks);
190 } 177 }
191 178
192 set_cpus_allowed_ptr(current, old); 179 set_cpus_allowed_ptr(current, old);
@@ -200,7 +187,7 @@ void cmci_reenable(void)
200{ 187{
201 int banks; 188 int banks;
202 if (cmci_supported(&banks)) 189 if (cmci_supported(&banks))
203 cmci_discover(banks, 0); 190 cmci_discover(banks);
204} 191}
205 192
206static void intel_init_cmci(void) 193static void intel_init_cmci(void)
@@ -211,7 +198,7 @@ static void intel_init_cmci(void)
211 return; 198 return;
212 199
213 mce_threshold_vector = intel_threshold_interrupt; 200 mce_threshold_vector = intel_threshold_interrupt;
214 cmci_discover(banks, 1); 201 cmci_discover(banks);
215 /* 202 /*
216 * For CPU #0 this runs with still disabled APIC, but that's 203 * For CPU #0 this runs with still disabled APIC, but that's
217 * ok because only the vector is set up. We still do another 204 * ok because only the vector is set up. We still do another