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authorAndy Walls <awalls@radix.net>2008-08-29 15:10:21 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-10-12 07:36:58 -0400
commit4519064c1c7ccdd319d26181bdd12ee2df6e336e (patch)
treef350c218d9f8ac1b5fc4fd4a863f1409b7ea69fc
parent0be01004ddc0694d8c592fff05ab88dabd45f476 (diff)
V4L/DVB (8912): cx18: Correct CX23418 PCI configuration settings.
cx18: Correct CX23418 PCI configuration settings. The CX23418 doesn't have I/O space registers, so there was no need to try and turn them on (the card ignores the attempt to set the bit anyway). Also removed incorrect config space register setting that was errantly borrowed from ivtv. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/media/video/cx18/cx18-driver.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 3419de9a5a4e..3dfceb360b50 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -511,9 +511,9 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *dev,
511 return -EIO; 511 return -EIO;
512 } 512 }
513 513
514 /* Check for bus mastering */ 514 /* Enable bus mastering and memory mapped IO for the CX23418 */
515 pci_read_config_word(dev, PCI_COMMAND, &cmd); 515 pci_read_config_word(dev, PCI_COMMAND, &cmd);
516 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 516 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
517 pci_write_config_word(dev, PCI_COMMAND, cmd); 517 pci_write_config_word(dev, PCI_COMMAND, cmd);
518 518
519 pci_read_config_byte(dev, PCI_CLASS_REVISION, &cx->card_rev); 519 pci_read_config_byte(dev, PCI_CLASS_REVISION, &cx->card_rev);
@@ -525,11 +525,6 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *dev,
525 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 525 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
526 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &pci_latency); 526 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &pci_latency);
527 } 527 }
528 /* This config space value relates to DMA latencies. The
529 default value 0x8080 is too low however and will lead
530 to DMA errors. 0xffff is the max value which solves
531 these problems. */
532 pci_write_config_dword(dev, 0x40, 0xffff);
533 528
534 CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, " 529 CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, "
535 "irq: %d, latency: %d, memory: 0x%lx\n", 530 "irq: %d, latency: %d, memory: 0x%lx\n",