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authorIlia Mirkin <imirkin@alum.mit.edu>2013-06-27 00:08:22 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-06-30 23:50:48 -0400
commit44b1e3bd6adc050fac1daccee5bbff019daadc8e (patch)
tree0f7d60b1da7aa19af37ecbbf2661423d2b9a5032
parent0d4a1450c95801c21ba4db109303fbad62378b91 (diff)
drm/nouveau/core: xtensa engine base class implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/xtensa.c170
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/xtensa.h38
3 files changed, 209 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 78f9aa24f1fd..b59cfd79bd79 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -142,6 +142,7 @@ nouveau-y += core/subdev/vm/nv50.o
142nouveau-y += core/subdev/vm/nvc0.o 142nouveau-y += core/subdev/vm/nvc0.o
143 143
144nouveau-y += core/engine/falcon.o 144nouveau-y += core/engine/falcon.o
145nouveau-y += core/engine/xtensa.o
145nouveau-y += core/engine/dmaobj/base.o 146nouveau-y += core/engine/dmaobj/base.o
146nouveau-y += core/engine/dmaobj/nv04.o 147nouveau-y += core/engine/dmaobj/nv04.o
147nouveau-y += core/engine/dmaobj/nv50.o 148nouveau-y += core/engine/dmaobj/nv50.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c
new file mode 100644
index 000000000000..0639bc59d0a5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/xtensa.c
@@ -0,0 +1,170 @@
1/*
2 * Copyright 2013 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <engine/xtensa.h>
24
25u32
26_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr)
27{
28 struct nouveau_xtensa *xtensa = (void *)object;
29 return nv_rd32(xtensa, xtensa->addr + addr);
30}
31
32void
33_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data)
34{
35 struct nouveau_xtensa *xtensa = (void *)object;
36 nv_wr32(xtensa, xtensa->addr + addr, data);
37}
38
39int
40_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent,
41 struct nouveau_object *engine,
42 struct nouveau_oclass *oclass, void *data, u32 size,
43 struct nouveau_object **pobject)
44{
45 struct nouveau_engctx *engctx;
46 int ret;
47
48 ret = nouveau_engctx_create(parent, engine, oclass, NULL,
49 0x10000, 0x1000,
50 NVOBJ_FLAG_ZERO_ALLOC, &engctx);
51 *pobject = nv_object(engctx);
52 return ret;
53}
54
55void
56_nouveau_xtensa_intr(struct nouveau_subdev *subdev)
57{
58 struct nouveau_xtensa *xtensa = (void *)subdev;
59 u32 unk104 = nv_ro32(xtensa, 0xd04);
60 u32 intr = nv_ro32(xtensa, 0xc20);
61 u32 chan = nv_ro32(xtensa, 0xc28);
62 u32 unk10c = nv_ro32(xtensa, 0xd0c);
63
64 if (intr & 0x10)
65 nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");
66 nv_wo32(xtensa, 0xc20, intr);
67 intr = nv_ro32(xtensa, 0xc20);
68 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
69 nv_debug(xtensa, "Enabling FIFO_CTRL\n");
70 nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
71 }
72}
73
74int
75nouveau_xtensa_create_(struct nouveau_object *parent,
76 struct nouveau_object *engine,
77 struct nouveau_oclass *oclass, u32 addr, bool enable,
78 const char *iname, const char *fname,
79 int length, void **pobject)
80{
81 struct nouveau_xtensa *xtensa;
82 int ret;
83
84 ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
85 fname, length, pobject);
86 xtensa = *pobject;
87 if (ret)
88 return ret;
89
90 nv_subdev(xtensa)->intr = _nouveau_xtensa_intr;
91
92 xtensa->addr = addr;
93
94 return 0;
95}
96
97int
98_nouveau_xtensa_init(struct nouveau_object *object)
99{
100 struct nouveau_device *device = nv_device(object);
101 struct nouveau_xtensa *xtensa = (void *)object;
102 const struct firmware *fw;
103 char name[32];
104 int i, ret;
105 u32 tmp;
106
107 ret = nouveau_engine_init(&xtensa->base);
108 if (ret)
109 return ret;
110
111 if (!xtensa->gpu_fw) {
112 snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
113 xtensa->addr >> 12);
114
115 ret = request_firmware(&fw, name, &device->pdev->dev);
116 if (ret) {
117 nv_warn(xtensa, "unable to load firmware %s\n", name);
118 return ret;
119 }
120
121 ret = nouveau_gpuobj_new(object, NULL, fw->size, 0x1000, 0,
122 &xtensa->gpu_fw);
123 if (ret) {
124 release_firmware(fw);
125 return ret;
126 }
127
128 nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",
129 xtensa->gpu_fw->addr);
130
131 for (i = 0; i < fw->size / 4; i++)
132 nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));
133 release_firmware(fw);
134 }
135
136 nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */
137 nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */
138
139 nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
140 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
141 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
142
143 nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
144 nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
145 nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
146
147 tmp = nv_rd32(xtensa, 0x0);
148 nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */
149
150 nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */
151
152 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
153 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
154
155 return 0;
156}
157
158int
159_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend)
160{
161 struct nouveau_xtensa *xtensa = (void *)object;
162
163 nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
164 nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
165
166 if (!suspend)
167 nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw);
168
169 return nouveau_engine_fini(&xtensa->base, suspend);
170}
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
new file mode 100644
index 000000000000..306100f31f02
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
@@ -0,0 +1,38 @@
1#ifndef __NOUVEAU_XTENSA_H__
2#define __NOUVEAU_XTENSA_H__
3
4#include <core/engine.h>
5#include <core/engctx.h>
6#include <core/gpuobj.h>
7
8struct nouveau_xtensa {
9 struct nouveau_engine base;
10
11 u32 addr;
12 struct nouveau_gpuobj *gpu_fw;
13 u32 fifo_val;
14 u32 unkd28;
15};
16
17#define nouveau_xtensa_create(p,e,c,b,d,i,f,r) \
18 nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \
19 sizeof(**r),(void **)r)
20
21int _nouveau_xtensa_engctx_ctor(struct nouveau_object *,
22 struct nouveau_object *,
23 struct nouveau_oclass *, void *, u32,
24 struct nouveau_object **);
25
26void _nouveau_xtensa_intr(struct nouveau_subdev *);
27int nouveau_xtensa_create_(struct nouveau_object *,
28 struct nouveau_object *,
29 struct nouveau_oclass *, u32, bool,
30 const char *, const char *,
31 int, void **);
32#define _nouveau_xtensa_dtor _nouveau_engine_dtor
33int _nouveau_xtensa_init(struct nouveau_object *);
34int _nouveau_xtensa_fini(struct nouveau_object *, bool);
35u32 _nouveau_xtensa_rd32(struct nouveau_object *, u64);
36void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32);
37
38#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 09:09:58 -0400