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authorBen Skeggs <bskeggs@redhat.com>2010-10-19 04:01:41 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-12-03 00:10:56 -0500
commit43ce028ff2b1df68c690f0af14a109288d3e9e86 (patch)
treeef037b1c317b21600a9a7331ec8873d2225b749d
parent1e96268aca1bb40f42bdbc9d2293b123b072f1de (diff)
drm/nv50: rework evo init to match nvidia more closely
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c73
1 files changed, 26 insertions, 47 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index dbad233e750f..d270f17a5310 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -149,60 +149,36 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
149static int 149static int
150nv50_evo_channel_init(struct nouveau_channel *evo) 150nv50_evo_channel_init(struct nouveau_channel *evo)
151{ 151{
152 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
153 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
154 struct drm_device *dev = evo->dev; 152 struct drm_device *dev = evo->dev;
155 int id = evo->id, ret, i; 153 int id = evo->id, ret, i;
156 u64 start; 154 u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
157 u32 tmp; 155 u32 tmp;
158 156
159 /* taken from nv bug #12637, attempts to un-wedge the hw if it's 157 tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
160 * stuck in some unspecified state 158 if ((tmp & 0x009f0000) == 0x00020000)
161 */ 159 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
162 start = ptimer->read(dev);
163 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x2b00);
164 while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))) & 0x1e0000) {
165 if ((tmp & 0x9f0000) == 0x20000)
166 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x800000);
167
168 if ((tmp & 0x3f0000) == 0x30000)
169 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x200000);
170
171 if (ptimer->read(dev) - start > 1000000000ULL) {
172 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
173 NV_ERROR(dev, "0x610200 = 0x%08x\n", tmp);
174 return -EBUSY;
175 }
176 }
177 160
178 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x1000b03); 161 tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
179 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 162 if ((tmp & 0x003f0000) == 0x00030000)
180 0x40000000, 0x40000000)) { 163 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
181 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
182 NV_ERROR(dev, "0x610200 = 0x%08x\n",
183 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
184 return -EBUSY;
185 }
186 164
187 /* initialise fifo */ 165 /* initialise fifo */
188 nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), 166 nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
189 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) | 167 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
190 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM | 168 NV50_PDISPLAY_EVO_DMA_CB_VALID);
191 NV50_PDISPLAY_EVO_DMA_CB_VALID);
192 nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000); 169 nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
193 nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id); 170 nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
171 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
172 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
173
174 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
175 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
176 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
194 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) { 177 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
195 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n"); 178 NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
196 NV_ERROR(dev, "0x610200 = 0x%08x\n",
197 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))); 179 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
198 return -EBUSY; 180 return -EBUSY;
199 } 181 }
200 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id),
201 (nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)) & ~0x00000003) |
202 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
203 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0);
204 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
205 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
206 182
207 /* enable error reporting on the channel */ 183 /* enable error reporting on the channel */
208 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id); 184 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
@@ -226,12 +202,15 @@ static void
226nv50_evo_channel_fini(struct nouveau_channel *evo) 202nv50_evo_channel_fini(struct nouveau_channel *evo)
227{ 203{
228 struct drm_device *dev = evo->dev; 204 struct drm_device *dev = evo->dev;
229 205 int id = evo->id;
230 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0); 206
231 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0x1e0000, 0)) { 207 nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
232 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n"); 208 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
233 NV_ERROR(dev, "0x610200 = 0x%08x\n", 209 nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
234 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id))); 210 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
211 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
212 NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
213 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
235 } 214 }
236} 215}
237 216