aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorStephane Eranian <eranian@hpl.hp.com>2006-12-06 20:14:01 -0500
committerAndi Kleen <andi@basil.nowhere.org>2006-12-06 20:14:01 -0500
commit42ed458aa51337357d7632c64aed4528f923e829 (patch)
tree7ac9aafa6d995bcca812c679fc56b2fd15ab8916
parentd7731c0ff69dc3f18ea020257e627dae4d214fdb (diff)
[PATCH] i386: i386 add X86_FEATURE_PEBS and detection
Here is a patch (used by perfmon2) to detect the presence of the Precise Event Based Sampling (PEBS) feature for i386. The patch also adds the cpu_has_pebs macro. - adds X86_FEATURE_PEBS - adds cpu_has_pebs to test for X86_FEATURE_PEBS Signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org>
-rw-r--r--arch/i386/kernel/cpu/intel.c8
-rw-r--r--include/asm-i386/cpufeature.h2
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 94a95aa5227e..798c2f617e87 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -195,8 +195,14 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
195 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 195 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
196 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 196 (c->x86 == 0x6 && c->x86_model >= 0x0e))
197 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); 197 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
198}
199 198
199 if (cpu_has_ds) {
200 unsigned int l1;
201 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
202 if (!(l1 & (1<<12)))
203 set_bit(X86_FEATURE_PEBS, c->x86_capability);
204 }
205}
200 206
201static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size) 207static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
202{ 208{
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 69ce35049a07..231672558c1f 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -73,6 +73,7 @@
73#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 73#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
74#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ 74#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
75#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 75#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
76#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
76 77
77/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 78/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
78#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 79#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -135,6 +136,7 @@
135#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) 136#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
136#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) 137#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
137#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) 138#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
139#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
138 140
139#endif /* __ASM_I386_CPUFEATURE_H */ 141#endif /* __ASM_I386_CPUFEATURE_H */
140 142