diff options
author | Jiang Liu <jiang.liu@huawei.com> | 2012-07-24 05:20:15 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-08-23 12:11:12 -0400 |
commit | 424ffc943dbac747818b7e4698cdc50be91e4c25 (patch) | |
tree | c4731ebddca495f511cfd17a6c9e1d4fa5fee3de | |
parent | 39a3612e03440be5e2dbd02a5672cd4d1dd243c4 (diff) |
tile: PCI: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify Tile PCIe code.
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
-rw-r--r-- | arch/tile/kernel/pci.c | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 33c10864d2f7..d2292be6fb90 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c | |||
@@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void) | |||
246 | 246 | ||
247 | /* Scan for the smallest maximum payload size. */ | 247 | /* Scan for the smallest maximum payload size. */ |
248 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | 248 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { |
249 | int pcie_caps_offset; | ||
250 | u32 devcap; | 249 | u32 devcap; |
251 | int max_payload; | 250 | int max_payload; |
252 | 251 | ||
253 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | 252 | if (!pci_is_pcie(dev)) |
254 | if (pcie_caps_offset == 0) | ||
255 | continue; | 253 | continue; |
256 | 254 | ||
257 | pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP, | 255 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap); |
258 | &devcap); | ||
259 | max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; | 256 | max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; |
260 | if (max_payload < smallest_max_payload) | 257 | if (max_payload < smallest_max_payload) |
261 | smallest_max_payload = max_payload; | 258 | smallest_max_payload = max_payload; |
@@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void) | |||
263 | 260 | ||
264 | /* Now, set the max_payload_size for all devices to that value. */ | 261 | /* Now, set the max_payload_size for all devices to that value. */ |
265 | new_values = (max_read_size << 12) | (smallest_max_payload << 5); | 262 | new_values = (max_read_size << 12) | (smallest_max_payload << 5); |
266 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | 263 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) |
267 | int pcie_caps_offset; | 264 | pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
268 | u16 devctl; | 265 | PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ, |
269 | 266 | new_values); | |
270 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | ||
271 | if (pcie_caps_offset == 0) | ||
272 | continue; | ||
273 | |||
274 | pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | ||
275 | &devctl); | ||
276 | devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ); | ||
277 | devctl |= new_values; | ||
278 | pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | ||
279 | devctl); | ||
280 | } | ||
281 | } | 267 | } |
282 | 268 | ||
283 | 269 | ||