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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2010-11-19 02:23:52 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-11-24 01:34:04 -0500
commit421b446abeec55bed1251fab80cb5c12be58b773 (patch)
tree7c9b92368cf986b776f9ecf457683761a592a941
parentb16a2892b9852839307894cc429b7a7b145138a7 (diff)
ARM: mach-shmobile: clock-sh7372: remove bogus pllc2 clock toggling.
The PLLC2 clock was utilizing the same sort of enable/disable without regard to usecount approach that the FSIDIV clock was when being used as a PLL pass-through. This forces the enable/disable through the clock framework, which now prevents the clock from being ripped out or modified underneath users that have an existing handle on it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c5
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c12
2 files changed, 7 insertions, 10 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index e084b423146e..d440e5f456ad 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -969,6 +969,11 @@ static int __init hdmi_init_pm_clock(void)
969 goto out; 969 goto out;
970 } 970 }
971 971
972 ret = clk_enable(&sh7372_pllc2_clk);
973 if (ret < 0) {
974 pr_err("Cannot enable pllc2 clock\n");
975 goto out;
976 }
972 pr_debug("PLLC2 set frequency %lu\n", rate); 977 pr_debug("PLLC2 set frequency %lu\n", rate);
973 978
974 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); 979 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index cbeca2849918..e18a1241a95e 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -230,21 +230,13 @@ static int pllc2_set_rate(struct clk *clk,
230 if (idx < 0) 230 if (idx < 0)
231 return idx; 231 return idx;
232 232
233 if (rate == clk->parent->rate) { 233 if (rate == clk->parent->rate)
234 pllc2_disable(clk); 234 return -EINVAL;
235 return 0;
236 }
237 235
238 value = __raw_readl(PLLC2CR) & ~(0x3f << 24); 236 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
239 237
240 if (value & 0x80000000)
241 pllc2_disable(clk);
242
243 __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR); 238 __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
244 239
245 if (value & 0x80000000)
246 return pllc2_enable(clk);
247
248 return 0; 240 return 0;
249} 241}
250 242