diff options
| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-10-30 00:03:47 -0400 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-30 00:03:47 -0400 |
| commit | 41241c17eb11df08efa81727f9c01225cd0f56b3 (patch) | |
| tree | 34dc780b020176c0524820e745a8373b0adf41d0 | |
| parent | 36208059c18cd5e8c89fc9037cb1a79e62733882 (diff) | |
Blackfin arch: Add missing definitions for BF561
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
| -rw-r--r-- | include/asm-blackfin/mach-bf561/defBF561.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index bf7dc4e00065..7945e8a3a841 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h | |||
| @@ -55,6 +55,9 @@ | |||
| 55 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 55 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
| 56 | #define SWRST SICA_SWRST | 56 | #define SWRST SICA_SWRST |
| 57 | #define SYSCR SICA_SYSCR | 57 | #define SYSCR SICA_SYSCR |
| 58 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) | ||
| 59 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | ||
| 60 | #define RESET_SOFTWARE (SWRST_OCCURRED) | ||
| 58 | 61 | ||
| 59 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 62 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
| 60 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | 63 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ |