drm/radeon/kms: Add crtc tiling setup support for r6xx/r7xx

Needed for scanning out of a tiled buffer.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

2 files changed, 16 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a22d5a3bca4e..3b8f087eaf62 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1000,11 +1000,18 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                 return -EINVAL;
         }
 
-        if (tiling_flags & RADEON_TILING_MACRO)
-                fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+        if (rdev->family >= CHIP_R600) {
+                if (tiling_flags & RADEON_TILING_MACRO)
+                        fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
+                else if (tiling_flags & RADEON_TILING_MICRO)
+                        fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
+        } else {
+                if (tiling_flags & RADEON_TILING_MACRO)
+                        fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 
-        if (tiling_flags & RADEON_TILING_MICRO)
-                fb_format |= AVIVO_D1GRPH_TILED;
+                if (tiling_flags & RADEON_TILING_MICRO)
+                        fb_format |= AVIVO_D1GRPH_TILED;
+        }
 
         if (radeon_crtc->crtc_id == 0)
                 WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 93c9a2bbccf8..6ac1f604e29b 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -386,6 +386,11 @@
 #       define AVIVO_D1GRPH_TILED                               (1 << 20)
 #       define AVIVO_D1GRPH_MACRO_ADDRESS_MODE                  (1 << 21)
 
+#       define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL            (0 << 20)
+#       define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED            (1 << 20)
+#       define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)
+#       define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)
+
 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
  * block and vice versa.  This applies to GRPH, CUR, etc.
  */