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authorBard Liao <bardliao@realtek.com>2014-04-16 07:20:46 -0400
committerMark Brown <broonie@linaro.org>2014-04-18 13:52:18 -0400
commit40bc18a2a2677150840eff7fa77835b07da214dd (patch)
treed0e9366325f4c30ad75abc60e0410c94dce97a33
parentc9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)
ASoC: add RT5651 CODEC driver
This patch adds the Realtek ALC5651 codec driver. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat
-rw-r--r--include/sound/rt5651.h21
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5651.c1898
-rw-r--r--sound/soc/codecs/rt5651.h2081
5 files changed, 4006 insertions, 0 deletions
diff --git a/include/sound/rt5651.h b/include/sound/rt5651.h
new file mode 100644
index 000000000000..d35de758dfb5
--- /dev/null
+++ b/include/sound/rt5651.h
@@ -0,0 +1,21 @@
1/*
2 * linux/sound/rt286.h -- Platform data for RT286
3 *
4 * Copyright 2013 Realtek Microelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_RT5651_H
12#define __LINUX_SND_RT5651_H
13
14struct rt5651_platform_data {
15 /* IN2 can optionally be differential */
16 bool in2_diff;
17
18 bool dmic_en;
19};
20
21#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f0e840137887..deba71bad6e9 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -71,6 +71,7 @@ config SND_SOC_ALL_CODECS
71 select SND_SOC_PCM512x_SPI if SPI_MASTER 71 select SND_SOC_PCM512x_SPI if SPI_MASTER
72 select SND_SOC_RT5631 if I2C 72 select SND_SOC_RT5631 if I2C
73 select SND_SOC_RT5640 if I2C 73 select SND_SOC_RT5640 if I2C
74 select SND_SOC_RT5651 if I2C
74 select SND_SOC_SGTL5000 if I2C 75 select SND_SOC_SGTL5000 if I2C
75 select SND_SOC_SI476X if MFD_SI476X_CORE 76 select SND_SOC_SI476X if MFD_SI476X_CORE
76 select SND_SOC_SIRF_AUDIO_CODEC 77 select SND_SOC_SIRF_AUDIO_CODEC
@@ -396,6 +397,9 @@ config SND_SOC_RT5631
396config SND_SOC_RT5640 397config SND_SOC_RT5640
397 tristate 398 tristate
398 399
400config SND_SOC_RT5651
401 tristate
402
399#Freescale sgtl5000 codec 403#Freescale sgtl5000 codec
400config SND_SOC_SGTL5000 404config SND_SOC_SGTL5000
401 tristate "Freescale SGTL5000 CODEC" 405 tristate "Freescale SGTL5000 CODEC"
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 3c4d275d064b..e76938ee82f4 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -60,6 +60,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
60snd-soc-pcm512x-spi-objs := pcm512x-spi.o 60snd-soc-pcm512x-spi-objs := pcm512x-spi.o
61snd-soc-rt5631-objs := rt5631.o 61snd-soc-rt5631-objs := rt5631.o
62snd-soc-rt5640-objs := rt5640.o 62snd-soc-rt5640-objs := rt5640.o
63snd-soc-rt5651-objs := rt5651.o
63snd-soc-sgtl5000-objs := sgtl5000.o 64snd-soc-sgtl5000-objs := sgtl5000.o
64snd-soc-alc5623-objs := alc5623.o 65snd-soc-alc5623-objs := alc5623.o
65snd-soc-alc5632-objs := alc5632.o 66snd-soc-alc5632-objs := alc5632.o
@@ -211,6 +212,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
211obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o 212obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
212obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 213obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
213obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 214obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
215obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
214obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 216obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
215obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 217obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
216obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o 218obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
new file mode 100644
index 000000000000..a1577369c49c
--- /dev/null
+++ b/sound/soc/codecs/rt5651.c
@@ -0,0 +1,1898 @@
1/*
2 * rt5651.c -- RT5651 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "rt5651.h"
30
31#define RT5651_DEVICE_ID_VALUE 0x6281
32
33#define RT5651_PR_RANGE_BASE (0xff + 1)
34#define RT5651_PR_SPACING 0x100
35
36#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
37
38static const struct regmap_range_cfg rt5651_ranges[] = {
39 { .name = "PR", .range_min = RT5651_PR_BASE,
40 .range_max = RT5651_PR_BASE + 0xb4,
41 .selector_reg = RT5651_PRIV_INDEX,
42 .selector_mask = 0xff,
43 .selector_shift = 0x0,
44 .window_start = RT5651_PRIV_DATA,
45 .window_len = 0x1, },
46};
47
48static struct reg_default init_list[] = {
49 {RT5651_PR_BASE + 0x3d, 0x3e00},
50};
51
52static const struct reg_default rt5651_reg[] = {
53 { 0x00, 0x0000 },
54 { 0x02, 0xc8c8 },
55 { 0x03, 0xc8c8 },
56 { 0x05, 0x0000 },
57 { 0x0d, 0x0000 },
58 { 0x0e, 0x0000 },
59 { 0x0f, 0x0808 },
60 { 0x10, 0x0808 },
61 { 0x19, 0xafaf },
62 { 0x1a, 0xafaf },
63 { 0x1b, 0x0c00 },
64 { 0x1c, 0x2f2f },
65 { 0x1d, 0x2f2f },
66 { 0x1e, 0x0000 },
67 { 0x27, 0x7860 },
68 { 0x28, 0x7070 },
69 { 0x29, 0x8080 },
70 { 0x2a, 0x5252 },
71 { 0x2b, 0x5454 },
72 { 0x2f, 0x0000 },
73 { 0x30, 0x5000 },
74 { 0x3b, 0x0000 },
75 { 0x3c, 0x006f },
76 { 0x3d, 0x0000 },
77 { 0x3e, 0x006f },
78 { 0x45, 0x6000 },
79 { 0x4d, 0x0000 },
80 { 0x4e, 0x0000 },
81 { 0x4f, 0x0279 },
82 { 0x50, 0x0000 },
83 { 0x51, 0x0000 },
84 { 0x52, 0x0279 },
85 { 0x53, 0xf000 },
86 { 0x61, 0x0000 },
87 { 0x62, 0x0000 },
88 { 0x63, 0x00c0 },
89 { 0x64, 0x0000 },
90 { 0x65, 0x0000 },
91 { 0x66, 0x0000 },
92 { 0x70, 0x8000 },
93 { 0x71, 0x8000 },
94 { 0x73, 0x1104 },
95 { 0x74, 0x0c00 },
96 { 0x75, 0x1400 },
97 { 0x77, 0x0c00 },
98 { 0x78, 0x4000 },
99 { 0x79, 0x0123 },
100 { 0x80, 0x0000 },
101 { 0x81, 0x0000 },
102 { 0x82, 0x0000 },
103 { 0x83, 0x0800 },
104 { 0x84, 0x0000 },
105 { 0x85, 0x0008 },
106 { 0x89, 0x0000 },
107 { 0x8e, 0x0004 },
108 { 0x8f, 0x1100 },
109 { 0x90, 0x0000 },
110 { 0x93, 0x2000 },
111 { 0x94, 0x0200 },
112 { 0xb0, 0x2080 },
113 { 0xb1, 0x0000 },
114 { 0xb4, 0x2206 },
115 { 0xb5, 0x1f00 },
116 { 0xb6, 0x0000 },
117 { 0xbb, 0x0000 },
118 { 0xbc, 0x0000 },
119 { 0xbd, 0x0000 },
120 { 0xbe, 0x0000 },
121 { 0xbf, 0x0000 },
122 { 0xc0, 0x0400 },
123 { 0xc1, 0x0000 },
124 { 0xc2, 0x0000 },
125 { 0xcf, 0x0013 },
126 { 0xd0, 0x0680 },
127 { 0xd1, 0x1c17 },
128 { 0xd3, 0xb320 },
129 { 0xd9, 0x0809 },
130 { 0xfa, 0x0010 },
131 { 0xfe, 0x10ec },
132 { 0xff, 0x6281 },
133};
134
135static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
136{
137 int i;
138
139 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
140 if ((reg >= rt5651_ranges[i].window_start &&
141 reg <= rt5651_ranges[i].window_start +
142 rt5651_ranges[i].window_len) ||
143 (reg >= rt5651_ranges[i].range_min &&
144 reg <= rt5651_ranges[i].range_max)) {
145 return true;
146 }
147 }
148
149 switch (reg) {
150 case RT5651_RESET:
151 case RT5651_PRIV_DATA:
152 case RT5651_EQ_CTRL1:
153 case RT5651_ALC_1:
154 case RT5651_IRQ_CTRL2:
155 case RT5651_INT_IRQ_ST:
156 case RT5651_PGM_REG_ARR1:
157 case RT5651_PGM_REG_ARR3:
158 case RT5651_VENDOR_ID:
159 case RT5651_DEVICE_ID:
160 return true;
161 default:
162 return false;
163 }
164}
165
166static bool rt5651_readable_register(struct device *dev, unsigned int reg)
167{
168 int i;
169
170 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
171 if ((reg >= rt5651_ranges[i].window_start &&
172 reg <= rt5651_ranges[i].window_start +
173 rt5651_ranges[i].window_len) ||
174 (reg >= rt5651_ranges[i].range_min &&
175 reg <= rt5651_ranges[i].range_max)) {
176 return true;
177 }
178 }
179
180 switch (reg) {
181 case RT5651_RESET:
182 case RT5651_VERSION_ID:
183 case RT5651_VENDOR_ID:
184 case RT5651_DEVICE_ID:
185 case RT5651_HP_VOL:
186 case RT5651_LOUT_CTRL1:
187 case RT5651_LOUT_CTRL2:
188 case RT5651_IN1_IN2:
189 case RT5651_IN3:
190 case RT5651_INL1_INR1_VOL:
191 case RT5651_INL2_INR2_VOL:
192 case RT5651_DAC1_DIG_VOL:
193 case RT5651_DAC2_DIG_VOL:
194 case RT5651_DAC2_CTRL:
195 case RT5651_ADC_DIG_VOL:
196 case RT5651_ADC_DATA:
197 case RT5651_ADC_BST_VOL:
198 case RT5651_STO1_ADC_MIXER:
199 case RT5651_STO2_ADC_MIXER:
200 case RT5651_AD_DA_MIXER:
201 case RT5651_STO_DAC_MIXER:
202 case RT5651_DD_MIXER:
203 case RT5651_DIG_INF_DATA:
204 case RT5651_PDM_CTL:
205 case RT5651_REC_L1_MIXER:
206 case RT5651_REC_L2_MIXER:
207 case RT5651_REC_R1_MIXER:
208 case RT5651_REC_R2_MIXER:
209 case RT5651_HPO_MIXER:
210 case RT5651_OUT_L1_MIXER:
211 case RT5651_OUT_L2_MIXER:
212 case RT5651_OUT_L3_MIXER:
213 case RT5651_OUT_R1_MIXER:
214 case RT5651_OUT_R2_MIXER:
215 case RT5651_OUT_R3_MIXER:
216 case RT5651_LOUT_MIXER:
217 case RT5651_PWR_DIG1:
218 case RT5651_PWR_DIG2:
219 case RT5651_PWR_ANLG1:
220 case RT5651_PWR_ANLG2:
221 case RT5651_PWR_MIXER:
222 case RT5651_PWR_VOL:
223 case RT5651_PRIV_INDEX:
224 case RT5651_PRIV_DATA:
225 case RT5651_I2S1_SDP:
226 case RT5651_I2S2_SDP:
227 case RT5651_ADDA_CLK1:
228 case RT5651_ADDA_CLK2:
229 case RT5651_DMIC:
230 case RT5651_TDM_CTL_1:
231 case RT5651_TDM_CTL_2:
232 case RT5651_TDM_CTL_3:
233 case RT5651_GLB_CLK:
234 case RT5651_PLL_CTRL1:
235 case RT5651_PLL_CTRL2:
236 case RT5651_PLL_MODE_1:
237 case RT5651_PLL_MODE_2:
238 case RT5651_PLL_MODE_3:
239 case RT5651_PLL_MODE_4:
240 case RT5651_PLL_MODE_5:
241 case RT5651_PLL_MODE_6:
242 case RT5651_PLL_MODE_7:
243 case RT5651_DEPOP_M1:
244 case RT5651_DEPOP_M2:
245 case RT5651_DEPOP_M3:
246 case RT5651_CHARGE_PUMP:
247 case RT5651_MICBIAS:
248 case RT5651_A_JD_CTL1:
249 case RT5651_EQ_CTRL1:
250 case RT5651_EQ_CTRL2:
251 case RT5651_ALC_1:
252 case RT5651_ALC_2:
253 case RT5651_ALC_3:
254 case RT5651_JD_CTRL1:
255 case RT5651_JD_CTRL2:
256 case RT5651_IRQ_CTRL1:
257 case RT5651_IRQ_CTRL2:
258 case RT5651_INT_IRQ_ST:
259 case RT5651_GPIO_CTRL1:
260 case RT5651_GPIO_CTRL2:
261 case RT5651_GPIO_CTRL3:
262 case RT5651_PGM_REG_ARR1:
263 case RT5651_PGM_REG_ARR2:
264 case RT5651_PGM_REG_ARR3:
265 case RT5651_PGM_REG_ARR4:
266 case RT5651_PGM_REG_ARR5:
267 case RT5651_SCB_FUNC:
268 case RT5651_SCB_CTRL:
269 case RT5651_BASE_BACK:
270 case RT5651_MP3_PLUS1:
271 case RT5651_MP3_PLUS2:
272 case RT5651_ADJ_HPF_CTRL1:
273 case RT5651_ADJ_HPF_CTRL2:
274 case RT5651_HP_CALIB_AMP_DET:
275 case RT5651_HP_CALIB2:
276 case RT5651_SV_ZCD1:
277 case RT5651_SV_ZCD2:
278 case RT5651_D_MISC:
279 case RT5651_DUMMY2:
280 case RT5651_DUMMY3:
281 return true;
282 default:
283 return false;
284 }
285}
286
287static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
288static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
289static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
290static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
291static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
292
293/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
294static unsigned int bst_tlv[] = {
295 TLV_DB_RANGE_HEAD(7),
296 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
297 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
298 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
299 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
300 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
301 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
302 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
303};
304
305/* Interface data select */
306static const char * const rt5651_data_select[] = {
307 "Normal", "Swap", "left copy to right", "right copy to left"};
308
309static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
310 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
311
312static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
313 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
314
315static const struct snd_kcontrol_new rt5651_snd_controls[] = {
316 /* Headphone Output Volume */
317 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
318 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
319 /* OUTPUT Control */
320 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
321 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
322
323 /* DAC Digital Volume */
324 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
325 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
326 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
327 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
328 175, 0, dac_vol_tlv),
329 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
330 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
331 175, 0, dac_vol_tlv),
332 /* IN1/IN2 Control */
333 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
334 RT5651_BST_SFT1, 8, 0, bst_tlv),
335 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
336 RT5651_BST_SFT2, 8, 0, bst_tlv),
337 /* INL/INR Volume Control */
338 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
339 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
340 31, 1, in_vol_tlv),
341 /* ADC Digital Volume Control */
342 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
343 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
344 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
345 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
346 127, 0, adc_vol_tlv),
347 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
348 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
349 127, 0, adc_vol_tlv),
350 /* ADC Boost Volume Control */
351 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
352 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
353 3, 0, adc_bst_tlv),
354
355 /* ASRC */
356 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
357 RT5651_STO1_T_SFT, 1, 0),
358 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
359 RT5651_STO2_T_SFT, 1, 0),
360 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
361 RT5651_DMIC_1_M_SFT, 1, 0),
362
363 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
364 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
365};
366
367/**
368 * set_dmic_clk - Set parameter of dmic.
369 *
370 * @w: DAPM widget.
371 * @kcontrol: The kcontrol of this widget.
372 * @event: Event id.
373 *
374 * Choose dmic clock between 1MHz and 3MHz.
375 * It is better for clock to approximate 3MHz.
376 */
377static int set_dmic_clk(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
379{
380 struct snd_soc_codec *codec = w->codec;
381 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
382 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
383 int i, rate, red, bound, temp;
384
385 rate = rt5651->sysclk;
386 red = 3000000 * 12;
387 for (i = 0; i < ARRAY_SIZE(div); i++) {
388 bound = div[i] * 3000000;
389 if (rate > bound)
390 continue;
391 temp = bound - rate;
392 if (temp < red) {
393 red = temp;
394 idx = i;
395 }
396 }
397 if (idx < 0)
398 dev_err(codec->dev, "Failed to set DMIC clock\n");
399 else
400 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
401 idx << RT5651_DMIC_CLK_SFT);
402
403 return idx;
404}
405
406static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
407 struct snd_soc_dapm_widget *sink)
408{
409 unsigned int val;
410
411 val = snd_soc_read(source->codec, RT5651_GLB_CLK);
412 val &= RT5651_SCLK_SRC_MASK;
413 if (val == RT5651_SCLK_SRC_PLL1)
414 return 1;
415 else
416 return 0;
417}
418
419/* Digital Mixer */
420static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
421 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
422 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
423 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
424 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
425};
426
427static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
428 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
429 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
430 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
431 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
432};
433
434static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
435 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
436 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
437 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
438 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
439};
440
441static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
442 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
443 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
444 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
445 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
446};
447
448static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
449 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
450 RT5651_M_ADCMIX_L_SFT, 1, 1),
451 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
452 RT5651_M_IF1_DAC_L_SFT, 1, 1),
453};
454
455static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
456 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
457 RT5651_M_ADCMIX_R_SFT, 1, 1),
458 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
459 RT5651_M_IF1_DAC_R_SFT, 1, 1),
460};
461
462static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
463 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
464 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
465 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
466 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
467 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
468 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
469};
470
471static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
472 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
473 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
474 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
475 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
476 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
477 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
478};
479
480static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
481 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
482 RT5651_M_STO_DD_L1_SFT, 1, 1),
483 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
484 RT5651_M_STO_DD_L2_SFT, 1, 1),
485 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
486 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
487};
488
489static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
490 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
491 RT5651_M_STO_DD_R1_SFT, 1, 1),
492 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
493 RT5651_M_STO_DD_R2_SFT, 1, 1),
494 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
495 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
496};
497
498/* Analog Input Mixer */
499static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
500 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
501 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
502 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
503 RT5651_M_BST3_RM_L_SFT, 1, 1),
504 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
505 RT5651_M_BST2_RM_L_SFT, 1, 1),
506 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
507 RT5651_M_BST1_RM_L_SFT, 1, 1),
508};
509
510static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
511 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
512 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
513 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
514 RT5651_M_BST3_RM_R_SFT, 1, 1),
515 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
516 RT5651_M_BST2_RM_R_SFT, 1, 1),
517 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
518 RT5651_M_BST1_RM_R_SFT, 1, 1),
519};
520
521/* Analog Output Mixer */
522
523static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
524 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
525 RT5651_M_BST1_OM_L_SFT, 1, 1),
526 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
527 RT5651_M_BST2_OM_L_SFT, 1, 1),
528 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
529 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
530 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
531 RT5651_M_RM_L_OM_L_SFT, 1, 1),
532 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
533 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
534};
535
536static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
537 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
538 RT5651_M_BST2_OM_R_SFT, 1, 1),
539 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
540 RT5651_M_BST1_OM_R_SFT, 1, 1),
541 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
542 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
543 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
544 RT5651_M_RM_R_OM_R_SFT, 1, 1),
545 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
546 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
547};
548
549static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
550 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
551 RT5651_M_DAC1_HM_SFT, 1, 1),
552 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
553 RT5651_M_HPVOL_HM_SFT, 1, 1),
554};
555
556static const struct snd_kcontrol_new rt5651_lout_mix[] = {
557 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
558 RT5651_M_DAC_L1_LM_SFT, 1, 1),
559 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
560 RT5651_M_DAC_R1_LM_SFT, 1, 1),
561 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
562 RT5651_M_OV_L_LM_SFT, 1, 1),
563 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
564 RT5651_M_OV_R_LM_SFT, 1, 1),
565};
566
567static const struct snd_kcontrol_new outvol_l_control =
568 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
569 RT5651_VOL_L_SFT, 1, 1);
570
571static const struct snd_kcontrol_new outvol_r_control =
572 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
573 RT5651_VOL_R_SFT, 1, 1);
574
575static const struct snd_kcontrol_new lout_l_mute_control =
576 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
577 RT5651_L_MUTE_SFT, 1, 1);
578
579static const struct snd_kcontrol_new lout_r_mute_control =
580 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
581 RT5651_R_MUTE_SFT, 1, 1);
582
583static const struct snd_kcontrol_new hpovol_l_control =
584 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
585 RT5651_VOL_L_SFT, 1, 1);
586
587static const struct snd_kcontrol_new hpovol_r_control =
588 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
589 RT5651_VOL_R_SFT, 1, 1);
590
591static const struct snd_kcontrol_new hpo_l_mute_control =
592 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
593 RT5651_L_MUTE_SFT, 1, 1);
594
595static const struct snd_kcontrol_new hpo_r_mute_control =
596 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
597 RT5651_R_MUTE_SFT, 1, 1);
598
599/* INL/R source */
600static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
601
602static SOC_ENUM_SINGLE_DECL(
603 rt5651_inl_enum, RT5651_INL1_INR1_VOL,
604 RT5651_INL_SEL_SFT, rt5651_inl_src);
605
606static const struct snd_kcontrol_new rt5651_inl1_mux =
607 SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
608
609static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
610
611static SOC_ENUM_SINGLE_DECL(
612 rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
613 RT5651_INR_SEL_SFT, rt5651_inr1_src);
614
615static const struct snd_kcontrol_new rt5651_inr1_mux =
616 SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
617
618static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
619
620static SOC_ENUM_SINGLE_DECL(
621 rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
622 RT5651_INL_SEL_SFT, rt5651_inl2_src);
623
624static const struct snd_kcontrol_new rt5651_inl2_mux =
625 SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
626
627static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
628
629static SOC_ENUM_SINGLE_DECL(
630 rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
631 RT5651_INR_SEL_SFT, rt5651_inr2_src);
632
633static const struct snd_kcontrol_new rt5651_inr2_mux =
634 SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
635
636
637/* Stereo ADC source */
638static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
639
640static SOC_ENUM_SINGLE_DECL(
641 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
642 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
643
644static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
645 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
646
647static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
648 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
649
650static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
651
652static SOC_ENUM_SINGLE_DECL(
653 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
654 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
655
656static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
657 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
658
659static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
660 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
661
662/* Mono ADC source */
663static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
664
665static SOC_ENUM_SINGLE_DECL(
666 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
667 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
668
669static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
670 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
671
672static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
673
674static SOC_ENUM_SINGLE_DECL(
675 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
676 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
677
678static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
679 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
680
681static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
682
683static SOC_ENUM_SINGLE_DECL(
684 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
685 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
686
687static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
688 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
689
690static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
691
692static SOC_ENUM_SINGLE_DECL(
693 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
694 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
695
696static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
697 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
698
699/* DAC2 channel source */
700
701static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
702
703static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
704 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
705
706static const struct snd_kcontrol_new rt5651_dac_l2_mux =
707 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
708
709static SOC_ENUM_SINGLE_DECL(
710 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
711 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
712
713static const struct snd_kcontrol_new rt5651_dac_r2_mux =
714 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
715
716/* IF2_ADC channel source */
717
718static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
719
720static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
721 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
722
723static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
724 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
725
726/* PDM select */
727static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
728
729static SOC_ENUM_SINGLE_DECL(
730 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
731 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
732
733static SOC_ENUM_SINGLE_DECL(
734 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
735 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
736
737static const struct snd_kcontrol_new rt5651_pdm_l_mux =
738 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
739
740static const struct snd_kcontrol_new rt5651_pdm_r_mux =
741 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
742
743static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
744 struct snd_kcontrol *kcontrol, int event)
745{
746 struct snd_soc_codec *codec = w->codec;
747 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
748
749 switch (event) {
750 case SND_SOC_DAPM_POST_PMU:
751 /* depop parameters */
752 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
753 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
754 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
755 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
756 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
757 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
758 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
759 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
760 regmap_write(rt5651->regmap, RT5651_PR_BASE +
761 RT5651_HP_DCC_INT1, 0x9f00);
762 /* headphone amp power on */
763 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
764 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
765 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
766 RT5651_PWR_HA,
767 RT5651_PWR_HA);
768 usleep_range(10000, 15000);
769 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
770 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
771 RT5651_PWR_FV1 | RT5651_PWR_FV2);
772 break;
773
774 default:
775 return 0;
776 }
777
778 return 0;
779}
780
781static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
782 struct snd_kcontrol *kcontrol, int event)
783{
784 struct snd_soc_codec *codec = w->codec;
785 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
786
787 switch (event) {
788 case SND_SOC_DAPM_POST_PMU:
789 /* headphone unmute sequence */
790 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
791 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
792 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
793 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
794 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
795
796 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
797 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
798 RT5651_CP_FQ3_MASK,
799 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
800 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
801 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
802
803 regmap_write(rt5651->regmap, RT5651_PR_BASE +
804 RT5651_MAMP_INT_REG2, 0x1c00);
805 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
806 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
807 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
808 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
809 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
810 rt5651->hp_mute = 0;
811 break;
812
813 case SND_SOC_DAPM_PRE_PMD:
814 rt5651->hp_mute = 1;
815 usleep_range(70000, 75000);
816 break;
817
818 default:
819 return 0;
820 }
821
822 return 0;
823}
824
825static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
826 struct snd_kcontrol *kcontrol, int event)
827{
828 struct snd_soc_codec *codec = w->codec;
829 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
830
831 switch (event) {
832 case SND_SOC_DAPM_POST_PMU:
833 if (!rt5651->hp_mute)
834 usleep_range(80000, 85000);
835
836 break;
837
838 default:
839 return 0;
840 }
841
842 return 0;
843}
844
845static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
846 struct snd_kcontrol *kcontrol, int event)
847{
848 struct snd_soc_codec *codec = w->codec;
849
850 switch (event) {
851 case SND_SOC_DAPM_POST_PMU:
852 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
853 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
854 break;
855
856 case SND_SOC_DAPM_PRE_PMD:
857 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
858 RT5651_PWR_BST1_OP2, 0);
859 break;
860
861 default:
862 return 0;
863 }
864
865 return 0;
866}
867
868static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
869 struct snd_kcontrol *kcontrol, int event)
870{
871 struct snd_soc_codec *codec = w->codec;
872
873 switch (event) {
874 case SND_SOC_DAPM_POST_PMU:
875 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
876 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
877 break;
878
879 case SND_SOC_DAPM_PRE_PMD:
880 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
881 RT5651_PWR_BST2_OP2, 0);
882 break;
883
884 default:
885 return 0;
886 }
887
888 return 0;
889}
890
891static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
892 struct snd_kcontrol *kcontrol, int event)
893{
894 struct snd_soc_codec *codec = w->codec;
895
896 switch (event) {
897 case SND_SOC_DAPM_POST_PMU:
898 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
899 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
900 break;
901
902 case SND_SOC_DAPM_PRE_PMD:
903 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
904 RT5651_PWR_BST3_OP2, 0);
905 break;
906
907 default:
908 return 0;
909 }
910
911 return 0;
912}
913
914static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
915 /* ASRC */
916 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
917 15, 0, NULL, 0),
918 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
919 14, 0, NULL, 0),
920 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
921 13, 0, NULL, 0),
922 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
923 12, 0, NULL, 0),
924 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
925 11, 0, NULL, 0),
926
927 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
928 RT5651_PWR_PLL_BIT, 0, NULL, 0),
929 /* Input Side */
930 /* micbias */
931 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
932 RT5651_PWR_LDO_BIT, 0, NULL, 0),
933 SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
934 RT5651_PWR_MB1_BIT, 0),
935 /* Input Lines */
936 SND_SOC_DAPM_INPUT("MIC1"),
937 SND_SOC_DAPM_INPUT("MIC2"),
938 SND_SOC_DAPM_INPUT("MIC3"),
939
940 SND_SOC_DAPM_INPUT("IN1P"),
941 SND_SOC_DAPM_INPUT("IN2P"),
942 SND_SOC_DAPM_INPUT("IN2N"),
943 SND_SOC_DAPM_INPUT("IN3P"),
944 SND_SOC_DAPM_INPUT("DMIC L1"),
945 SND_SOC_DAPM_INPUT("DMIC R1"),
946 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
947 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
948 /* Boost */
949 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
950 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
951 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
952 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
953 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
954 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
955 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
956 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
957 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
958 /* Input Volume */
959 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
960 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
961 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
962 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
963 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
964 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
965 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
966 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
967 /* IN Mux */
968 SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
969 SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
970 SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
971 SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
972 /* REC Mixer */
973 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
974 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
975 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
976 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
977 /* ADCs */
978 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
979 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
980 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
981 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
982 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
983 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
984 /* ADC Mux */
985 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
986 &rt5651_sto1_adc_l2_mux),
987 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
988 &rt5651_sto1_adc_r2_mux),
989 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
990 &rt5651_sto1_adc_l1_mux),
991 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
992 &rt5651_sto1_adc_r1_mux),
993 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
994 &rt5651_sto2_adc_l2_mux),
995 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
996 &rt5651_sto2_adc_l1_mux),
997 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
998 &rt5651_sto2_adc_r1_mux),
999 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1000 &rt5651_sto2_adc_r2_mux),
1001 /* ADC Mixer */
1002 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
1003 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
1004 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
1005 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
1006 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1007 rt5651_sto1_adc_l_mix,
1008 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
1009 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1010 rt5651_sto1_adc_r_mix,
1011 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
1012 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1013 rt5651_sto2_adc_l_mix,
1014 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
1015 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1016 rt5651_sto2_adc_r_mix,
1017 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
1018
1019 /* Digital Interface */
1020 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
1021 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
1022 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1023 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1024 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1025 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1026 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1027 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1028 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1029 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1030 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1031 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1032 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1033 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1034 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1035 &rt5651_if2_adc_src_mux),
1036
1037 /* Digital Interface Select */
1038
1039 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1040 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1041 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1042 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1043 /* Audio Interface */
1044 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1045 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1046 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1047 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1048
1049 /* Audio DSP */
1050 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1051
1052 /* Output Side */
1053 /* DAC mixer before sound effect */
1054 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1055 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1056 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1057 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1058
1059 /* DAC2 channel Mux */
1060 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1061 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1062 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1063 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1064
1065 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1066 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1067 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1068 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1069 /* DAC Mixer */
1070 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1071 rt5651_sto_dac_l_mix,
1072 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1073 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1074 rt5651_sto_dac_r_mix,
1075 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1076 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1077 rt5651_dd_dac_l_mix,
1078 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1079 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1080 rt5651_dd_dac_r_mix,
1081 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1082
1083 /* DACs */
1084 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1085 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1086 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1087 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1088 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1089 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1090 /* OUT Mixer */
1091 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1092 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1093 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1094 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1095 /* Ouput Volume */
1096 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1097 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1098 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1099 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1100 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1101 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1102 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1103 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1104 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1105 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1106 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1107 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1109 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1110 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1111 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1112 /* HPO/LOUT/Mono Mixer */
1113 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1114 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1115 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1116 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1117 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1118 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1119 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1120 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1121 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1122 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1123
1124 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1125 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1126 SND_SOC_DAPM_POST_PMU),
1127 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1128 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1129 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1130 &hpo_l_mute_control),
1131 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1132 &hpo_r_mute_control),
1133 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1134 &lout_l_mute_control),
1135 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1136 &lout_r_mute_control),
1137 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1138
1139 /* Output Lines */
1140 SND_SOC_DAPM_OUTPUT("HPOL"),
1141 SND_SOC_DAPM_OUTPUT("HPOR"),
1142 SND_SOC_DAPM_OUTPUT("LOUTL"),
1143 SND_SOC_DAPM_OUTPUT("LOUTR"),
1144 SND_SOC_DAPM_OUTPUT("PDML"),
1145 SND_SOC_DAPM_OUTPUT("PDMR"),
1146};
1147
1148static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1149 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1150 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1151 {"I2S1", NULL, "I2S1 ASRC"},
1152 {"I2S2", NULL, "I2S2 ASRC"},
1153
1154 {"IN1P", NULL, "LDO"},
1155 {"IN2P", NULL, "LDO"},
1156 {"IN3P", NULL, "LDO"},
1157
1158 {"IN1P", NULL, "MIC1"},
1159 {"IN2P", NULL, "MIC2"},
1160 {"IN2N", NULL, "MIC2"},
1161 {"IN3P", NULL, "MIC3"},
1162
1163 {"BST1", NULL, "IN1P"},
1164 {"BST2", NULL, "IN2P"},
1165 {"BST2", NULL, "IN2N"},
1166 {"BST3", NULL, "IN3P"},
1167
1168 {"INL1 VOL", NULL, "IN2P"},
1169 {"INR1 VOL", NULL, "IN2N"},
1170
1171 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1172 {"RECMIXL", "BST3 Switch", "BST3"},
1173 {"RECMIXL", "BST2 Switch", "BST2"},
1174 {"RECMIXL", "BST1 Switch", "BST1"},
1175
1176 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1177 {"RECMIXR", "BST3 Switch", "BST3"},
1178 {"RECMIXR", "BST2 Switch", "BST2"},
1179 {"RECMIXR", "BST1 Switch", "BST1"},
1180
1181 {"ADC L", NULL, "RECMIXL"},
1182 {"ADC L", NULL, "ADC L Power"},
1183 {"ADC R", NULL, "RECMIXR"},
1184 {"ADC R", NULL, "ADC R Power"},
1185
1186 {"DMIC L1", NULL, "DMIC CLK"},
1187 {"DMIC R1", NULL, "DMIC CLK"},
1188
1189 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1190 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1191 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1192 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1193
1194 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1195 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1196 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1197 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1198
1199 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1200 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1201 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1202 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1203
1204 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1205 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1206 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1207 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1208
1209 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1210 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1211 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1212 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1213 {"Stereo1 Filter", NULL, "ADC ASRC"},
1214
1215 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1216 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1217 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1218
1219 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1220 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1221 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1222 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1223 {"Stereo2 Filter", NULL, "ADC ASRC"},
1224
1225 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1226 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1227 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1228
1229 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1230 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1231 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1232 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1233
1234 {"IF1 ADC1", NULL, "I2S1"},
1235
1236 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1237 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1238 {"IF2 ADC", NULL, "I2S2"},
1239
1240 {"AIF1TX", NULL, "IF1 ADC1"},
1241 {"AIF1TX", NULL, "IF1 ADC2"},
1242 {"AIF2TX", NULL, "IF2 ADC"},
1243
1244 {"IF1 DAC", NULL, "AIF1RX"},
1245 {"IF1 DAC", NULL, "I2S1"},
1246 {"IF2 DAC", NULL, "AIF2RX"},
1247 {"IF2 DAC", NULL, "I2S2"},
1248
1249 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1250 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1251 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1252 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1253 {"IF2 DAC L", NULL, "IF2 DAC"},
1254 {"IF2 DAC R", NULL, "IF2 DAC"},
1255
1256 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1257 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1258 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1259 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1260
1261 {"Audio DSP", NULL, "DAC MIXL"},
1262 {"Audio DSP", NULL, "DAC MIXR"},
1263
1264 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1265 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1266 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1267
1268 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1269 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1270 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1271
1272 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1273 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1274 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1275 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1276 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1277 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1278 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1279 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1280 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1281 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1282
1283 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1284 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1285 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1286 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1287
1288 {"DAC L1", NULL, "Stereo DAC MIXL"},
1289 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1290 {"DAC L1", NULL, "DAC L1 Power"},
1291 {"DAC R1", NULL, "Stereo DAC MIXR"},
1292 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1293 {"DAC R1", NULL, "DAC R1 Power"},
1294
1295 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1296 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1297 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1298 {"DD MIXL", NULL, "Stero2 DAC Power"},
1299
1300 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1301 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1302 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1303 {"DD MIXR", NULL, "Stero2 DAC Power"},
1304
1305 {"OUT MIXL", "BST1 Switch", "BST1"},
1306 {"OUT MIXL", "BST2 Switch", "BST2"},
1307 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1308 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1309 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1310
1311 {"OUT MIXR", "BST2 Switch", "BST2"},
1312 {"OUT MIXR", "BST1 Switch", "BST1"},
1313 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1314 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1315 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1316
1317 {"HPOVOL L", "Switch", "OUT MIXL"},
1318 {"HPOVOL R", "Switch", "OUT MIXR"},
1319 {"OUTVOL L", "Switch", "OUT MIXL"},
1320 {"OUTVOL R", "Switch", "OUT MIXR"},
1321
1322 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1323 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1324 {"HPOL MIX", NULL, "HP L Amp"},
1325 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1326 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1327 {"HPOR MIX", NULL, "HP R Amp"},
1328
1329 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1330 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1331 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1332 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1333
1334 {"HP Amp", NULL, "HPOL MIX"},
1335 {"HP Amp", NULL, "HPOR MIX"},
1336 {"HP Amp", NULL, "Amp Power"},
1337 {"HPO L Playback", "Switch", "HP Amp"},
1338 {"HPO R Playback", "Switch", "HP Amp"},
1339 {"HPOL", NULL, "HPO L Playback"},
1340 {"HPOR", NULL, "HPO R Playback"},
1341
1342 {"LOUT L Playback", "Switch", "LOUT MIX"},
1343 {"LOUT R Playback", "Switch", "LOUT MIX"},
1344 {"LOUTL", NULL, "LOUT L Playback"},
1345 {"LOUTL", NULL, "Amp Power"},
1346 {"LOUTR", NULL, "LOUT R Playback"},
1347 {"LOUTR", NULL, "Amp Power"},
1348
1349 {"PDML", NULL, "PDM L Mux"},
1350 {"PDMR", NULL, "PDM R Mux"},
1351};
1352
1353static int get_clk_info(int sclk, int rate)
1354{
1355 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1356
1357 if (sclk <= 0 || rate <= 0)
1358 return -EINVAL;
1359
1360 rate = rate << 8;
1361 for (i = 0; i < ARRAY_SIZE(pd); i++)
1362 if (sclk == rate * pd[i])
1363 return i;
1364
1365 return -EINVAL;
1366}
1367
1368static int rt5651_hw_params(struct snd_pcm_substream *substream,
1369 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1370{
1371 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1372 struct snd_soc_codec *codec = rtd->codec;
1373 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1374 unsigned int val_len = 0, val_clk, mask_clk;
1375 int pre_div, bclk_ms, frame_size;
1376
1377 rt5651->lrck[dai->id] = params_rate(params);
1378 pre_div = get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1379
1380 if (pre_div < 0) {
1381 dev_err(codec->dev, "Unsupported clock setting\n");
1382 return -EINVAL;
1383 }
1384 frame_size = snd_soc_params_to_frame_size(params);
1385 if (frame_size < 0) {
1386 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1387 return -EINVAL;
1388 }
1389 bclk_ms = frame_size > 32 ? 1 : 0;
1390 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1391
1392 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1393 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1394 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1395 bclk_ms, pre_div, dai->id);
1396
1397 switch (params_format(params)) {
1398 case SNDRV_PCM_FORMAT_S16_LE:
1399 break;
1400 case SNDRV_PCM_FORMAT_S20_3LE:
1401 val_len |= RT5651_I2S_DL_20;
1402 break;
1403 case SNDRV_PCM_FORMAT_S24_LE:
1404 val_len |= RT5651_I2S_DL_24;
1405 break;
1406 case SNDRV_PCM_FORMAT_S8:
1407 val_len |= RT5651_I2S_DL_8;
1408 break;
1409 default:
1410 return -EINVAL;
1411 }
1412
1413 switch (dai->id) {
1414 case RT5651_AIF1:
1415 mask_clk = RT5651_I2S_PD1_MASK;
1416 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1417 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1418 RT5651_I2S_DL_MASK, val_len);
1419 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1420 break;
1421 case RT5651_AIF2:
1422 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1423 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1424 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1425 RT5651_I2S_DL_MASK, val_len);
1426 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1427 break;
1428 default:
1429 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1430 return -EINVAL;
1431 }
1432
1433 return 0;
1434}
1435
1436static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1437{
1438 struct snd_soc_codec *codec = dai->codec;
1439 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1440 unsigned int reg_val = 0;
1441
1442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1443 case SND_SOC_DAIFMT_CBM_CFM:
1444 rt5651->master[dai->id] = 1;
1445 break;
1446 case SND_SOC_DAIFMT_CBS_CFS:
1447 reg_val |= RT5651_I2S_MS_S;
1448 rt5651->master[dai->id] = 0;
1449 break;
1450 default:
1451 return -EINVAL;
1452 }
1453
1454 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1455 case SND_SOC_DAIFMT_NB_NF:
1456 break;
1457 case SND_SOC_DAIFMT_IB_NF:
1458 reg_val |= RT5651_I2S_BP_INV;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1465 case SND_SOC_DAIFMT_I2S:
1466 break;
1467 case SND_SOC_DAIFMT_LEFT_J:
1468 reg_val |= RT5651_I2S_DF_LEFT;
1469 break;
1470 case SND_SOC_DAIFMT_DSP_A:
1471 reg_val |= RT5651_I2S_DF_PCM_A;
1472 break;
1473 case SND_SOC_DAIFMT_DSP_B:
1474 reg_val |= RT5651_I2S_DF_PCM_B;
1475 break;
1476 default:
1477 return -EINVAL;
1478 }
1479
1480 switch (dai->id) {
1481 case RT5651_AIF1:
1482 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1483 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1484 RT5651_I2S_DF_MASK, reg_val);
1485 break;
1486 case RT5651_AIF2:
1487 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1488 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1489 RT5651_I2S_DF_MASK, reg_val);
1490 break;
1491 default:
1492 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1493 return -EINVAL;
1494 }
1495 return 0;
1496}
1497
1498static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1499 int clk_id, unsigned int freq, int dir)
1500{
1501 struct snd_soc_codec *codec = dai->codec;
1502 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1503 unsigned int reg_val = 0;
1504
1505 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1506 return 0;
1507
1508 switch (clk_id) {
1509 case RT5651_SCLK_S_MCLK:
1510 reg_val |= RT5651_SCLK_SRC_MCLK;
1511 break;
1512 case RT5651_SCLK_S_PLL1:
1513 reg_val |= RT5651_SCLK_SRC_PLL1;
1514 break;
1515 case RT5651_SCLK_S_RCCLK:
1516 reg_val |= RT5651_SCLK_SRC_RCCLK;
1517 break;
1518 default:
1519 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1520 return -EINVAL;
1521 }
1522 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1523 RT5651_SCLK_SRC_MASK, reg_val);
1524 rt5651->sysclk = freq;
1525 rt5651->sysclk_src = clk_id;
1526
1527 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1528
1529 return 0;
1530}
1531
1532/**
1533 * rt5651_pll_calc - Calcualte PLL M/N/K code.
1534 * @freq_in: external clock provided to codec.
1535 * @freq_out: target clock which codec works on.
1536 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1537 *
1538 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1539 * which make calculation more efficiently.
1540 *
1541 * Returns 0 for success or negative error code.
1542 */
1543static int rt5651_pll_calc(const unsigned int freq_in,
1544 const unsigned int freq_out, struct rt5651_pll_code *pll_code)
1545{
1546 int max_n = RT5651_PLL_N_MAX, max_m = RT5651_PLL_M_MAX;
1547 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1548 int red_t = abs(freq_out - freq_in);
1549 bool bypass = false;
1550
1551 if (RT5651_PLL_INP_MAX < freq_in || RT5651_PLL_INP_MIN > freq_in)
1552 return -EINVAL;
1553
1554 for (n_t = 0; n_t <= max_n; n_t++) {
1555 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1556 if (in_t < 0)
1557 continue;
1558 if (in_t == freq_out) {
1559 bypass = true;
1560 n = n_t;
1561 goto code_find;
1562 }
1563 for (m_t = 0; m_t <= max_m; m_t++) {
1564 out_t = in_t / (m_t + 2);
1565 red = abs(out_t - freq_out);
1566 if (red < red_t) {
1567 n = n_t;
1568 m = m_t;
1569 if (red == 0)
1570 goto code_find;
1571 red_t = red;
1572 }
1573 }
1574 }
1575 pr_debug("Only get approximation about PLL\n");
1576
1577code_find:
1578 pll_code->m_bp = bypass;
1579 pll_code->m_code = m;
1580 pll_code->n_code = n;
1581 pll_code->k_code = 2;
1582 return 0;
1583}
1584
1585static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1586 unsigned int freq_in, unsigned int freq_out)
1587{
1588 struct snd_soc_codec *codec = dai->codec;
1589 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1590 struct rt5651_pll_code *pll_code = &rt5651->pll_code;
1591 int ret;
1592
1593 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1594 freq_out == rt5651->pll_out)
1595 return 0;
1596
1597 if (!freq_in || !freq_out) {
1598 dev_dbg(codec->dev, "PLL disabled\n");
1599
1600 rt5651->pll_in = 0;
1601 rt5651->pll_out = 0;
1602 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1603 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1604 return 0;
1605 }
1606
1607 switch (source) {
1608 case RT5651_PLL1_S_MCLK:
1609 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1610 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1611 break;
1612 case RT5651_PLL1_S_BCLK1:
1613 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1614 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1615 break;
1616 case RT5651_PLL1_S_BCLK2:
1617 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1618 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1619 break;
1620 default:
1621 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1622 return -EINVAL;
1623 }
1624
1625 ret = rt5651_pll_calc(freq_in, freq_out, pll_code);
1626 if (ret < 0) {
1627 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1628 return ret;
1629 }
1630
1631 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
1632 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
1633
1634 snd_soc_write(codec, RT5651_PLL_CTRL1,
1635 pll_code->n_code << RT5651_PLL_N_SFT | pll_code->k_code);
1636 snd_soc_write(codec, RT5651_PLL_CTRL2,
1637 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5651_PLL_M_SFT |
1638 pll_code->m_bp << RT5651_PLL_M_BP_SFT);
1639
1640 rt5651->pll_in = freq_in;
1641 rt5651->pll_out = freq_out;
1642 rt5651->pll_src = source;
1643
1644 return 0;
1645}
1646
1647static int rt5651_set_bias_level(struct snd_soc_codec *codec,
1648 enum snd_soc_bias_level level)
1649{
1650 switch (level) {
1651 case SND_SOC_BIAS_PREPARE:
1652 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1653 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1654 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1655 RT5651_PWR_BG | RT5651_PWR_VREF2,
1656 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1657 RT5651_PWR_BG | RT5651_PWR_VREF2);
1658 usleep_range(10000, 15000);
1659 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1660 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1661 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1662 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1663 RT5651_PWR_LDO_DVO_MASK,
1664 RT5651_PWR_LDO_DVO_1_2V);
1665 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
1666 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
1667 snd_soc_update_bits(codec, RT5651_D_MISC,
1668 0xc00, 0xc00);
1669 }
1670 break;
1671
1672 case SND_SOC_BIAS_STANDBY:
1673 snd_soc_write(codec, RT5651_D_MISC, 0x0010);
1674 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
1675 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
1676 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
1677 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
1678 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
1679 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
1680 break;
1681
1682 default:
1683 break;
1684 }
1685 codec->dapm.bias_level = level;
1686
1687 return 0;
1688}
1689
1690static int rt5651_probe(struct snd_soc_codec *codec)
1691{
1692 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1693
1694 rt5651->codec = codec;
1695
1696 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1697 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1698 RT5651_PWR_BG | RT5651_PWR_VREF2,
1699 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1700 RT5651_PWR_BG | RT5651_PWR_VREF2);
1701 usleep_range(10000, 15000);
1702 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1703 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1704 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1705
1706 rt5651_set_bias_level(codec, SND_SOC_BIAS_OFF);
1707
1708 return 0;
1709}
1710
1711#ifdef CONFIG_PM
1712static int rt5651_suspend(struct snd_soc_codec *codec)
1713{
1714 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1715
1716 regcache_cache_only(rt5651->regmap, true);
1717 regcache_mark_dirty(rt5651->regmap);
1718 return 0;
1719}
1720
1721static int rt5651_resume(struct snd_soc_codec *codec)
1722{
1723 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1724
1725 regcache_cache_only(rt5651->regmap, false);
1726 snd_soc_cache_sync(codec);
1727
1728 return 0;
1729}
1730#else
1731#define rt5651_suspend NULL
1732#define rt5651_resume NULL
1733#endif
1734
1735#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1736#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1737 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1738
1739struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1740 .hw_params = rt5651_hw_params,
1741 .set_fmt = rt5651_set_dai_fmt,
1742 .set_sysclk = rt5651_set_dai_sysclk,
1743 .set_pll = rt5651_set_dai_pll,
1744};
1745
1746struct snd_soc_dai_driver rt5651_dai[] = {
1747 {
1748 .name = "rt5651-aif1",
1749 .id = RT5651_AIF1,
1750 .playback = {
1751 .stream_name = "AIF1 Playback",
1752 .channels_min = 1,
1753 .channels_max = 2,
1754 .rates = RT5651_STEREO_RATES,
1755 .formats = RT5651_FORMATS,
1756 },
1757 .capture = {
1758 .stream_name = "AIF1 Capture",
1759 .channels_min = 1,
1760 .channels_max = 2,
1761 .rates = RT5651_STEREO_RATES,
1762 .formats = RT5651_FORMATS,
1763 },
1764 .ops = &rt5651_aif_dai_ops,
1765 },
1766 {
1767 .name = "rt5651-aif2",
1768 .id = RT5651_AIF2,
1769 .playback = {
1770 .stream_name = "AIF2 Playback",
1771 .channels_min = 1,
1772 .channels_max = 2,
1773 .rates = RT5651_STEREO_RATES,
1774 .formats = RT5651_FORMATS,
1775 },
1776 .capture = {
1777 .stream_name = "AIF2 Capture",
1778 .channels_min = 1,
1779 .channels_max = 2,
1780 .rates = RT5651_STEREO_RATES,
1781 .formats = RT5651_FORMATS,
1782 },
1783 .ops = &rt5651_aif_dai_ops,
1784 },
1785};
1786
1787static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
1788 .probe = rt5651_probe,
1789 .suspend = rt5651_suspend,
1790 .resume = rt5651_resume,
1791 .set_bias_level = rt5651_set_bias_level,
1792 .idle_bias_off = true,
1793 .controls = rt5651_snd_controls,
1794 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1795 .dapm_widgets = rt5651_dapm_widgets,
1796 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1797 .dapm_routes = rt5651_dapm_routes,
1798 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1799};
1800
1801static const struct regmap_config rt5651_regmap = {
1802 .reg_bits = 8,
1803 .val_bits = 16,
1804
1805 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1806 RT5651_PR_SPACING),
1807 .volatile_reg = rt5651_volatile_register,
1808 .readable_reg = rt5651_readable_register,
1809
1810 .cache_type = REGCACHE_RBTREE,
1811 .reg_defaults = rt5651_reg,
1812 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1813 .ranges = rt5651_ranges,
1814 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1815};
1816
1817static const struct i2c_device_id rt5651_i2c_id[] = {
1818 { "rt5651", 0 },
1819 { }
1820};
1821MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1822
1823static int rt5651_i2c_probe(struct i2c_client *i2c,
1824 const struct i2c_device_id *id)
1825{
1826 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
1827 struct rt5651_priv *rt5651;
1828 int ret;
1829
1830 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1831 GFP_KERNEL);
1832 if (NULL == rt5651)
1833 return -ENOMEM;
1834
1835 i2c_set_clientdata(i2c, rt5651);
1836
1837 if (pdata)
1838 rt5651->pdata = *pdata;
1839
1840 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1841 if (IS_ERR(rt5651->regmap)) {
1842 ret = PTR_ERR(rt5651->regmap);
1843 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1844 ret);
1845 return ret;
1846 }
1847
1848 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1849 if (ret != RT5651_DEVICE_ID_VALUE) {
1850 dev_err(&i2c->dev,
1851 "Device with ID register %x is not rt5651\n", ret);
1852 return -ENODEV;
1853 }
1854
1855 regmap_write(rt5651->regmap, RT5651_RESET, 0);
1856
1857 ret = regmap_register_patch(rt5651->regmap, init_list,
1858 ARRAY_SIZE(init_list));
1859 if (ret != 0)
1860 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1861
1862 if (rt5651->pdata.in2_diff)
1863 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
1864 RT5651_IN_DF2, RT5651_IN_DF2);
1865
1866 if (rt5651->pdata.dmic_en)
1867 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
1868 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1869
1870 rt5651->hp_mute = 1;
1871
1872 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
1873 rt5651_dai, ARRAY_SIZE(rt5651_dai));
1874
1875 return ret;
1876}
1877
1878static int rt5651_i2c_remove(struct i2c_client *i2c)
1879{
1880 snd_soc_unregister_codec(&i2c->dev);
1881
1882 return 0;
1883}
1884
1885struct i2c_driver rt5651_i2c_driver = {
1886 .driver = {
1887 .name = "rt5651",
1888 .owner = THIS_MODULE,
1889 },
1890 .probe = rt5651_i2c_probe,
1891 .remove = rt5651_i2c_remove,
1892 .id_table = rt5651_i2c_id,
1893};
1894module_i2c_driver(rt5651_i2c_driver);
1895
1896MODULE_DESCRIPTION("ASoC RT5651 driver");
1897MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1898MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
new file mode 100644
index 000000000000..a28bd0c3d613
--- /dev/null
+++ b/sound/soc/codecs/rt5651.h
@@ -0,0 +1,2081 @@
1/*
2 * rt5651.h -- RT5651 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5651_H__
13#define __RT5651_H__
14
15#include <sound/rt5651.h>
16
17/* Info */
18#define RT5651_RESET 0x00
19#define RT5651_VERSION_ID 0xfd
20#define RT5651_VENDOR_ID 0xfe
21#define RT5651_DEVICE_ID 0xff
22/* I/O - Output */
23#define RT5651_HP_VOL 0x02
24#define RT5651_LOUT_CTRL1 0x03
25#define RT5651_LOUT_CTRL2 0x05
26/* I/O - Input */
27#define RT5651_IN1_IN2 0x0d
28#define RT5651_IN3 0x0e
29#define RT5651_INL1_INR1_VOL 0x0f
30#define RT5651_INL2_INR2_VOL 0x10
31/* I/O - ADC/DAC/DMIC */
32#define RT5651_DAC1_DIG_VOL 0x19
33#define RT5651_DAC2_DIG_VOL 0x1a
34#define RT5651_DAC2_CTRL 0x1b
35#define RT5651_ADC_DIG_VOL 0x1c
36#define RT5651_ADC_DATA 0x1d
37#define RT5651_ADC_BST_VOL 0x1e
38/* Mixer - D-D */
39#define RT5651_STO1_ADC_MIXER 0x27
40#define RT5651_STO2_ADC_MIXER 0x28
41#define RT5651_AD_DA_MIXER 0x29
42#define RT5651_STO_DAC_MIXER 0x2a
43#define RT5651_DD_MIXER 0x2b
44#define RT5651_DIG_INF_DATA 0x2f
45/* PDM */
46#define RT5651_PDM_CTL 0x30
47#define RT5651_PDM_I2C_CTL1 0x31
48#define RT5651_PDM_I2C_CTL2 0x32
49#define RT5651_PDM_I2C_DATA_W 0x33
50#define RT5651_PDM_I2C_DATA_R 0x34
51/* Mixer - ADC */
52#define RT5651_REC_L1_MIXER 0x3b
53#define RT5651_REC_L2_MIXER 0x3c
54#define RT5651_REC_R1_MIXER 0x3d
55#define RT5651_REC_R2_MIXER 0x3e
56/* Mixer - DAC */
57#define RT5651_HPO_MIXER 0x45
58#define RT5651_OUT_L1_MIXER 0x4d
59#define RT5651_OUT_L2_MIXER 0x4e
60#define RT5651_OUT_L3_MIXER 0x4f
61#define RT5651_OUT_R1_MIXER 0x50
62#define RT5651_OUT_R2_MIXER 0x51
63#define RT5651_OUT_R3_MIXER 0x52
64#define RT5651_LOUT_MIXER 0x53
65/* Power */
66#define RT5651_PWR_DIG1 0x61
67#define RT5651_PWR_DIG2 0x62
68#define RT5651_PWR_ANLG1 0x63
69#define RT5651_PWR_ANLG2 0x64
70#define RT5651_PWR_MIXER 0x65
71#define RT5651_PWR_VOL 0x66
72/* Private Register Control */
73#define RT5651_PRIV_INDEX 0x6a
74#define RT5651_PRIV_DATA 0x6c
75/* Format - ADC/DAC */
76#define RT5651_I2S1_SDP 0x70
77#define RT5651_I2S2_SDP 0x71
78#define RT5651_ADDA_CLK1 0x73
79#define RT5651_ADDA_CLK2 0x74
80#define RT5651_DMIC 0x75
81/* TDM Control */
82#define RT5651_TDM_CTL_1 0x77
83#define RT5651_TDM_CTL_2 0x78
84#define RT5651_TDM_CTL_3 0x79
85/* Function - Analog */
86#define RT5651_GLB_CLK 0x80
87#define RT5651_PLL_CTRL1 0x81
88#define RT5651_PLL_CTRL2 0x82
89#define RT5651_PLL_MODE_1 0x83
90#define RT5651_PLL_MODE_2 0x84
91#define RT5651_PLL_MODE_3 0x85
92#define RT5651_PLL_MODE_4 0x86
93#define RT5651_PLL_MODE_5 0x87
94#define RT5651_PLL_MODE_6 0x89
95#define RT5651_PLL_MODE_7 0x8a
96#define RT5651_DEPOP_M1 0x8e
97#define RT5651_DEPOP_M2 0x8f
98#define RT5651_DEPOP_M3 0x90
99#define RT5651_CHARGE_PUMP 0x91
100#define RT5651_MICBIAS 0x93
101#define RT5651_A_JD_CTL1 0x94
102/* Function - Digital */
103#define RT5651_EQ_CTRL1 0xb0
104#define RT5651_EQ_CTRL2 0xb1
105#define RT5651_ALC_1 0xb4
106#define RT5651_ALC_2 0xb5
107#define RT5651_ALC_3 0xb6
108#define RT5651_JD_CTRL1 0xbb
109#define RT5651_JD_CTRL2 0xbc
110#define RT5651_IRQ_CTRL1 0xbd
111#define RT5651_IRQ_CTRL2 0xbe
112#define RT5651_INT_IRQ_ST 0xbf
113#define RT5651_GPIO_CTRL1 0xc0
114#define RT5651_GPIO_CTRL2 0xc1
115#define RT5651_GPIO_CTRL3 0xc2
116#define RT5651_PGM_REG_ARR1 0xc8
117#define RT5651_PGM_REG_ARR2 0xc9
118#define RT5651_PGM_REG_ARR3 0xca
119#define RT5651_PGM_REG_ARR4 0xcb
120#define RT5651_PGM_REG_ARR5 0xcc
121#define RT5651_SCB_FUNC 0xcd
122#define RT5651_SCB_CTRL 0xce
123#define RT5651_BASE_BACK 0xcf
124#define RT5651_MP3_PLUS1 0xd0
125#define RT5651_MP3_PLUS2 0xd1
126#define RT5651_ADJ_HPF_CTRL1 0xd3
127#define RT5651_ADJ_HPF_CTRL2 0xd4
128#define RT5651_HP_CALIB_AMP_DET 0xd6
129#define RT5651_HP_CALIB2 0xd7
130#define RT5651_SV_ZCD1 0xd9
131#define RT5651_SV_ZCD2 0xda
132#define RT5651_D_MISC 0xfa
133/* Dummy Register */
134#define RT5651_DUMMY2 0xfb
135#define RT5651_DUMMY3 0xfc
136
137
138/* Index of Codec Private Register definition */
139#define RT5651_BIAS_CUR1 0x12
140#define RT5651_BIAS_CUR3 0x14
141#define RT5651_CLSD_INT_REG1 0x1c
142#define RT5651_CHPUMP_INT_REG1 0x24
143#define RT5651_MAMP_INT_REG2 0x37
144#define RT5651_CHOP_DAC_ADC 0x3d
145#define RT5651_3D_SPK 0x63
146#define RT5651_WND_1 0x6c
147#define RT5651_WND_2 0x6d
148#define RT5651_WND_3 0x6e
149#define RT5651_WND_4 0x6f
150#define RT5651_WND_5 0x70
151#define RT5651_WND_8 0x73
152#define RT5651_DIP_SPK_INF 0x75
153#define RT5651_HP_DCC_INT1 0x77
154#define RT5651_EQ_BW_LOP 0xa0
155#define RT5651_EQ_GN_LOP 0xa1
156#define RT5651_EQ_FC_BP1 0xa2
157#define RT5651_EQ_BW_BP1 0xa3
158#define RT5651_EQ_GN_BP1 0xa4
159#define RT5651_EQ_FC_BP2 0xa5
160#define RT5651_EQ_BW_BP2 0xa6
161#define RT5651_EQ_GN_BP2 0xa7
162#define RT5651_EQ_FC_BP3 0xa8
163#define RT5651_EQ_BW_BP3 0xa9
164#define RT5651_EQ_GN_BP3 0xaa
165#define RT5651_EQ_FC_BP4 0xab
166#define RT5651_EQ_BW_BP4 0xac
167#define RT5651_EQ_GN_BP4 0xad
168#define RT5651_EQ_FC_HIP1 0xae
169#define RT5651_EQ_GN_HIP1 0xaf
170#define RT5651_EQ_FC_HIP2 0xb0
171#define RT5651_EQ_BW_HIP2 0xb1
172#define RT5651_EQ_GN_HIP2 0xb2
173#define RT5651_EQ_PRE_VOL 0xb3
174#define RT5651_EQ_PST_VOL 0xb4
175
176
177/* global definition */
178#define RT5651_L_MUTE (0x1 << 15)
179#define RT5651_L_MUTE_SFT 15
180#define RT5651_VOL_L_MUTE (0x1 << 14)
181#define RT5651_VOL_L_SFT 14
182#define RT5651_R_MUTE (0x1 << 7)
183#define RT5651_R_MUTE_SFT 7
184#define RT5651_VOL_R_MUTE (0x1 << 6)
185#define RT5651_VOL_R_SFT 6
186#define RT5651_L_VOL_MASK (0x3f << 8)
187#define RT5651_L_VOL_SFT 8
188#define RT5651_R_VOL_MASK (0x3f)
189#define RT5651_R_VOL_SFT 0
190
191/* LOUT Control 2(0x05) */
192#define RT5651_EN_DFO (0x1 << 15)
193
194/* IN1 and IN2 Control (0x0d) */
195/* IN3 and IN4 Control (0x0e) */
196#define RT5651_BST_MASK1 (0xf<<12)
197#define RT5651_BST_SFT1 12
198#define RT5651_BST_MASK2 (0xf<<8)
199#define RT5651_BST_SFT2 8
200#define RT5651_IN_DF1 (0x1 << 7)
201#define RT5651_IN_SFT1 7
202#define RT5651_IN_DF2 (0x1 << 6)
203#define RT5651_IN_SFT2 6
204
205/* INL1 and INR1 Volume Control (0x0f) */
206/* INL2 and INR2 Volume Control (0x10) */
207#define RT5651_INL_SEL_MASK (0x1 << 15)
208#define RT5651_INL_SEL_SFT 15
209#define RT5651_INL_SEL_IN4P (0x0 << 15)
210#define RT5651_INL_SEL_MONOP (0x1 << 15)
211#define RT5651_INL_VOL_MASK (0x1f << 8)
212#define RT5651_INL_VOL_SFT 8
213#define RT5651_INR_SEL_MASK (0x1 << 7)
214#define RT5651_INR_SEL_SFT 7
215#define RT5651_INR_SEL_IN4N (0x0 << 7)
216#define RT5651_INR_SEL_MONON (0x1 << 7)
217#define RT5651_INR_VOL_MASK (0x1f)
218#define RT5651_INR_VOL_SFT 0
219
220/* DAC1 Digital Volume (0x19) */
221#define RT5651_DAC_L1_VOL_MASK (0xff << 8)
222#define RT5651_DAC_L1_VOL_SFT 8
223#define RT5651_DAC_R1_VOL_MASK (0xff)
224#define RT5651_DAC_R1_VOL_SFT 0
225
226/* DAC2 Digital Volume (0x1a) */
227#define RT5651_DAC_L2_VOL_MASK (0xff << 8)
228#define RT5651_DAC_L2_VOL_SFT 8
229#define RT5651_DAC_R2_VOL_MASK (0xff)
230#define RT5651_DAC_R2_VOL_SFT 0
231
232/* DAC2 Control (0x1b) */
233#define RT5651_M_DAC_L2_VOL (0x1 << 13)
234#define RT5651_M_DAC_L2_VOL_SFT 13
235#define RT5651_M_DAC_R2_VOL (0x1 << 12)
236#define RT5651_M_DAC_R2_VOL_SFT 12
237#define RT5651_SEL_DAC_L2 (0x1 << 11)
238#define RT5651_IF2_DAC_L2 (0x1 << 11)
239#define RT5651_IF1_DAC_L2 (0x0 << 11)
240#define RT5651_SEL_DAC_L2_SFT 11
241#define RT5651_SEL_DAC_R2 (0x1 << 10)
242#define RT5651_IF2_DAC_R2 (0x1 << 11)
243#define RT5651_IF1_DAC_R2 (0x0 << 11)
244#define RT5651_SEL_DAC_R2_SFT 10
245
246/* ADC Digital Volume Control (0x1c) */
247#define RT5651_ADC_L_VOL_MASK (0x7f << 8)
248#define RT5651_ADC_L_VOL_SFT 8
249#define RT5651_ADC_R_VOL_MASK (0x7f)
250#define RT5651_ADC_R_VOL_SFT 0
251
252/* Mono ADC Digital Volume Control (0x1d) */
253#define RT5651_M_MONO_ADC_L (0x1 << 15)
254#define RT5651_M_MONO_ADC_L_SFT 15
255#define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
256#define RT5651_MONO_ADC_L_VOL_SFT 8
257#define RT5651_M_MONO_ADC_R (0x1 << 7)
258#define RT5651_M_MONO_ADC_R_SFT 7
259#define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
260#define RT5651_MONO_ADC_R_VOL_SFT 0
261
262/* ADC Boost Volume Control (0x1e) */
263#define RT5651_ADC_L_BST_MASK (0x3 << 14)
264#define RT5651_ADC_L_BST_SFT 14
265#define RT5651_ADC_R_BST_MASK (0x3 << 12)
266#define RT5651_ADC_R_BST_SFT 12
267#define RT5651_ADC_COMP_MASK (0x3 << 10)
268#define RT5651_ADC_COMP_SFT 10
269
270/* Stereo ADC1 Mixer Control (0x27) */
271#define RT5651_M_STO1_ADC_L1 (0x1 << 14)
272#define RT5651_M_STO1_ADC_L1_SFT 14
273#define RT5651_M_STO1_ADC_L2 (0x1 << 13)
274#define RT5651_M_STO1_ADC_L2_SFT 13
275#define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
276#define RT5651_STO1_ADC_1_SRC_SFT 12
277#define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
278#define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
279#define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
280#define RT5651_STO1_ADC_2_SRC_SFT 11
281#define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
282#define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
283#define RT5651_M_STO1_ADC_R1 (0x1 << 6)
284#define RT5651_M_STO1_ADC_R1_SFT 6
285#define RT5651_M_STO1_ADC_R2 (0x1 << 5)
286#define RT5651_M_STO1_ADC_R2_SFT 5
287
288/* Stereo ADC2 Mixer Control (0x28) */
289#define RT5651_M_STO2_ADC_L1 (0x1 << 14)
290#define RT5651_M_STO2_ADC_L1_SFT 14
291#define RT5651_M_STO2_ADC_L2 (0x1 << 13)
292#define RT5651_M_STO2_ADC_L2_SFT 13
293#define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
294#define RT5651_STO2_ADC_L1_SRC_SFT 12
295#define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
296#define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
297#define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
298#define RT5651_STO2_ADC_L2_SRC_SFT 11
299#define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
300#define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
301#define RT5651_M_STO2_ADC_R1 (0x1 << 6)
302#define RT5651_M_STO2_ADC_R1_SFT 6
303#define RT5651_M_STO2_ADC_R2 (0x1 << 5)
304#define RT5651_M_STO2_ADC_R2_SFT 5
305#define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
306#define RT5651_STO2_ADC_R1_SRC_SFT 4
307#define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
308#define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
309#define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
310#define RT5651_STO2_ADC_R2_SRC_SFT 3
311#define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
312#define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
313
314/* ADC Mixer to DAC Mixer Control (0x29) */
315#define RT5651_M_ADCMIX_L (0x1 << 15)
316#define RT5651_M_ADCMIX_L_SFT 15
317#define RT5651_M_IF1_DAC_L (0x1 << 14)
318#define RT5651_M_IF1_DAC_L_SFT 14
319#define RT5651_M_ADCMIX_R (0x1 << 7)
320#define RT5651_M_ADCMIX_R_SFT 7
321#define RT5651_M_IF1_DAC_R (0x1 << 6)
322#define RT5651_M_IF1_DAC_R_SFT 6
323
324/* Stereo DAC Mixer Control (0x2a) */
325#define RT5651_M_DAC_L1_MIXL (0x1 << 14)
326#define RT5651_M_DAC_L1_MIXL_SFT 14
327#define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
328#define RT5651_DAC_L1_STO_L_VOL_SFT 13
329#define RT5651_M_DAC_L2_MIXL (0x1 << 12)
330#define RT5651_M_DAC_L2_MIXL_SFT 12
331#define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
332#define RT5651_DAC_L2_STO_L_VOL_SFT 11
333#define RT5651_M_DAC_R1_MIXL (0x1 << 9)
334#define RT5651_M_DAC_R1_MIXL_SFT 9
335#define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
336#define RT5651_DAC_R1_STO_L_VOL_SFT 8
337#define RT5651_M_DAC_R1_MIXR (0x1 << 6)
338#define RT5651_M_DAC_R1_MIXR_SFT 6
339#define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
340#define RT5651_DAC_R1_STO_R_VOL_SFT 5
341#define RT5651_M_DAC_R2_MIXR (0x1 << 4)
342#define RT5651_M_DAC_R2_MIXR_SFT 4
343#define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
344#define RT5651_DAC_R2_STO_R_VOL_SFT 3
345#define RT5651_M_DAC_L1_MIXR (0x1 << 1)
346#define RT5651_M_DAC_L1_MIXR_SFT 1
347#define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
348#define RT5651_DAC_L1_STO_R_VOL_SFT 0
349
350/* DD Mixer Control (0x2b) */
351#define RT5651_M_STO_DD_L1 (0x1 << 14)
352#define RT5651_M_STO_DD_L1_SFT 14
353#define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
354#define RT5651_DAC_DD_L1_VOL_SFT 13
355#define RT5651_M_STO_DD_L2 (0x1 << 12)
356#define RT5651_M_STO_DD_L2_SFT 12
357#define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
358#define RT5651_STO_DD_L2_VOL_SFT 11
359#define RT5651_M_STO_DD_R2_L (0x1 << 10)
360#define RT5651_M_STO_DD_R2_L_SFT 10
361#define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
362#define RT5651_STO_DD_R2_L_VOL_SFT 9
363#define RT5651_M_STO_DD_R1 (0x1 << 6)
364#define RT5651_M_STO_DD_R1_SFT 6
365#define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
366#define RT5651_STO_DD_R1_VOL_SFT 5
367#define RT5651_M_STO_DD_R2 (0x1 << 4)
368#define RT5651_M_STO_DD_R2_SFT 4
369#define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
370#define RT5651_STO_DD_R2_VOL_SFT 3
371#define RT5651_M_STO_DD_L2_R (0x1 << 2)
372#define RT5651_M_STO_DD_L2_R_SFT 2
373#define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
374#define RT5651_STO_DD_L2_R_VOL_SFT 1
375
376/* Digital Mixer Control (0x2c) */
377#define RT5651_M_STO_L_DAC_L (0x1 << 15)
378#define RT5651_M_STO_L_DAC_L_SFT 15
379#define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
380#define RT5651_STO_L_DAC_L_VOL_SFT 14
381#define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
382#define RT5651_M_DAC_L2_DAC_L_SFT 13
383#define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
384#define RT5651_DAC_L2_DAC_L_VOL_SFT 12
385#define RT5651_M_STO_R_DAC_R (0x1 << 11)
386#define RT5651_M_STO_R_DAC_R_SFT 11
387#define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
388#define RT5651_STO_R_DAC_R_VOL_SFT 10
389#define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
390#define RT5651_M_DAC_R2_DAC_R_SFT 9
391#define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
392#define RT5651_DAC_R2_DAC_R_VOL_SFT 8
393
394/* DSP Path Control 1 (0x2d) */
395#define RT5651_RXDP_SRC_MASK (0x1 << 15)
396#define RT5651_RXDP_SRC_SFT 15
397#define RT5651_RXDP_SRC_NOR (0x0 << 15)
398#define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
399#define RT5651_TXDP_SRC_MASK (0x1 << 14)
400#define RT5651_TXDP_SRC_SFT 14
401#define RT5651_TXDP_SRC_NOR (0x0 << 14)
402#define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
403
404/* DSP Path Control 2 (0x2e) */
405#define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
406#define RT5651_DAC_L2_SEL_SFT 14
407#define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
408#define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
409#define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
410#define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
411#define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
412#define RT5651_DAC_R2_SEL_SFT 12
413#define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
414#define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
415#define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
416#define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
417#define RT5651_IF2_ADC_L_SEL_SFT 11
418#define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
419#define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
420#define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
421#define RT5651_IF2_ADC_R_SEL_SFT 10
422#define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
423#define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
424#define RT5651_RXDC_SEL_MASK (0x3 << 8)
425#define RT5651_RXDC_SEL_SFT 8
426#define RT5651_RXDC_SEL_NOR (0x0 << 8)
427#define RT5651_RXDC_SEL_L2R (0x1 << 8)
428#define RT5651_RXDC_SEL_R2L (0x2 << 8)
429#define RT5651_RXDC_SEL_SWAP (0x3 << 8)
430#define RT5651_RXDP_SEL_MASK (0x3 << 6)
431#define RT5651_RXDP_SEL_SFT 6
432#define RT5651_RXDP_SEL_NOR (0x0 << 6)
433#define RT5651_RXDP_SEL_L2R (0x1 << 6)
434#define RT5651_RXDP_SEL_R2L (0x2 << 6)
435#define RT5651_RXDP_SEL_SWAP (0x3 << 6)
436#define RT5651_TXDC_SEL_MASK (0x3 << 4)
437#define RT5651_TXDC_SEL_SFT 4
438#define RT5651_TXDC_SEL_NOR (0x0 << 4)
439#define RT5651_TXDC_SEL_L2R (0x1 << 4)
440#define RT5651_TXDC_SEL_R2L (0x2 << 4)
441#define RT5651_TXDC_SEL_SWAP (0x3 << 4)
442#define RT5651_TXDP_SEL_MASK (0x3 << 2)
443#define RT5651_TXDP_SEL_SFT 2
444#define RT5651_TXDP_SEL_NOR (0x0 << 2)
445#define RT5651_TXDP_SEL_L2R (0x1 << 2)
446#define RT5651_TXDP_SEL_R2L (0x2 << 2)
447#define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
448
449/* Digital Interface Data Control (0x2f) */
450#define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
451#define RT5651_IF2_DAC_SEL_SFT 10
452#define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
453#define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
454#define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
455#define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
456#define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
457#define RT5651_IF2_ADC_SEL_SFT 8
458#define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
459#define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
460#define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
461#define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
462#define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
463#define RT5651_IF2_ADC_SRC_SFT 7
464#define RT5651_IF1_ADC1 (0x0 << 7)
465#define RT5651_IF1_ADC2 (0x1 << 7)
466
467/* PDM Output Control (0x30) */
468#define RT5651_PDM_L_SEL_MASK (0x1 << 15)
469#define RT5651_PDM_L_SEL_SFT 15
470#define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
471#define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
472#define RT5651_M_PDM_L (0x1 << 14)
473#define RT5651_M_PDM_L_SFT 14
474#define RT5651_PDM_R_SEL_MASK (0x1 << 13)
475#define RT5651_PDM_R_SEL_SFT 13
476#define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
477#define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
478#define RT5651_M_PDM_R (0x1 << 12)
479#define RT5651_M_PDM_R_SFT 12
480#define RT5651_PDM_BUSY (0x1 << 6)
481#define RT5651_PDM_BUSY_SFT 6
482#define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
483#define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
484#define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
485#define RT5651_PDM_VOL_MASK (0x1 << 4)
486#define RT5651_PDM_VOL_SFT 4
487#define RT5651_PDM_DIV_MASK (0x3)
488#define RT5651_PDM_DIV_SFT 0
489#define RT5651_PDM_DIV_1 0
490#define RT5651_PDM_DIV_2 1
491#define RT5651_PDM_DIV_3 2
492#define RT5651_PDM_DIV_4 3
493
494/* PDM I2C/Data Control 1 (0x31) */
495#define RT5651_PDM_I2C_ID_MASK (0xf << 12)
496#define PT5631_PDM_CMD_EXE (0x1 << 11)
497#define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
498#define RT5651_PDM_I2C_CMD_R (0x0 << 10)
499#define RT5651_PDM_I2C_CMD_W (0x1 << 10)
500#define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
501#define RT5651_PDM_I2C_NORMAL (0x0 << 8)
502#define RT5651_PDM_I2C_BUSY (0x1 << 8)
503
504/* PDM I2C/Data Control 2 (0x32) */
505#define RT5651_PDM_I2C_ADDR (0xff << 8)
506#define RT5651_PDM_I2C_CMD_PATTERN (0xff)
507
508
509/* REC Left Mixer Control 1 (0x3b) */
510#define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
511#define RT5651_G_IN_L2_RM_L_SFT 13
512#define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
513#define RT5651_G_IN_L1_RM_L_SFT 10
514#define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
515#define RT5651_G_BST3_RM_L_SFT 4
516#define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
517#define RT5651_G_BST2_RM_L_SFT 1
518
519/* REC Left Mixer Control 2 (0x3c) */
520#define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
521#define RT5651_G_BST1_RM_L_SFT 13
522#define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
523#define RT5651_G_OM_L_RM_L_SFT 10
524#define RT5651_M_IN2_L_RM_L (0x1 << 6)
525#define RT5651_M_IN2_L_RM_L_SFT 6
526#define RT5651_M_IN1_L_RM_L (0x1 << 5)
527#define RT5651_M_IN1_L_RM_L_SFT 5
528#define RT5651_M_BST3_RM_L (0x1 << 3)
529#define RT5651_M_BST3_RM_L_SFT 3
530#define RT5651_M_BST2_RM_L (0x1 << 2)
531#define RT5651_M_BST2_RM_L_SFT 2
532#define RT5651_M_BST1_RM_L (0x1 << 1)
533#define RT5651_M_BST1_RM_L_SFT 1
534#define RT5651_M_OM_L_RM_L (0x1)
535#define RT5651_M_OM_L_RM_L_SFT 0
536
537/* REC Right Mixer Control 1 (0x3d) */
538#define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
539#define RT5651_G_IN2_R_RM_R_SFT 13
540#define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
541#define RT5651_G_IN1_R_RM_R_SFT 10
542#define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
543#define RT5651_G_BST3_RM_R_SFT 4
544#define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
545#define RT5651_G_BST2_RM_R_SFT 1
546
547/* REC Right Mixer Control 2 (0x3e) */
548#define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
549#define RT5651_G_BST1_RM_R_SFT 13
550#define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
551#define RT5651_G_OM_R_RM_R_SFT 10
552#define RT5651_M_IN2_R_RM_R (0x1 << 6)
553#define RT5651_M_IN2_R_RM_R_SFT 6
554#define RT5651_M_IN1_R_RM_R (0x1 << 5)
555#define RT5651_M_IN1_R_RM_R_SFT 5
556#define RT5651_M_BST3_RM_R (0x1 << 3)
557#define RT5651_M_BST3_RM_R_SFT 3
558#define RT5651_M_BST2_RM_R (0x1 << 2)
559#define RT5651_M_BST2_RM_R_SFT 2
560#define RT5651_M_BST1_RM_R (0x1 << 1)
561#define RT5651_M_BST1_RM_R_SFT 1
562#define RT5651_M_OM_R_RM_R (0x1)
563#define RT5651_M_OM_R_RM_R_SFT 0
564
565/* HPMIX Control (0x45) */
566#define RT5651_M_DAC1_HM (0x1 << 14)
567#define RT5651_M_DAC1_HM_SFT 14
568#define RT5651_M_HPVOL_HM (0x1 << 13)
569#define RT5651_M_HPVOL_HM_SFT 13
570#define RT5651_G_HPOMIX_MASK (0x1 << 12)
571#define RT5651_G_HPOMIX_SFT 12
572
573/* SPK Left Mixer Control (0x46) */
574#define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
575#define RT5651_G_RM_L_SM_L_SFT 14
576#define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
577#define RT5651_G_IN_L_SM_L_SFT 12
578#define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
579#define RT5651_G_DAC_L1_SM_L_SFT 10
580#define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
581#define RT5651_G_DAC_L2_SM_L_SFT 8
582#define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
583#define RT5651_G_OM_L_SM_L_SFT 6
584#define RT5651_M_RM_L_SM_L (0x1 << 5)
585#define RT5651_M_RM_L_SM_L_SFT 5
586#define RT5651_M_IN_L_SM_L (0x1 << 4)
587#define RT5651_M_IN_L_SM_L_SFT 4
588#define RT5651_M_DAC_L1_SM_L (0x1 << 3)
589#define RT5651_M_DAC_L1_SM_L_SFT 3
590#define RT5651_M_DAC_L2_SM_L (0x1 << 2)
591#define RT5651_M_DAC_L2_SM_L_SFT 2
592#define RT5651_M_OM_L_SM_L (0x1 << 1)
593#define RT5651_M_OM_L_SM_L_SFT 1
594
595/* SPK Right Mixer Control (0x47) */
596#define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
597#define RT5651_G_RM_R_SM_R_SFT 14
598#define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
599#define RT5651_G_IN_R_SM_R_SFT 12
600#define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
601#define RT5651_G_DAC_R1_SM_R_SFT 10
602#define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
603#define RT5651_G_DAC_R2_SM_R_SFT 8
604#define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
605#define RT5651_G_OM_R_SM_R_SFT 6
606#define RT5651_M_RM_R_SM_R (0x1 << 5)
607#define RT5651_M_RM_R_SM_R_SFT 5
608#define RT5651_M_IN_R_SM_R (0x1 << 4)
609#define RT5651_M_IN_R_SM_R_SFT 4
610#define RT5651_M_DAC_R1_SM_R (0x1 << 3)
611#define RT5651_M_DAC_R1_SM_R_SFT 3
612#define RT5651_M_DAC_R2_SM_R (0x1 << 2)
613#define RT5651_M_DAC_R2_SM_R_SFT 2
614#define RT5651_M_OM_R_SM_R (0x1 << 1)
615#define RT5651_M_OM_R_SM_R_SFT 1
616
617/* SPOLMIX Control (0x48) */
618#define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
619#define RT5651_M_DAC_R1_SPM_L_SFT 15
620#define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
621#define RT5651_M_DAC_L1_SPM_L_SFT 14
622#define RT5651_M_SV_R_SPM_L (0x1 << 13)
623#define RT5651_M_SV_R_SPM_L_SFT 13
624#define RT5651_M_SV_L_SPM_L (0x1 << 12)
625#define RT5651_M_SV_L_SPM_L_SFT 12
626#define RT5651_M_BST1_SPM_L (0x1 << 11)
627#define RT5651_M_BST1_SPM_L_SFT 11
628
629/* SPORMIX Control (0x49) */
630#define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
631#define RT5651_M_DAC_R1_SPM_R_SFT 13
632#define RT5651_M_SV_R_SPM_R (0x1 << 12)
633#define RT5651_M_SV_R_SPM_R_SFT 12
634#define RT5651_M_BST1_SPM_R (0x1 << 11)
635#define RT5651_M_BST1_SPM_R_SFT 11
636
637/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
638#define RT5651_SPO_CLSD_RATIO_MASK (0x7)
639#define RT5651_SPO_CLSD_RATIO_SFT 0
640
641/* Mono Output Mixer Control (0x4c) */
642#define RT5651_M_DAC_R2_MM (0x1 << 15)
643#define RT5651_M_DAC_R2_MM_SFT 15
644#define RT5651_M_DAC_L2_MM (0x1 << 14)
645#define RT5651_M_DAC_L2_MM_SFT 14
646#define RT5651_M_OV_R_MM (0x1 << 13)
647#define RT5651_M_OV_R_MM_SFT 13
648#define RT5651_M_OV_L_MM (0x1 << 12)
649#define RT5651_M_OV_L_MM_SFT 12
650#define RT5651_M_BST1_MM (0x1 << 11)
651#define RT5651_M_BST1_MM_SFT 11
652#define RT5651_G_MONOMIX_MASK (0x1 << 10)
653#define RT5651_G_MONOMIX_SFT 10
654
655/* Output Left Mixer Control 1 (0x4d) */
656#define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
657#define RT5651_G_BST2_OM_L_SFT 10
658#define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
659#define RT5651_G_BST1_OM_L_SFT 7
660#define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
661#define RT5651_G_IN1_L_OM_L_SFT 4
662#define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
663#define RT5651_G_RM_L_OM_L_SFT 1
664
665/* Output Left Mixer Control 2 (0x4e) */
666#define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
667#define RT5651_G_DAC_L1_OM_L_SFT 7
668#define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
669#define RT5651_G_IN2_L_OM_L_SFT 4
670
671/* Output Left Mixer Control 3 (0x4f) */
672#define RT5651_M_IN2_L_OM_L (0x1 << 9)
673#define RT5651_M_IN2_L_OM_L_SFT 9
674#define RT5651_M_BST2_OM_L (0x1 << 6)
675#define RT5651_M_BST2_OM_L_SFT 6
676#define RT5651_M_BST1_OM_L (0x1 << 5)
677#define RT5651_M_BST1_OM_L_SFT 5
678#define RT5651_M_IN1_L_OM_L (0x1 << 4)
679#define RT5651_M_IN1_L_OM_L_SFT 4
680#define RT5651_M_RM_L_OM_L (0x1 << 3)
681#define RT5651_M_RM_L_OM_L_SFT 3
682#define RT5651_M_DAC_L1_OM_L (0x1)
683#define RT5651_M_DAC_L1_OM_L_SFT 0
684
685/* Output Right Mixer Control 1 (0x50) */
686#define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
687#define RT5651_G_BST2_OM_R_SFT 10
688#define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
689#define RT5651_G_BST1_OM_R_SFT 7
690#define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
691#define RT5651_G_IN1_R_OM_R_SFT 4
692#define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
693#define RT5651_G_RM_R_OM_R_SFT 1
694
695/* Output Right Mixer Control 2 (0x51) */
696#define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
697#define RT5651_G_DAC_R1_OM_R_SFT 7
698#define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
699#define RT5651_G_IN2_R_OM_R_SFT 4
700
701/* Output Right Mixer Control 3 (0x52) */
702#define RT5651_M_IN2_R_OM_R (0x1 << 9)
703#define RT5651_M_IN2_R_OM_R_SFT 9
704#define RT5651_M_BST2_OM_R (0x1 << 6)
705#define RT5651_M_BST2_OM_R_SFT 6
706#define RT5651_M_BST1_OM_R (0x1 << 5)
707#define RT5651_M_BST1_OM_R_SFT 5
708#define RT5651_M_IN1_R_OM_R (0x1 << 4)
709#define RT5651_M_IN1_R_OM_R_SFT 4
710#define RT5651_M_RM_R_OM_R (0x1 << 3)
711#define RT5651_M_RM_R_OM_R_SFT 3
712#define RT5651_M_DAC_R1_OM_R (0x1)
713#define RT5651_M_DAC_R1_OM_R_SFT 0
714
715/* LOUT Mixer Control (0x53) */
716#define RT5651_M_DAC_L1_LM (0x1 << 15)
717#define RT5651_M_DAC_L1_LM_SFT 15
718#define RT5651_M_DAC_R1_LM (0x1 << 14)
719#define RT5651_M_DAC_R1_LM_SFT 14
720#define RT5651_M_OV_L_LM (0x1 << 13)
721#define RT5651_M_OV_L_LM_SFT 13
722#define RT5651_M_OV_R_LM (0x1 << 12)
723#define RT5651_M_OV_R_LM_SFT 12
724#define RT5651_G_LOUTMIX_MASK (0x1 << 11)
725#define RT5651_G_LOUTMIX_SFT 11
726
727/* Power Management for Digital 1 (0x61) */
728#define RT5651_PWR_I2S1 (0x1 << 15)
729#define RT5651_PWR_I2S1_BIT 15
730#define RT5651_PWR_I2S2 (0x1 << 14)
731#define RT5651_PWR_I2S2_BIT 14
732#define RT5651_PWR_DAC_L1 (0x1 << 12)
733#define RT5651_PWR_DAC_L1_BIT 12
734#define RT5651_PWR_DAC_R1 (0x1 << 11)
735#define RT5651_PWR_DAC_R1_BIT 11
736#define RT5651_PWR_ADC_L (0x1 << 2)
737#define RT5651_PWR_ADC_L_BIT 2
738#define RT5651_PWR_ADC_R (0x1 << 1)
739#define RT5651_PWR_ADC_R_BIT 1
740
741/* Power Management for Digital 2 (0x62) */
742#define RT5651_PWR_ADC_STO1_F (0x1 << 15)
743#define RT5651_PWR_ADC_STO1_F_BIT 15
744#define RT5651_PWR_ADC_STO2_F (0x1 << 14)
745#define RT5651_PWR_ADC_STO2_F_BIT 14
746#define RT5651_PWR_DAC_STO1_F (0x1 << 11)
747#define RT5651_PWR_DAC_STO1_F_BIT 11
748#define RT5651_PWR_DAC_STO2_F (0x1 << 10)
749#define RT5651_PWR_DAC_STO2_F_BIT 10
750#define RT5651_PWR_PDM (0x1 << 9)
751#define RT5651_PWR_PDM_BIT 9
752
753/* Power Management for Analog 1 (0x63) */
754#define RT5651_PWR_VREF1 (0x1 << 15)
755#define RT5651_PWR_VREF1_BIT 15
756#define RT5651_PWR_FV1 (0x1 << 14)
757#define RT5651_PWR_FV1_BIT 14
758#define RT5651_PWR_MB (0x1 << 13)
759#define RT5651_PWR_MB_BIT 13
760#define RT5651_PWR_LM (0x1 << 12)
761#define RT5651_PWR_LM_BIT 12
762#define RT5651_PWR_BG (0x1 << 11)
763#define RT5651_PWR_BG_BIT 11
764#define RT5651_PWR_HP_L (0x1 << 7)
765#define RT5651_PWR_HP_L_BIT 7
766#define RT5651_PWR_HP_R (0x1 << 6)
767#define RT5651_PWR_HP_R_BIT 6
768#define RT5651_PWR_HA (0x1 << 5)
769#define RT5651_PWR_HA_BIT 5
770#define RT5651_PWR_VREF2 (0x1 << 4)
771#define RT5651_PWR_VREF2_BIT 4
772#define RT5651_PWR_FV2 (0x1 << 3)
773#define RT5651_PWR_FV2_BIT 3
774#define RT5651_PWR_LDO (0x1 << 2)
775#define RT5651_PWR_LDO_BIT 2
776#define RT5651_PWR_LDO_DVO_MASK (0x3)
777#define RT5651_PWR_LDO_DVO_1_0V 0
778#define RT5651_PWR_LDO_DVO_1_1V 1
779#define RT5651_PWR_LDO_DVO_1_2V 2
780#define RT5651_PWR_LDO_DVO_1_3V 3
781
782/* Power Management for Analog 2 (0x64) */
783#define RT5651_PWR_BST1 (0x1 << 15)
784#define RT5651_PWR_BST1_BIT 15
785#define RT5651_PWR_BST2 (0x1 << 14)
786#define RT5651_PWR_BST2_BIT 14
787#define RT5651_PWR_BST3 (0x1 << 13)
788#define RT5651_PWR_BST3_BIT 13
789#define RT5651_PWR_MB1 (0x1 << 11)
790#define RT5651_PWR_MB1_BIT 11
791#define RT5651_PWR_PLL (0x1 << 9)
792#define RT5651_PWR_PLL_BIT 9
793#define RT5651_PWR_BST1_OP2 (0x1 << 5)
794#define RT5651_PWR_BST1_OP2_BIT 5
795#define RT5651_PWR_BST2_OP2 (0x1 << 4)
796#define RT5651_PWR_BST2_OP2_BIT 4
797#define RT5651_PWR_BST3_OP2 (0x1 << 3)
798#define RT5651_PWR_BST3_OP2_BIT 3
799#define RT5651_PWR_JD_M (0x1 << 2)
800#define RT5651_PWM_JD_M_BIT 2
801#define RT5651_PWR_JD2 (0x1 << 1)
802#define RT5651_PWM_JD2_BIT 1
803#define RT5651_PWR_JD3 (0x1)
804#define RT5651_PWM_JD3_BIT 0
805
806/* Power Management for Mixer (0x65) */
807#define RT5651_PWR_OM_L (0x1 << 15)
808#define RT5651_PWR_OM_L_BIT 15
809#define RT5651_PWR_OM_R (0x1 << 14)
810#define RT5651_PWR_OM_R_BIT 14
811#define RT5651_PWR_RM_L (0x1 << 11)
812#define RT5651_PWR_RM_L_BIT 11
813#define RT5651_PWR_RM_R (0x1 << 10)
814#define RT5651_PWR_RM_R_BIT 10
815
816/* Power Management for Volume (0x66) */
817#define RT5651_PWR_OV_L (0x1 << 13)
818#define RT5651_PWR_OV_L_BIT 13
819#define RT5651_PWR_OV_R (0x1 << 12)
820#define RT5651_PWR_OV_R_BIT 12
821#define RT5651_PWR_HV_L (0x1 << 11)
822#define RT5651_PWR_HV_L_BIT 11
823#define RT5651_PWR_HV_R (0x1 << 10)
824#define RT5651_PWR_HV_R_BIT 10
825#define RT5651_PWR_IN1_L (0x1 << 9)
826#define RT5651_PWR_IN1_L_BIT 9
827#define RT5651_PWR_IN1_R (0x1 << 8)
828#define RT5651_PWR_IN1_R_BIT 8
829#define RT5651_PWR_IN2_L (0x1 << 7)
830#define RT5651_PWR_IN2_L_BIT 7
831#define RT5651_PWR_IN2_R (0x1 << 6)
832#define RT5651_PWR_IN2_R_BIT 6
833
834/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
835#define RT5651_I2S_MS_MASK (0x1 << 15)
836#define RT5651_I2S_MS_SFT 15
837#define RT5651_I2S_MS_M (0x0 << 15)
838#define RT5651_I2S_MS_S (0x1 << 15)
839#define RT5651_I2S_O_CP_MASK (0x3 << 10)
840#define RT5651_I2S_O_CP_SFT 10
841#define RT5651_I2S_O_CP_OFF (0x0 << 10)
842#define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
843#define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
844#define RT5651_I2S_I_CP_MASK (0x3 << 8)
845#define RT5651_I2S_I_CP_SFT 8
846#define RT5651_I2S_I_CP_OFF (0x0 << 8)
847#define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
848#define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
849#define RT5651_I2S_BP_MASK (0x1 << 7)
850#define RT5651_I2S_BP_SFT 7
851#define RT5651_I2S_BP_NOR (0x0 << 7)
852#define RT5651_I2S_BP_INV (0x1 << 7)
853#define RT5651_I2S_DL_MASK (0x3 << 2)
854#define RT5651_I2S_DL_SFT 2
855#define RT5651_I2S_DL_16 (0x0 << 2)
856#define RT5651_I2S_DL_20 (0x1 << 2)
857#define RT5651_I2S_DL_24 (0x2 << 2)
858#define RT5651_I2S_DL_8 (0x3 << 2)
859#define RT5651_I2S_DF_MASK (0x3)
860#define RT5651_I2S_DF_SFT 0
861#define RT5651_I2S_DF_I2S (0x0)
862#define RT5651_I2S_DF_LEFT (0x1)
863#define RT5651_I2S_DF_PCM_A (0x2)
864#define RT5651_I2S_DF_PCM_B (0x3)
865
866/* ADC/DAC Clock Control 1 (0x73) */
867#define RT5651_I2S_PD1_MASK (0x7 << 12)
868#define RT5651_I2S_PD1_SFT 12
869#define RT5651_I2S_PD1_1 (0x0 << 12)
870#define RT5651_I2S_PD1_2 (0x1 << 12)
871#define RT5651_I2S_PD1_3 (0x2 << 12)
872#define RT5651_I2S_PD1_4 (0x3 << 12)
873#define RT5651_I2S_PD1_6 (0x4 << 12)
874#define RT5651_I2S_PD1_8 (0x5 << 12)
875#define RT5651_I2S_PD1_12 (0x6 << 12)
876#define RT5651_I2S_PD1_16 (0x7 << 12)
877#define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
878#define RT5651_I2S_BCLK_MS2_SFT 11
879#define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
880#define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
881#define RT5651_I2S_PD2_MASK (0x7 << 8)
882#define RT5651_I2S_PD2_SFT 8
883#define RT5651_I2S_PD2_1 (0x0 << 8)
884#define RT5651_I2S_PD2_2 (0x1 << 8)
885#define RT5651_I2S_PD2_3 (0x2 << 8)
886#define RT5651_I2S_PD2_4 (0x3 << 8)
887#define RT5651_I2S_PD2_6 (0x4 << 8)
888#define RT5651_I2S_PD2_8 (0x5 << 8)
889#define RT5651_I2S_PD2_12 (0x6 << 8)
890#define RT5651_I2S_PD2_16 (0x7 << 8)
891#define RT5651_DAC_OSR_MASK (0x3 << 2)
892#define RT5651_DAC_OSR_SFT 2
893#define RT5651_DAC_OSR_128 (0x0 << 2)
894#define RT5651_DAC_OSR_64 (0x1 << 2)
895#define RT5651_DAC_OSR_32 (0x2 << 2)
896#define RT5651_DAC_OSR_128_3 (0x3 << 2)
897#define RT5651_ADC_OSR_MASK (0x3)
898#define RT5651_ADC_OSR_SFT 0
899#define RT5651_ADC_OSR_128 (0x0)
900#define RT5651_ADC_OSR_64 (0x1)
901#define RT5651_ADC_OSR_32 (0x2)
902#define RT5651_ADC_OSR_128_3 (0x3)
903
904/* ADC/DAC Clock Control 2 (0x74) */
905#define RT5651_DAHPF_EN (0x1 << 11)
906#define RT5651_DAHPF_EN_SFT 11
907#define RT5651_ADHPF_EN (0x1 << 10)
908#define RT5651_ADHPF_EN_SFT 10
909
910/* Digital Microphone Control (0x75) */
911#define RT5651_DMIC_1_EN_MASK (0x1 << 15)
912#define RT5651_DMIC_1_EN_SFT 15
913#define RT5651_DMIC_1_DIS (0x0 << 15)
914#define RT5651_DMIC_1_EN (0x1 << 15)
915#define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
916#define RT5651_DMIC_1L_LH_SFT 13
917#define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
918#define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
919#define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
920#define RT5651_DMIC_1R_LH_SFT 12
921#define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
922#define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
923#define RT5651_DMIC_1_DP_MASK (0x3 << 10)
924#define RT5651_DMIC_1_DP_SFT 10
925#define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
926#define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
927#define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
928#define RT5651_DMIC_CLK_MASK (0x7 << 5)
929#define RT5651_DMIC_CLK_SFT 5
930
931/* TDM Control 1 (0x77) */
932#define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
933#define RT5651_TDM_INTEL_SEL_SFT 15
934#define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
935#define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
936#define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
937#define RT5651_TDM_MODE_SEL_SFT 14
938#define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
939#define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
940#define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
941#define RT5651_TDM_CH_NUM_SEL_SFT 12
942#define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
943#define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
944#define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
945#define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
946#define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
947#define RT5651_TDM_CH_LEN_SEL_SFT 10
948#define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
949#define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
950#define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
951#define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
952#define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
953#define RT5651_TDM_ADC_SEL_SFT 9
954#define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
955#define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
956#define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
957#define RT5651_TDM_ADC_START_SEL_SFT 8
958#define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
959#define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
960#define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
961#define RT5651_TDM_I2S_CH2_SEL_SFT 6
962#define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
963#define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
964#define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
965#define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
966#define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
967#define RT5651_TDM_I2S_CH4_SEL_SFT 4
968#define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
969#define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
970#define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
971#define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
972#define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
973#define RT5651_TDM_I2S_CH6_SEL_SFT 2
974#define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
975#define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
976#define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
977#define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
978#define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
979#define RT5651_TDM_I2S_CH8_SEL_SFT 0
980#define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
981#define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
982#define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
983#define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
984
985/* TDM Control 2 (0x78) */
986#define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
987#define RT5651_TDM_LRCK_POL_SEL_SFT 15
988#define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
989#define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
990#define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
991#define RT5651_TDM_CH_VAL_SEL_SFT 14
992#define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
993#define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
994#define RT5651_TDM_CH_VAL_EN (0x1 << 13)
995#define RT5651_TDM_CH_VAL_SFT 13
996#define RT5651_TDM_LPBK_EN (0x1 << 12)
997#define RT5651_TDM_LPBK_SFT 12
998#define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
999#define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
1000#define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
1001#define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1002#define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1003#define RT5651_TDM_END_EDGE_SEL_SFT 10
1004#define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1005#define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1006#define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1007#define RT5651_TDM_END_EDGE_EN_SFT 9
1008#define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1009#define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1010#define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1011#define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1012#define RT5651_M_TDM2_L (0x1 << 7)
1013#define RT5651_M_TDM2_L_SFT 7
1014#define RT5651_M_TDM2_R (0x1 << 6)
1015#define RT5651_M_TDM2_R_SFT 6
1016#define RT5651_M_TDM4_L (0x1 << 5)
1017#define RT5651_M_TDM4_L_SFT 5
1018#define RT5651_M_TDM4_R (0x1 << 4)
1019#define RT5651_M_TDM4_R_SFT 4
1020
1021/* TDM Control 3 (0x79) */
1022#define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1023#define RT5651_CH2_L_SEL_SFT 12
1024#define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1025#define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1026#define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1027#define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1028#define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1029#define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1030#define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1031#define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1032#define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1033#define RT5651_CH2_R_SEL_SFT 8
1034#define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1035#define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1036#define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1037#define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1038#define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1039#define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1040#define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1041#define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1042#define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1043#define RT5651_CH4_L_SEL_SFT 4
1044#define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1045#define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1046#define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1047#define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1048#define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1049#define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1050#define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1051#define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1052#define RT5651_CH4_R_SEL_MASK (0x7)
1053#define RT5651_CH4_R_SEL_SFT 0
1054#define RT5651_CH4_R_SEL_SL0 (0x0)
1055#define RT5651_CH4_R_SEL_SL1 (0x1)
1056#define RT5651_CH4_R_SEL_SL2 (0x2)
1057#define RT5651_CH4_R_SEL_SL3 (0x3)
1058#define RT5651_CH4_R_SEL_SL4 (0x4)
1059#define RT5651_CH4_R_SEL_SL5 (0x5)
1060#define RT5651_CH4_R_SEL_SL6 (0x6)
1061#define RT5651_CH4_R_SEL_SL7 (0x7)
1062
1063/* Global Clock Control (0x80) */
1064#define RT5651_SCLK_SRC_MASK (0x3 << 14)
1065#define RT5651_SCLK_SRC_SFT 14
1066#define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1067#define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1068#define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1069#define RT5651_PLL1_SRC_MASK (0x3 << 12)
1070#define RT5651_PLL1_SRC_SFT 12
1071#define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1072#define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1073#define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1074#define RT5651_PLL1_PD_MASK (0x1 << 3)
1075#define RT5651_PLL1_PD_SFT 3
1076#define RT5651_PLL1_PD_1 (0x0 << 3)
1077#define RT5651_PLL1_PD_2 (0x1 << 3)
1078
1079#define RT5651_PLL_INP_MAX 40000000
1080#define RT5651_PLL_INP_MIN 256000
1081/* PLL M/N/K Code Control 1 (0x81) */
1082#define RT5651_PLL_N_MAX 0x1ff
1083#define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1084#define RT5651_PLL_N_SFT 7
1085#define RT5651_PLL_K_MAX 0x1f
1086#define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
1087#define RT5651_PLL_K_SFT 0
1088
1089/* PLL M/N/K Code Control 2 (0x82) */
1090#define RT5651_PLL_M_MAX 0xf
1091#define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1092#define RT5651_PLL_M_SFT 12
1093#define RT5651_PLL_M_BP (0x1 << 11)
1094#define RT5651_PLL_M_BP_SFT 11
1095
1096/* PLL tracking mode 1 (0x83) */
1097#define RT5651_STO1_T_MASK (0x1 << 15)
1098#define RT5651_STO1_T_SFT 15
1099#define RT5651_STO1_T_SCLK (0x0 << 15)
1100#define RT5651_STO1_T_LRCK1 (0x1 << 15)
1101#define RT5651_STO2_T_MASK (0x1 << 12)
1102#define RT5651_STO2_T_SFT 12
1103#define RT5651_STO2_T_I2S2 (0x0 << 12)
1104#define RT5651_STO2_T_LRCK2 (0x1 << 12)
1105#define RT5651_ASRC2_REF_MASK (0x1 << 11)
1106#define RT5651_ASRC2_REF_SFT 11
1107#define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1108#define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1109#define RT5651_DMIC_1_M_MASK (0x1 << 9)
1110#define RT5651_DMIC_1_M_SFT 9
1111#define RT5651_DMIC_1_M_NOR (0x0 << 9)
1112#define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1113
1114/* PLL tracking mode 2 (0x84) */
1115#define RT5651_STO1_ASRC_EN (0x1 << 15)
1116#define RT5651_STO1_ASRC_EN_SFT 15
1117#define RT5651_STO2_ASRC_EN (0x1 << 14)
1118#define RT5651_STO2_ASRC_EN_SFT 14
1119#define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1120#define RT5651_STO1_DAC_M_SFT 13
1121#define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1122#define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1123#define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1124#define RT5651_STO2_DAC_M_SFT 12
1125#define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1126#define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1127#define RT5651_ADC_M_MASK (0x1 << 11)
1128#define RT5651_ADC_M_SFT 11
1129#define RT5651_ADC_M_NOR (0x0 << 11)
1130#define RT5651_ADC_M_ASRC (0x1 << 11)
1131#define RT5651_I2S1_R_D_MASK (0x1 << 4)
1132#define RT5651_I2S1_R_D_SFT 4
1133#define RT5651_I2S1_R_D_DIS (0x0 << 4)
1134#define RT5651_I2S1_R_D_EN (0x1 << 4)
1135#define RT5651_I2S2_R_D_MASK (0x1 << 3)
1136#define RT5651_I2S2_R_D_SFT 3
1137#define RT5651_I2S2_R_D_DIS (0x0 << 3)
1138#define RT5651_I2S2_R_D_EN (0x1 << 3)
1139#define RT5651_PRE_SCLK_MASK (0x3)
1140#define RT5651_PRE_SCLK_SFT 0
1141#define RT5651_PRE_SCLK_512 (0x0)
1142#define RT5651_PRE_SCLK_1024 (0x1)
1143#define RT5651_PRE_SCLK_2048 (0x2)
1144
1145/* PLL tracking mode 3 (0x85) */
1146#define RT5651_I2S1_RATE_MASK (0xf << 12)
1147#define RT5651_I2S1_RATE_SFT 12
1148#define RT5651_I2S2_RATE_MASK (0xf << 8)
1149#define RT5651_I2S2_RATE_SFT 8
1150#define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1151#define RT5651_G_ASRC_LP_SFT 3
1152#define RT5651_ASRC_LP_F_M (0x1 << 2)
1153#define RT5651_ASRC_LP_F_SFT 2
1154#define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1155#define RT5651_ASRC_LP_F_SB (0x1 << 2)
1156#define RT5651_FTK_PH_DET_MASK (0x3)
1157#define RT5651_FTK_PH_DET_SFT 0
1158#define RT5651_FTK_PH_DET_DIV1 (0x0)
1159#define RT5651_FTK_PH_DET_DIV2 (0x1)
1160#define RT5651_FTK_PH_DET_DIV4 (0x2)
1161#define RT5651_FTK_PH_DET_DIV8 (0x3)
1162
1163/*PLL tracking mode 6 (0x89) */
1164#define RT5651_I2S1_PD_MASK (0x7 << 12)
1165#define RT5651_I2S1_PD_SFT 12
1166#define RT5651_I2S2_PD_MASK (0x7 << 8)
1167#define RT5651_I2S2_PD_SFT 8
1168
1169/*PLL tracking mode 7 (0x8a) */
1170#define RT5651_FSI1_RATE_MASK (0xf << 12)
1171#define RT5651_FSI1_RATE_SFT 12
1172#define RT5651_FSI2_RATE_MASK (0xf << 8)
1173#define RT5651_FSI2_RATE_SFT 8
1174
1175/* HPOUT Over Current Detection (0x8b) */
1176#define RT5651_HP_OVCD_MASK (0x1 << 10)
1177#define RT5651_HP_OVCD_SFT 10
1178#define RT5651_HP_OVCD_DIS (0x0 << 10)
1179#define RT5651_HP_OVCD_EN (0x1 << 10)
1180#define RT5651_HP_OC_TH_MASK (0x3 << 8)
1181#define RT5651_HP_OC_TH_SFT 8
1182#define RT5651_HP_OC_TH_90 (0x0 << 8)
1183#define RT5651_HP_OC_TH_105 (0x1 << 8)
1184#define RT5651_HP_OC_TH_120 (0x2 << 8)
1185#define RT5651_HP_OC_TH_135 (0x3 << 8)
1186
1187/* Depop Mode Control 1 (0x8e) */
1188#define RT5651_SMT_TRIG_MASK (0x1 << 15)
1189#define RT5651_SMT_TRIG_SFT 15
1190#define RT5651_SMT_TRIG_DIS (0x0 << 15)
1191#define RT5651_SMT_TRIG_EN (0x1 << 15)
1192#define RT5651_HP_L_SMT_MASK (0x1 << 9)
1193#define RT5651_HP_L_SMT_SFT 9
1194#define RT5651_HP_L_SMT_DIS (0x0 << 9)
1195#define RT5651_HP_L_SMT_EN (0x1 << 9)
1196#define RT5651_HP_R_SMT_MASK (0x1 << 8)
1197#define RT5651_HP_R_SMT_SFT 8
1198#define RT5651_HP_R_SMT_DIS (0x0 << 8)
1199#define RT5651_HP_R_SMT_EN (0x1 << 8)
1200#define RT5651_HP_CD_PD_MASK (0x1 << 7)
1201#define RT5651_HP_CD_PD_SFT 7
1202#define RT5651_HP_CD_PD_DIS (0x0 << 7)
1203#define RT5651_HP_CD_PD_EN (0x1 << 7)
1204#define RT5651_RSTN_MASK (0x1 << 6)
1205#define RT5651_RSTN_SFT 6
1206#define RT5651_RSTN_DIS (0x0 << 6)
1207#define RT5651_RSTN_EN (0x1 << 6)
1208#define RT5651_RSTP_MASK (0x1 << 5)
1209#define RT5651_RSTP_SFT 5
1210#define RT5651_RSTP_DIS (0x0 << 5)
1211#define RT5651_RSTP_EN (0x1 << 5)
1212#define RT5651_HP_CO_MASK (0x1 << 4)
1213#define RT5651_HP_CO_SFT 4
1214#define RT5651_HP_CO_DIS (0x0 << 4)
1215#define RT5651_HP_CO_EN (0x1 << 4)
1216#define RT5651_HP_CP_MASK (0x1 << 3)
1217#define RT5651_HP_CP_SFT 3
1218#define RT5651_HP_CP_PD (0x0 << 3)
1219#define RT5651_HP_CP_PU (0x1 << 3)
1220#define RT5651_HP_SG_MASK (0x1 << 2)
1221#define RT5651_HP_SG_SFT 2
1222#define RT5651_HP_SG_DIS (0x0 << 2)
1223#define RT5651_HP_SG_EN (0x1 << 2)
1224#define RT5651_HP_DP_MASK (0x1 << 1)
1225#define RT5651_HP_DP_SFT 1
1226#define RT5651_HP_DP_PD (0x0 << 1)
1227#define RT5651_HP_DP_PU (0x1 << 1)
1228#define RT5651_HP_CB_MASK (0x1)
1229#define RT5651_HP_CB_SFT 0
1230#define RT5651_HP_CB_PD (0x0)
1231#define RT5651_HP_CB_PU (0x1)
1232
1233/* Depop Mode Control 2 (0x8f) */
1234#define RT5651_DEPOP_MASK (0x1 << 13)
1235#define RT5651_DEPOP_SFT 13
1236#define RT5651_DEPOP_AUTO (0x0 << 13)
1237#define RT5651_DEPOP_MAN (0x1 << 13)
1238#define RT5651_RAMP_MASK (0x1 << 12)
1239#define RT5651_RAMP_SFT 12
1240#define RT5651_RAMP_DIS (0x0 << 12)
1241#define RT5651_RAMP_EN (0x1 << 12)
1242#define RT5651_BPS_MASK (0x1 << 11)
1243#define RT5651_BPS_SFT 11
1244#define RT5651_BPS_DIS (0x0 << 11)
1245#define RT5651_BPS_EN (0x1 << 11)
1246#define RT5651_FAST_UPDN_MASK (0x1 << 10)
1247#define RT5651_FAST_UPDN_SFT 10
1248#define RT5651_FAST_UPDN_DIS (0x0 << 10)
1249#define RT5651_FAST_UPDN_EN (0x1 << 10)
1250#define RT5651_MRES_MASK (0x3 << 8)
1251#define RT5651_MRES_SFT 8
1252#define RT5651_MRES_15MO (0x0 << 8)
1253#define RT5651_MRES_25MO (0x1 << 8)
1254#define RT5651_MRES_35MO (0x2 << 8)
1255#define RT5651_MRES_45MO (0x3 << 8)
1256#define RT5651_VLO_MASK (0x1 << 7)
1257#define RT5651_VLO_SFT 7
1258#define RT5651_VLO_3V (0x0 << 7)
1259#define RT5651_VLO_32V (0x1 << 7)
1260#define RT5651_DIG_DP_MASK (0x1 << 6)
1261#define RT5651_DIG_DP_SFT 6
1262#define RT5651_DIG_DP_DIS (0x0 << 6)
1263#define RT5651_DIG_DP_EN (0x1 << 6)
1264#define RT5651_DP_TH_MASK (0x3 << 4)
1265#define RT5651_DP_TH_SFT 4
1266
1267/* Depop Mode Control 3 (0x90) */
1268#define RT5651_CP_SYS_MASK (0x7 << 12)
1269#define RT5651_CP_SYS_SFT 12
1270#define RT5651_CP_FQ1_MASK (0x7 << 8)
1271#define RT5651_CP_FQ1_SFT 8
1272#define RT5651_CP_FQ2_MASK (0x7 << 4)
1273#define RT5651_CP_FQ2_SFT 4
1274#define RT5651_CP_FQ3_MASK (0x7)
1275#define RT5651_CP_FQ3_SFT 0
1276#define RT5651_CP_FQ_1_5_KHZ 0
1277#define RT5651_CP_FQ_3_KHZ 1
1278#define RT5651_CP_FQ_6_KHZ 2
1279#define RT5651_CP_FQ_12_KHZ 3
1280#define RT5651_CP_FQ_24_KHZ 4
1281#define RT5651_CP_FQ_48_KHZ 5
1282#define RT5651_CP_FQ_96_KHZ 6
1283#define RT5651_CP_FQ_192_KHZ 7
1284
1285/* HPOUT charge pump (0x91) */
1286#define RT5651_OSW_L_MASK (0x1 << 11)
1287#define RT5651_OSW_L_SFT 11
1288#define RT5651_OSW_L_DIS (0x0 << 11)
1289#define RT5651_OSW_L_EN (0x1 << 11)
1290#define RT5651_OSW_R_MASK (0x1 << 10)
1291#define RT5651_OSW_R_SFT 10
1292#define RT5651_OSW_R_DIS (0x0 << 10)
1293#define RT5651_OSW_R_EN (0x1 << 10)
1294#define RT5651_PM_HP_MASK (0x3 << 8)
1295#define RT5651_PM_HP_SFT 8
1296#define RT5651_PM_HP_LV (0x0 << 8)
1297#define RT5651_PM_HP_MV (0x1 << 8)
1298#define RT5651_PM_HP_HV (0x2 << 8)
1299#define RT5651_IB_HP_MASK (0x3 << 6)
1300#define RT5651_IB_HP_SFT 6
1301#define RT5651_IB_HP_125IL (0x0 << 6)
1302#define RT5651_IB_HP_25IL (0x1 << 6)
1303#define RT5651_IB_HP_5IL (0x2 << 6)
1304#define RT5651_IB_HP_1IL (0x3 << 6)
1305
1306/* Micbias Control (0x93) */
1307#define RT5651_MIC1_BS_MASK (0x1 << 15)
1308#define RT5651_MIC1_BS_SFT 15
1309#define RT5651_MIC1_BS_9AV (0x0 << 15)
1310#define RT5651_MIC1_BS_75AV (0x1 << 15)
1311#define RT5651_MIC1_CLK_MASK (0x1 << 13)
1312#define RT5651_MIC1_CLK_SFT 13
1313#define RT5651_MIC1_CLK_DIS (0x0 << 13)
1314#define RT5651_MIC1_CLK_EN (0x1 << 13)
1315#define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1316#define RT5651_MIC1_OVCD_SFT 11
1317#define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1318#define RT5651_MIC1_OVCD_EN (0x1 << 11)
1319#define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1320#define RT5651_MIC1_OVTH_SFT 9
1321#define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1322#define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1323#define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1324#define RT5651_PWR_MB_MASK (0x1 << 5)
1325#define RT5651_PWR_MB_SFT 5
1326#define RT5651_PWR_MB_PD (0x0 << 5)
1327#define RT5651_PWR_MB_PU (0x1 << 5)
1328#define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1329#define RT5651_PWR_CLK12M_SFT 4
1330#define RT5651_PWR_CLK12M_PD (0x0 << 4)
1331#define RT5651_PWR_CLK12M_PU (0x1 << 4)
1332
1333/* Analog JD Control 1 (0x94) */
1334#define RT5651_JD2_CMP_MASK (0x7 << 12)
1335#define RT5651_JD2_CMP_SFT 12
1336#define RT5651_JD_PU (0x1 << 11)
1337#define RT5651_JD_PU_SFT 11
1338#define RT5651_JD_PD (0x1 << 10)
1339#define RT5651_JD_PD_SFT 10
1340#define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1341#define RT5651_JD_MODE_SEL_SFT 8
1342#define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1343#define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1344#define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1345#define RT5651_JD_M_CMP (0x7 << 4)
1346#define RT5651_JD_M_CMP_SFT 4
1347#define RT5651_JD_M_PU (0x1 << 3)
1348#define RT5651_JD_M_PU_SFT 3
1349#define RT5651_JD_M_PD (0x1 << 2)
1350#define RT5651_JD_M_PD_SFT 2
1351#define RT5651_JD_M_MODE_SEL_MASK (0x3)
1352#define RT5651_JD_M_MODE_SEL_SFT 0
1353#define RT5651_JD_M_MODE_SEL_M0 (0x0)
1354#define RT5651_JD_M_MODE_SEL_M1 (0x1)
1355#define RT5651_JD_M_MODE_SEL_M2 (0x2)
1356
1357/* Analog JD Control 2 (0x95) */
1358#define RT5651_JD3_CMP_MASK (0x7 << 12)
1359#define RT5651_JD3_CMP_SFT 12
1360
1361/* EQ Control 1 (0xb0) */
1362#define RT5651_EQ_SRC_MASK (0x1 << 15)
1363#define RT5651_EQ_SRC_SFT 15
1364#define RT5651_EQ_SRC_DAC (0x0 << 15)
1365#define RT5651_EQ_SRC_ADC (0x1 << 15)
1366#define RT5651_EQ_UPD (0x1 << 14)
1367#define RT5651_EQ_UPD_BIT 14
1368#define RT5651_EQ_CD_MASK (0x1 << 13)
1369#define RT5651_EQ_CD_SFT 13
1370#define RT5651_EQ_CD_DIS (0x0 << 13)
1371#define RT5651_EQ_CD_EN (0x1 << 13)
1372#define RT5651_EQ_DITH_MASK (0x3 << 8)
1373#define RT5651_EQ_DITH_SFT 8
1374#define RT5651_EQ_DITH_NOR (0x0 << 8)
1375#define RT5651_EQ_DITH_LSB (0x1 << 8)
1376#define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1377#define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1378#define RT5651_EQ_CD_F (0x1 << 7)
1379#define RT5651_EQ_CD_F_BIT 7
1380#define RT5651_EQ_STA_HP2 (0x1 << 6)
1381#define RT5651_EQ_STA_HP2_BIT 6
1382#define RT5651_EQ_STA_HP1 (0x1 << 5)
1383#define RT5651_EQ_STA_HP1_BIT 5
1384#define RT5651_EQ_STA_BP4 (0x1 << 4)
1385#define RT5651_EQ_STA_BP4_BIT 4
1386#define RT5651_EQ_STA_BP3 (0x1 << 3)
1387#define RT5651_EQ_STA_BP3_BIT 3
1388#define RT5651_EQ_STA_BP2 (0x1 << 2)
1389#define RT5651_EQ_STA_BP2_BIT 2
1390#define RT5651_EQ_STA_BP1 (0x1 << 1)
1391#define RT5651_EQ_STA_BP1_BIT 1
1392#define RT5651_EQ_STA_LP (0x1)
1393#define RT5651_EQ_STA_LP_BIT 0
1394
1395/* EQ Control 2 (0xb1) */
1396#define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1397#define RT5651_EQ_HPF1_M_SFT 8
1398#define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1399#define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1400#define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1401#define RT5651_EQ_LPF1_M_SFT 7
1402#define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1403#define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1404#define RT5651_EQ_HPF2_MASK (0x1 << 6)
1405#define RT5651_EQ_HPF2_SFT 6
1406#define RT5651_EQ_HPF2_DIS (0x0 << 6)
1407#define RT5651_EQ_HPF2_EN (0x1 << 6)
1408#define RT5651_EQ_HPF1_MASK (0x1 << 5)
1409#define RT5651_EQ_HPF1_SFT 5
1410#define RT5651_EQ_HPF1_DIS (0x0 << 5)
1411#define RT5651_EQ_HPF1_EN (0x1 << 5)
1412#define RT5651_EQ_BPF4_MASK (0x1 << 4)
1413#define RT5651_EQ_BPF4_SFT 4
1414#define RT5651_EQ_BPF4_DIS (0x0 << 4)
1415#define RT5651_EQ_BPF4_EN (0x1 << 4)
1416#define RT5651_EQ_BPF3_MASK (0x1 << 3)
1417#define RT5651_EQ_BPF3_SFT 3
1418#define RT5651_EQ_BPF3_DIS (0x0 << 3)
1419#define RT5651_EQ_BPF3_EN (0x1 << 3)
1420#define RT5651_EQ_BPF2_MASK (0x1 << 2)
1421#define RT5651_EQ_BPF2_SFT 2
1422#define RT5651_EQ_BPF2_DIS (0x0 << 2)
1423#define RT5651_EQ_BPF2_EN (0x1 << 2)
1424#define RT5651_EQ_BPF1_MASK (0x1 << 1)
1425#define RT5651_EQ_BPF1_SFT 1
1426#define RT5651_EQ_BPF1_DIS (0x0 << 1)
1427#define RT5651_EQ_BPF1_EN (0x1 << 1)
1428#define RT5651_EQ_LPF_MASK (0x1)
1429#define RT5651_EQ_LPF_SFT 0
1430#define RT5651_EQ_LPF_DIS (0x0)
1431#define RT5651_EQ_LPF_EN (0x1)
1432#define RT5651_EQ_CTRL_MASK (0x7f)
1433
1434/* Memory Test (0xb2) */
1435#define RT5651_MT_MASK (0x1 << 15)
1436#define RT5651_MT_SFT 15
1437#define RT5651_MT_DIS (0x0 << 15)
1438#define RT5651_MT_EN (0x1 << 15)
1439
1440/* ALC Control 1 (0xb4) */
1441#define RT5651_ALC_P_MASK (0x1 << 15)
1442#define RT5651_ALC_P_SFT 15
1443#define RT5651_ALC_P_DAC (0x0 << 15)
1444#define RT5651_ALC_P_ADC (0x1 << 15)
1445#define RT5651_ALC_MASK (0x1 << 14)
1446#define RT5651_ALC_SFT 14
1447#define RT5651_ALC_DIS (0x0 << 14)
1448#define RT5651_ALC_EN (0x1 << 14)
1449#define RT5651_ALC_UPD (0x1 << 13)
1450#define RT5651_ALC_UPD_BIT 13
1451#define RT5651_ALC_AR_MASK (0x1f << 8)
1452#define RT5651_ALC_AR_SFT 8
1453#define RT5651_ALC_R_MASK (0x7 << 5)
1454#define RT5651_ALC_R_SFT 5
1455#define RT5651_ALC_R_48K (0x1 << 5)
1456#define RT5651_ALC_R_96K (0x2 << 5)
1457#define RT5651_ALC_R_192K (0x3 << 5)
1458#define RT5651_ALC_R_441K (0x5 << 5)
1459#define RT5651_ALC_R_882K (0x6 << 5)
1460#define RT5651_ALC_R_1764K (0x7 << 5)
1461#define RT5651_ALC_RC_MASK (0x1f)
1462#define RT5651_ALC_RC_SFT 0
1463
1464/* ALC Control 2 (0xb5) */
1465#define RT5651_ALC_POB_MASK (0x3f << 8)
1466#define RT5651_ALC_POB_SFT 8
1467#define RT5651_ALC_DRC_MASK (0x1 << 7)
1468#define RT5651_ALC_DRC_SFT 7
1469#define RT5651_ALC_DRC_DIS (0x0 << 7)
1470#define RT5651_ALC_DRC_EN (0x1 << 7)
1471#define RT5651_ALC_CPR_MASK (0x3 << 5)
1472#define RT5651_ALC_CPR_SFT 5
1473#define RT5651_ALC_CPR_1_1 (0x0 << 5)
1474#define RT5651_ALC_CPR_1_2 (0x1 << 5)
1475#define RT5651_ALC_CPR_1_4 (0x2 << 5)
1476#define RT5651_ALC_CPR_1_8 (0x3 << 5)
1477#define RT5651_ALC_PRB_MASK (0x1f)
1478#define RT5651_ALC_PRB_SFT 0
1479
1480/* ALC Control 3 (0xb6) */
1481#define RT5651_ALC_NGB_MASK (0xf << 12)
1482#define RT5651_ALC_NGB_SFT 12
1483#define RT5651_ALC_TAR_MASK (0x1f << 7)
1484#define RT5651_ALC_TAR_SFT 7
1485#define RT5651_ALC_NG_MASK (0x1 << 6)
1486#define RT5651_ALC_NG_SFT 6
1487#define RT5651_ALC_NG_DIS (0x0 << 6)
1488#define RT5651_ALC_NG_EN (0x1 << 6)
1489#define RT5651_ALC_NGH_MASK (0x1 << 5)
1490#define RT5651_ALC_NGH_SFT 5
1491#define RT5651_ALC_NGH_DIS (0x0 << 5)
1492#define RT5651_ALC_NGH_EN (0x1 << 5)
1493#define RT5651_ALC_NGT_MASK (0x1f)
1494#define RT5651_ALC_NGT_SFT 0
1495
1496/* Jack Detect Control 1 (0xbb) */
1497#define RT5651_JD_MASK (0x7 << 13)
1498#define RT5651_JD_SFT 13
1499#define RT5651_JD_DIS (0x0 << 13)
1500#define RT5651_JD_GPIO1 (0x1 << 13)
1501#define RT5651_JD_GPIO2 (0x2 << 13)
1502#define RT5651_JD_GPIO3 (0x3 << 13)
1503#define RT5651_JD_GPIO4 (0x4 << 13)
1504#define RT5651_JD_GPIO5 (0x5 << 13)
1505#define RT5651_JD_GPIO6 (0x6 << 13)
1506#define RT5651_JD_HP_MASK (0x1 << 11)
1507#define RT5651_JD_HP_SFT 11
1508#define RT5651_JD_HP_DIS (0x0 << 11)
1509#define RT5651_JD_HP_EN (0x1 << 11)
1510#define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1511#define RT5651_JD_HP_TRG_SFT 10
1512#define RT5651_JD_HP_TRG_LO (0x0 << 10)
1513#define RT5651_JD_HP_TRG_HI (0x1 << 10)
1514#define RT5651_JD_SPL_MASK (0x1 << 9)
1515#define RT5651_JD_SPL_SFT 9
1516#define RT5651_JD_SPL_DIS (0x0 << 9)
1517#define RT5651_JD_SPL_EN (0x1 << 9)
1518#define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1519#define RT5651_JD_SPL_TRG_SFT 8
1520#define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1521#define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1522#define RT5651_JD_SPR_MASK (0x1 << 7)
1523#define RT5651_JD_SPR_SFT 7
1524#define RT5651_JD_SPR_DIS (0x0 << 7)
1525#define RT5651_JD_SPR_EN (0x1 << 7)
1526#define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1527#define RT5651_JD_SPR_TRG_SFT 6
1528#define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1529#define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1530#define RT5651_JD_LO_MASK (0x1 << 3)
1531#define RT5651_JD_LO_SFT 3
1532#define RT5651_JD_LO_DIS (0x0 << 3)
1533#define RT5651_JD_LO_EN (0x1 << 3)
1534#define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1535#define RT5651_JD_LO_TRG_SFT 2
1536#define RT5651_JD_LO_TRG_LO (0x0 << 2)
1537#define RT5651_JD_LO_TRG_HI (0x1 << 2)
1538
1539/* Jack Detect Control 2 (0xbc) */
1540#define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1541#define RT5651_JD_TRG_SEL_SFT 9
1542#define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1543#define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1544#define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1545#define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1546#define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1547#define RT5651_JD3_IRQ_EN (0x1 << 8)
1548#define RT5651_JD3_IRQ_EN_SFT 8
1549#define RT5651_JD3_EN_STKY (0x1 << 7)
1550#define RT5651_JD3_EN_STKY_SFT 7
1551#define RT5651_JD3_INV (0x1 << 6)
1552#define RT5651_JD3_INV_SFT 6
1553
1554/* IRQ Control 1 (0xbd) */
1555#define RT5651_IRQ_JD_MASK (0x1 << 15)
1556#define RT5651_IRQ_JD_SFT 15
1557#define RT5651_IRQ_JD_BP (0x0 << 15)
1558#define RT5651_IRQ_JD_NOR (0x1 << 15)
1559#define RT5651_JD_STKY_MASK (0x1 << 13)
1560#define RT5651_JD_STKY_SFT 13
1561#define RT5651_JD_STKY_DIS (0x0 << 13)
1562#define RT5651_JD_STKY_EN (0x1 << 13)
1563#define RT5651_JD_P_MASK (0x1 << 11)
1564#define RT5651_JD_P_SFT 11
1565#define RT5651_JD_P_NOR (0x0 << 11)
1566#define RT5651_JD_P_INV (0x1 << 11)
1567#define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1568#define RT5651_JD1_1_IRQ_EN_SFT 9
1569#define RT5651_JD1_1_EN_STKY (0x1 << 8)
1570#define RT5651_JD1_1_EN_STKY_SFT 8
1571#define RT5651_JD1_1_INV (0x1 << 7)
1572#define RT5651_JD1_1_INV_SFT 7
1573#define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1574#define RT5651_JD1_2_IRQ_EN_SFT 6
1575#define RT5651_JD1_2_EN_STKY (0x1 << 5)
1576#define RT5651_JD1_2_EN_STKY_SFT 5
1577#define RT5651_JD1_2_INV (0x1 << 4)
1578#define RT5651_JD1_2_INV_SFT 4
1579#define RT5651_JD2_IRQ_EN (0x1 << 3)
1580#define RT5651_JD2_IRQ_EN_SFT 3
1581#define RT5651_JD2_EN_STKY (0x1 << 2)
1582#define RT5651_JD2_EN_STKY_SFT 2
1583#define RT5651_JD2_INV (0x1 << 1)
1584#define RT5651_JD2_INV_SFT 1
1585
1586/* IRQ Control 2 (0xbe) */
1587#define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1588#define RT5651_IRQ_MB1_OC_SFT 15
1589#define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1590#define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1591#define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1592#define RT5651_MB1_OC_STKY_SFT 11
1593#define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1594#define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1595#define RT5651_MB1_OC_P_MASK (0x1 << 7)
1596#define RT5651_MB1_OC_P_SFT 7
1597#define RT5651_MB1_OC_P_NOR (0x0 << 7)
1598#define RT5651_MB1_OC_P_INV (0x1 << 7)
1599#define RT5651_MB2_OC_P_MASK (0x1 << 6)
1600#define RT5651_MB1_OC_CLR (0x1 << 3)
1601#define RT5651_MB1_OC_CLR_SFT 3
1602#define RT5651_STA_GPIO8 (0x1)
1603#define RT5651_STA_GPIO8_BIT 0
1604
1605/* Internal Status and GPIO status (0xbf) */
1606#define RT5651_STA_JD3 (0x1 << 15)
1607#define RT5651_STA_JD3_BIT 15
1608#define RT5651_STA_JD2 (0x1 << 14)
1609#define RT5651_STA_JD2_BIT 14
1610#define RT5651_STA_JD1_2 (0x1 << 13)
1611#define RT5651_STA_JD1_2_BIT 13
1612#define RT5651_STA_JD1_1 (0x1 << 12)
1613#define RT5651_STA_JD1_1_BIT 12
1614#define RT5651_STA_GP7 (0x1 << 11)
1615#define RT5651_STA_GP7_BIT 11
1616#define RT5651_STA_GP6 (0x1 << 10)
1617#define RT5651_STA_GP6_BIT 10
1618#define RT5651_STA_GP5 (0x1 << 9)
1619#define RT5651_STA_GP5_BIT 9
1620#define RT5651_STA_GP1 (0x1 << 8)
1621#define RT5651_STA_GP1_BIT 8
1622#define RT5651_STA_GP2 (0x1 << 7)
1623#define RT5651_STA_GP2_BIT 7
1624#define RT5651_STA_GP3 (0x1 << 6)
1625#define RT5651_STA_GP3_BIT 6
1626#define RT5651_STA_GP4 (0x1 << 5)
1627#define RT5651_STA_GP4_BIT 5
1628#define RT5651_STA_GP_JD (0x1 << 4)
1629#define RT5651_STA_GP_JD_BIT 4
1630
1631/* GPIO Control 1 (0xc0) */
1632#define RT5651_GP1_PIN_MASK (0x1 << 15)
1633#define RT5651_GP1_PIN_SFT 15
1634#define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1635#define RT5651_GP1_PIN_IRQ (0x1 << 15)
1636#define RT5651_GP2_PIN_MASK (0x1 << 14)
1637#define RT5651_GP2_PIN_SFT 14
1638#define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1639#define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1640#define RT5651_GPIO_M_MASK (0x1 << 9)
1641#define RT5651_GPIO_M_SFT 9
1642#define RT5651_GPIO_M_FLT (0x0 << 9)
1643#define RT5651_GPIO_M_PH (0x1 << 9)
1644#define RT5651_I2S2_SEL_MASK (0x1 << 8)
1645#define RT5651_I2S2_SEL_SFT 8
1646#define RT5651_I2S2_SEL_I2S (0x0 << 8)
1647#define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1648#define RT5651_GP5_PIN_MASK (0x1 << 7)
1649#define RT5651_GP5_PIN_SFT 7
1650#define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1651#define RT5651_GP5_PIN_IRQ (0x1 << 7)
1652#define RT5651_GP6_PIN_MASK (0x1 << 6)
1653#define RT5651_GP6_PIN_SFT 6
1654#define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1655#define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1656#define RT5651_GP7_PIN_MASK (0x1 << 5)
1657#define RT5651_GP7_PIN_SFT 5
1658#define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1659#define RT5651_GP7_PIN_IRQ (0x1 << 5)
1660#define RT5651_GP8_PIN_MASK (0x1 << 4)
1661#define RT5651_GP8_PIN_SFT 4
1662#define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1663#define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1664#define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1665#define RT5651_GPIO_PDM_SEL_SFT 3
1666#define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1667#define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1668
1669/* GPIO Control 2 (0xc1) */
1670#define RT5651_GP5_DR_MASK (0x1 << 14)
1671#define RT5651_GP5_DR_SFT 14
1672#define RT5651_GP5_DR_IN (0x0 << 14)
1673#define RT5651_GP5_DR_OUT (0x1 << 14)
1674#define RT5651_GP5_OUT_MASK (0x1 << 13)
1675#define RT5651_GP5_OUT_SFT 13
1676#define RT5651_GP5_OUT_LO (0x0 << 13)
1677#define RT5651_GP5_OUT_HI (0x1 << 13)
1678#define RT5651_GP5_P_MASK (0x1 << 12)
1679#define RT5651_GP5_P_SFT 12
1680#define RT5651_GP5_P_NOR (0x0 << 12)
1681#define RT5651_GP5_P_INV (0x1 << 12)
1682#define RT5651_GP4_DR_MASK (0x1 << 11)
1683#define RT5651_GP4_DR_SFT 11
1684#define RT5651_GP4_DR_IN (0x0 << 11)
1685#define RT5651_GP4_DR_OUT (0x1 << 11)
1686#define RT5651_GP4_OUT_MASK (0x1 << 10)
1687#define RT5651_GP4_OUT_SFT 10
1688#define RT5651_GP4_OUT_LO (0x0 << 10)
1689#define RT5651_GP4_OUT_HI (0x1 << 10)
1690#define RT5651_GP4_P_MASK (0x1 << 9)
1691#define RT5651_GP4_P_SFT 9
1692#define RT5651_GP4_P_NOR (0x0 << 9)
1693#define RT5651_GP4_P_INV (0x1 << 9)
1694#define RT5651_GP3_DR_MASK (0x1 << 8)
1695#define RT5651_GP3_DR_SFT 8
1696#define RT5651_GP3_DR_IN (0x0 << 8)
1697#define RT5651_GP3_DR_OUT (0x1 << 8)
1698#define RT5651_GP3_OUT_MASK (0x1 << 7)
1699#define RT5651_GP3_OUT_SFT 7
1700#define RT5651_GP3_OUT_LO (0x0 << 7)
1701#define RT5651_GP3_OUT_HI (0x1 << 7)
1702#define RT5651_GP3_P_MASK (0x1 << 6)
1703#define RT5651_GP3_P_SFT 6
1704#define RT5651_GP3_P_NOR (0x0 << 6)
1705#define RT5651_GP3_P_INV (0x1 << 6)
1706#define RT5651_GP2_DR_MASK (0x1 << 5)
1707#define RT5651_GP2_DR_SFT 5
1708#define RT5651_GP2_DR_IN (0x0 << 5)
1709#define RT5651_GP2_DR_OUT (0x1 << 5)
1710#define RT5651_GP2_OUT_MASK (0x1 << 4)
1711#define RT5651_GP2_OUT_SFT 4
1712#define RT5651_GP2_OUT_LO (0x0 << 4)
1713#define RT5651_GP2_OUT_HI (0x1 << 4)
1714#define RT5651_GP2_P_MASK (0x1 << 3)
1715#define RT5651_GP2_P_SFT 3
1716#define RT5651_GP2_P_NOR (0x0 << 3)
1717#define RT5651_GP2_P_INV (0x1 << 3)
1718#define RT5651_GP1_DR_MASK (0x1 << 2)
1719#define RT5651_GP1_DR_SFT 2
1720#define RT5651_GP1_DR_IN (0x0 << 2)
1721#define RT5651_GP1_DR_OUT (0x1 << 2)
1722#define RT5651_GP1_OUT_MASK (0x1 << 1)
1723#define RT5651_GP1_OUT_SFT 1
1724#define RT5651_GP1_OUT_LO (0x0 << 1)
1725#define RT5651_GP1_OUT_HI (0x1 << 1)
1726#define RT5651_GP1_P_MASK (0x1)
1727#define RT5651_GP1_P_SFT 0
1728#define RT5651_GP1_P_NOR (0x0)
1729#define RT5651_GP1_P_INV (0x1)
1730
1731/* GPIO Control 3 (0xc2) */
1732#define RT5651_GP8_DR_MASK (0x1 << 8)
1733#define RT5651_GP8_DR_SFT 8
1734#define RT5651_GP8_DR_IN (0x0 << 8)
1735#define RT5651_GP8_DR_OUT (0x1 << 8)
1736#define RT5651_GP8_OUT_MASK (0x1 << 7)
1737#define RT5651_GP8_OUT_SFT 7
1738#define RT5651_GP8_OUT_LO (0x0 << 7)
1739#define RT5651_GP8_OUT_HI (0x1 << 7)
1740#define RT5651_GP8_P_MASK (0x1 << 6)
1741#define RT5651_GP8_P_SFT 6
1742#define RT5651_GP8_P_NOR (0x0 << 6)
1743#define RT5651_GP8_P_INV (0x1 << 6)
1744#define RT5651_GP7_DR_MASK (0x1 << 5)
1745#define RT5651_GP7_DR_SFT 5
1746#define RT5651_GP7_DR_IN (0x0 << 5)
1747#define RT5651_GP7_DR_OUT (0x1 << 5)
1748#define RT5651_GP7_OUT_MASK (0x1 << 4)
1749#define RT5651_GP7_OUT_SFT 4
1750#define RT5651_GP7_OUT_LO (0x0 << 4)
1751#define RT5651_GP7_OUT_HI (0x1 << 4)
1752#define RT5651_GP7_P_MASK (0x1 << 3)
1753#define RT5651_GP7_P_SFT 3
1754#define RT5651_GP7_P_NOR (0x0 << 3)
1755#define RT5651_GP7_P_INV (0x1 << 3)
1756#define RT5651_GP6_DR_MASK (0x1 << 2)
1757#define RT5651_GP6_DR_SFT 2
1758#define RT5651_GP6_DR_IN (0x0 << 2)
1759#define RT5651_GP6_DR_OUT (0x1 << 2)
1760#define RT5651_GP6_OUT_MASK (0x1 << 1)
1761#define RT5651_GP6_OUT_SFT 1
1762#define RT5651_GP6_OUT_LO (0x0 << 1)
1763#define RT5651_GP6_OUT_HI (0x1 << 1)
1764#define RT5651_GP6_P_MASK (0x1)
1765#define RT5651_GP6_P_SFT 0
1766#define RT5651_GP6_P_NOR (0x0)
1767#define RT5651_GP6_P_INV (0x1)
1768
1769/* Scramble Control (0xce) */
1770#define RT5651_SCB_SWAP_MASK (0x1 << 15)
1771#define RT5651_SCB_SWAP_SFT 15
1772#define RT5651_SCB_SWAP_DIS (0x0 << 15)
1773#define RT5651_SCB_SWAP_EN (0x1 << 15)
1774#define RT5651_SCB_MASK (0x1 << 14)
1775#define RT5651_SCB_SFT 14
1776#define RT5651_SCB_DIS (0x0 << 14)
1777#define RT5651_SCB_EN (0x1 << 14)
1778
1779/* Baseback Control (0xcf) */
1780#define RT5651_BB_MASK (0x1 << 15)
1781#define RT5651_BB_SFT 15
1782#define RT5651_BB_DIS (0x0 << 15)
1783#define RT5651_BB_EN (0x1 << 15)
1784#define RT5651_BB_CT_MASK (0x7 << 12)
1785#define RT5651_BB_CT_SFT 12
1786#define RT5651_BB_CT_A (0x0 << 12)
1787#define RT5651_BB_CT_B (0x1 << 12)
1788#define RT5651_BB_CT_C (0x2 << 12)
1789#define RT5651_BB_CT_D (0x3 << 12)
1790#define RT5651_M_BB_L_MASK (0x1 << 9)
1791#define RT5651_M_BB_L_SFT 9
1792#define RT5651_M_BB_R_MASK (0x1 << 8)
1793#define RT5651_M_BB_R_SFT 8
1794#define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1795#define RT5651_M_BB_HPF_L_SFT 7
1796#define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1797#define RT5651_M_BB_HPF_R_SFT 6
1798#define RT5651_G_BB_BST_MASK (0x3f)
1799#define RT5651_G_BB_BST_SFT 0
1800
1801/* MP3 Plus Control 1 (0xd0) */
1802#define RT5651_M_MP3_L_MASK (0x1 << 15)
1803#define RT5651_M_MP3_L_SFT 15
1804#define RT5651_M_MP3_R_MASK (0x1 << 14)
1805#define RT5651_M_MP3_R_SFT 14
1806#define RT5651_M_MP3_MASK (0x1 << 13)
1807#define RT5651_M_MP3_SFT 13
1808#define RT5651_M_MP3_DIS (0x0 << 13)
1809#define RT5651_M_MP3_EN (0x1 << 13)
1810#define RT5651_EG_MP3_MASK (0x1f << 8)
1811#define RT5651_EG_MP3_SFT 8
1812#define RT5651_MP3_HLP_MASK (0x1 << 7)
1813#define RT5651_MP3_HLP_SFT 7
1814#define RT5651_MP3_HLP_DIS (0x0 << 7)
1815#define RT5651_MP3_HLP_EN (0x1 << 7)
1816#define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1817#define RT5651_M_MP3_ORG_L_SFT 6
1818#define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1819#define RT5651_M_MP3_ORG_R_SFT 5
1820
1821/* MP3 Plus Control 2 (0xd1) */
1822#define RT5651_MP3_WT_MASK (0x1 << 13)
1823#define RT5651_MP3_WT_SFT 13
1824#define RT5651_MP3_WT_1_4 (0x0 << 13)
1825#define RT5651_MP3_WT_1_2 (0x1 << 13)
1826#define RT5651_OG_MP3_MASK (0x1f << 8)
1827#define RT5651_OG_MP3_SFT 8
1828#define RT5651_HG_MP3_MASK (0x3f)
1829#define RT5651_HG_MP3_SFT 0
1830
1831/* 3D HP Control 1 (0xd2) */
1832#define RT5651_3D_CF_MASK (0x1 << 15)
1833#define RT5651_3D_CF_SFT 15
1834#define RT5651_3D_CF_DIS (0x0 << 15)
1835#define RT5651_3D_CF_EN (0x1 << 15)
1836#define RT5651_3D_HP_MASK (0x1 << 14)
1837#define RT5651_3D_HP_SFT 14
1838#define RT5651_3D_HP_DIS (0x0 << 14)
1839#define RT5651_3D_HP_EN (0x1 << 14)
1840#define RT5651_3D_BT_MASK (0x1 << 13)
1841#define RT5651_3D_BT_SFT 13
1842#define RT5651_3D_BT_DIS (0x0 << 13)
1843#define RT5651_3D_BT_EN (0x1 << 13)
1844#define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1845#define RT5651_3D_1F_MIX_SFT 11
1846#define RT5651_3D_HP_M_MASK (0x1 << 10)
1847#define RT5651_3D_HP_M_SFT 10
1848#define RT5651_3D_HP_M_SUR (0x0 << 10)
1849#define RT5651_3D_HP_M_FRO (0x1 << 10)
1850#define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1851#define RT5651_M_3D_HRTF_SFT 9
1852#define RT5651_M_3D_D2H_MASK (0x1 << 8)
1853#define RT5651_M_3D_D2H_SFT 8
1854#define RT5651_M_3D_D2R_MASK (0x1 << 7)
1855#define RT5651_M_3D_D2R_SFT 7
1856#define RT5651_M_3D_REVB_MASK (0x1 << 6)
1857#define RT5651_M_3D_REVB_SFT 6
1858
1859/* Adjustable high pass filter control 1 (0xd3) */
1860#define RT5651_2ND_HPF_MASK (0x1 << 15)
1861#define RT5651_2ND_HPF_SFT 15
1862#define RT5651_2ND_HPF_DIS (0x0 << 15)
1863#define RT5651_2ND_HPF_EN (0x1 << 15)
1864#define RT5651_HPF_CF_L_MASK (0x7 << 12)
1865#define RT5651_HPF_CF_L_SFT 12
1866#define RT5651_HPF_CF_R_MASK (0x7 << 8)
1867#define RT5651_HPF_CF_R_SFT 8
1868#define RT5651_ZD_T_MASK (0x3 << 6)
1869#define RT5651_ZD_T_SFT 6
1870#define RT5651_ZD_F_MASK (0x3 << 4)
1871#define RT5651_ZD_F_SFT 4
1872#define RT5651_ZD_F_IM (0x0 << 4)
1873#define RT5651_ZD_F_ZC_IM (0x1 << 4)
1874#define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1875#define RT5651_ZD_F_UN (0x3 << 4)
1876
1877/* Adjustable high pass filter control 2 (0xd4) */
1878#define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1879#define RT5651_HPF_CF_L_NUM_SFT 8
1880#define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1881#define RT5651_HPF_CF_R_NUM_SFT 0
1882
1883/* HP calibration control and Amp detection (0xd6) */
1884#define RT5651_SI_DAC_MASK (0x1 << 11)
1885#define RT5651_SI_DAC_SFT 11
1886#define RT5651_SI_DAC_AUTO (0x0 << 11)
1887#define RT5651_SI_DAC_TEST (0x1 << 11)
1888#define RT5651_DC_CAL_M_MASK (0x1 << 10)
1889#define RT5651_DC_CAL_M_SFT 10
1890#define RT5651_DC_CAL_M_NOR (0x0 << 10)
1891#define RT5651_DC_CAL_M_CAL (0x1 << 10)
1892#define RT5651_DC_CAL_MASK (0x1 << 9)
1893#define RT5651_DC_CAL_SFT 9
1894#define RT5651_DC_CAL_DIS (0x0 << 9)
1895#define RT5651_DC_CAL_EN (0x1 << 9)
1896#define RT5651_HPD_RCV_MASK (0x7 << 6)
1897#define RT5651_HPD_RCV_SFT 6
1898#define RT5651_HPD_PS_MASK (0x1 << 5)
1899#define RT5651_HPD_PS_SFT 5
1900#define RT5651_HPD_PS_DIS (0x0 << 5)
1901#define RT5651_HPD_PS_EN (0x1 << 5)
1902#define RT5651_CAL_M_MASK (0x1 << 4)
1903#define RT5651_CAL_M_SFT 4
1904#define RT5651_CAL_M_DEP (0x0 << 4)
1905#define RT5651_CAL_M_CAL (0x1 << 4)
1906#define RT5651_CAL_MASK (0x1 << 3)
1907#define RT5651_CAL_SFT 3
1908#define RT5651_CAL_DIS (0x0 << 3)
1909#define RT5651_CAL_EN (0x1 << 3)
1910#define RT5651_CAL_TEST_MASK (0x1 << 2)
1911#define RT5651_CAL_TEST_SFT 2
1912#define RT5651_CAL_TEST_DIS (0x0 << 2)
1913#define RT5651_CAL_TEST_EN (0x1 << 2)
1914#define RT5651_CAL_P_MASK (0x3)
1915#define RT5651_CAL_P_SFT 0
1916#define RT5651_CAL_P_NONE (0x0)
1917#define RT5651_CAL_P_CAL (0x1)
1918#define RT5651_CAL_P_DAC_CAL (0x2)
1919
1920/* Soft volume and zero cross control 1 (0xd9) */
1921#define RT5651_SV_MASK (0x1 << 15)
1922#define RT5651_SV_SFT 15
1923#define RT5651_SV_DIS (0x0 << 15)
1924#define RT5651_SV_EN (0x1 << 15)
1925#define RT5651_OUT_SV_MASK (0x1 << 13)
1926#define RT5651_OUT_SV_SFT 13
1927#define RT5651_OUT_SV_DIS (0x0 << 13)
1928#define RT5651_OUT_SV_EN (0x1 << 13)
1929#define RT5651_HP_SV_MASK (0x1 << 12)
1930#define RT5651_HP_SV_SFT 12
1931#define RT5651_HP_SV_DIS (0x0 << 12)
1932#define RT5651_HP_SV_EN (0x1 << 12)
1933#define RT5651_ZCD_DIG_MASK (0x1 << 11)
1934#define RT5651_ZCD_DIG_SFT 11
1935#define RT5651_ZCD_DIG_DIS (0x0 << 11)
1936#define RT5651_ZCD_DIG_EN (0x1 << 11)
1937#define RT5651_ZCD_MASK (0x1 << 10)
1938#define RT5651_ZCD_SFT 10
1939#define RT5651_ZCD_PD (0x0 << 10)
1940#define RT5651_ZCD_PU (0x1 << 10)
1941#define RT5651_M_ZCD_MASK (0x3f << 4)
1942#define RT5651_M_ZCD_SFT 4
1943#define RT5651_M_ZCD_OM_L (0x1 << 7)
1944#define RT5651_M_ZCD_OM_R (0x1 << 6)
1945#define RT5651_M_ZCD_RM_L (0x1 << 5)
1946#define RT5651_M_ZCD_RM_R (0x1 << 4)
1947#define RT5651_SV_DLY_MASK (0xf)
1948#define RT5651_SV_DLY_SFT 0
1949
1950/* Soft volume and zero cross control 2 (0xda) */
1951#define RT5651_ZCD_HP_MASK (0x1 << 15)
1952#define RT5651_ZCD_HP_SFT 15
1953#define RT5651_ZCD_HP_DIS (0x0 << 15)
1954#define RT5651_ZCD_HP_EN (0x1 << 15)
1955
1956/* Digital Misc Control (0xfa) */
1957#define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1958#define RT5651_I2S2_MS_SP_SEL 8
1959#define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1960#define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1961#define RT5651_CLK_DET_EN (0x1 << 3)
1962#define RT5651_CLK_DET_EN_SFT 3
1963#define RT5651_AMP_DET_EN (0x1 << 1)
1964#define RT5651_AMP_DET_EN_SFT 1
1965#define RT5651_D_GATE_EN (0x1)
1966#define RT5651_D_GATE_EN_SFT 0
1967
1968/* Codec Private Register definition */
1969/* 3D Speaker Control (0x63) */
1970#define RT5651_3D_SPK_MASK (0x1 << 15)
1971#define RT5651_3D_SPK_SFT 15
1972#define RT5651_3D_SPK_DIS (0x0 << 15)
1973#define RT5651_3D_SPK_EN (0x1 << 15)
1974#define RT5651_3D_SPK_M_MASK (0x3 << 13)
1975#define RT5651_3D_SPK_M_SFT 13
1976#define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1977#define RT5651_3D_SPK_CG_SFT 8
1978#define RT5651_3D_SPK_SG_MASK (0x1f)
1979#define RT5651_3D_SPK_SG_SFT 0
1980
1981/* Wind Noise Detection Control 1 (0x6c) */
1982#define RT5651_WND_MASK (0x1 << 15)
1983#define RT5651_WND_SFT 15
1984#define RT5651_WND_DIS (0x0 << 15)
1985#define RT5651_WND_EN (0x1 << 15)
1986
1987/* Wind Noise Detection Control 2 (0x6d) */
1988#define RT5651_WND_FC_NW_MASK (0x3f << 10)
1989#define RT5651_WND_FC_NW_SFT 10
1990#define RT5651_WND_FC_WK_MASK (0x3f << 4)
1991#define RT5651_WND_FC_WK_SFT 4
1992
1993/* Wind Noise Detection Control 3 (0x6e) */
1994#define RT5651_HPF_FC_MASK (0x3f << 6)
1995#define RT5651_HPF_FC_SFT 6
1996#define RT5651_WND_FC_ST_MASK (0x3f)
1997#define RT5651_WND_FC_ST_SFT 0
1998
1999/* Wind Noise Detection Control 4 (0x6f) */
2000#define RT5651_WND_TH_LO_MASK (0x3ff)
2001#define RT5651_WND_TH_LO_SFT 0
2002
2003/* Wind Noise Detection Control 5 (0x70) */
2004#define RT5651_WND_TH_HI_MASK (0x3ff)
2005#define RT5651_WND_TH_HI_SFT 0
2006
2007/* Wind Noise Detection Control 8 (0x73) */
2008#define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2009#define RT5651_WND_WIND_SFT 13
2010#define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2011#define RT5651_WND_STRONG_SFT 12
2012enum {
2013 RT5651_NO_WIND,
2014 RT5651_BREEZE,
2015 RT5651_STORM,
2016};
2017
2018/* Dipole Speaker Interface (0x75) */
2019#define RT5651_DP_ATT_MASK (0x3 << 14)
2020#define RT5651_DP_ATT_SFT 14
2021#define RT5651_DP_SPK_MASK (0x1 << 10)
2022#define RT5651_DP_SPK_SFT 10
2023#define RT5651_DP_SPK_DIS (0x0 << 10)
2024#define RT5651_DP_SPK_EN (0x1 << 10)
2025
2026/* EQ Pre Volume Control (0xb3) */
2027#define RT5651_EQ_PRE_VOL_MASK (0xffff)
2028#define RT5651_EQ_PRE_VOL_SFT 0
2029
2030/* EQ Post Volume Control (0xb4) */
2031#define RT5651_EQ_PST_VOL_MASK (0xffff)
2032#define RT5651_EQ_PST_VOL_SFT 0
2033
2034/* System Clock Source */
2035enum {
2036 RT5651_SCLK_S_MCLK,
2037 RT5651_SCLK_S_PLL1,
2038 RT5651_SCLK_S_RCCLK,
2039};
2040
2041/* PLL1 Source */
2042enum {
2043 RT5651_PLL1_S_MCLK,
2044 RT5651_PLL1_S_BCLK1,
2045 RT5651_PLL1_S_BCLK2,
2046};
2047
2048enum {
2049 RT5651_AIF1,
2050 RT5651_AIF2,
2051 RT5651_AIFS,
2052};
2053
2054struct rt5651_pll_code {
2055 bool m_bp; /* Indicates bypass m code or not. */
2056 int m_code;
2057 int n_code;
2058 int k_code;
2059};
2060
2061struct rt5651_priv {
2062 struct snd_soc_codec *codec;
2063 struct rt5651_platform_data pdata;
2064 struct regmap *regmap;
2065
2066 int sysclk;
2067 int sysclk_src;
2068 int lrck[RT5651_AIFS];
2069 int bclk[RT5651_AIFS];
2070 int master[RT5651_AIFS];
2071
2072 struct rt5651_pll_code pll_code;
2073 int pll_src;
2074 int pll_in;
2075 int pll_out;
2076
2077 int dmic_en;
2078 bool hp_mute;
2079};
2080
2081#endif /* __RT5651_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-07 22:24:55 -0400