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authorMingkai Hu <Mingkai.hu@freescale.com>2011-06-28 03:52:34 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-07-08 01:21:32 -0400
commit3fce1c0ba2b35b68135d8d8a3438f8c8272a01d8 (patch)
tree5218391b3566c3eb842a67807a2d8b442999f70b
parent59f8df290acb6d279a690733a67b3902766999f3 (diff)
powerpc/85xx: Add p2040 RDB board support
P2040RDB Specification: ----------------------- 2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) 128 Mbyte NOR flash single-chip memory 256 Kbit M24256 I2C EEPROM 16 Mbyte SPI memory SD connector to interface with the SD memory card dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) I2C1: Real time clock, Temperature sensor I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors UART: supports two UARTs up to 115200 bps for console USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces PCIe: - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/p2040rdb.dts166
-rw-r--r--arch/powerpc/boot/dts/p2040si.dtsi623
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig1
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig12
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/p2040_rdb.c88
6 files changed, 891 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p2040rdb.dts b/arch/powerpc/boot/dts/p2040rdb.dts
new file mode 100644
index 000000000000..7d84e391c632
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040rdb.dts
@@ -0,0 +1,166 @@
1/*
2 * P2040RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p2040si.dtsi"
36
37/ {
38 model = "fsl,P2040RDB";
39 compatible = "fsl,P2040RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118000 {
79 lm75b@48 {
80 compatible = "nxp,lm75a";
81 reg = <0x48>;
82 };
83 eeprom@50 {
84 compatible = "at24,24c256";
85 reg = <0x50>;
86 };
87 rtc@68 {
88 compatible = "pericom,pt7c4338";
89 reg = <0x68>;
90 };
91 };
92
93 i2c@118100 {
94 eeprom@50 {
95 compatible = "at24,24c256";
96 reg = <0x50>;
97 };
98 };
99
100 usb0: usb@210000 {
101 phy_type = "utmi";
102 };
103
104 usb1: usb@211000 {
105 dr_mode = "host";
106 phy_type = "utmi";
107 };
108 };
109
110 localbus@ffe124000 {
111 reg = <0xf 0xfe124000 0 0x1000>;
112 ranges = <0 0 0xf 0xe8000000 0x08000000>;
113
114 flash@0,0 {
115 compatible = "cfi-flash";
116 reg = <0 0 0x08000000>;
117 bank-width = <2>;
118 device-width = <2>;
119 };
120 };
121
122 pci0: pcie@ffe200000 {
123 reg = <0xf 0xfe200000 0 0x1000>;
124 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
125 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126 pcie@0 {
127 ranges = <0x02000000 0 0xe0000000
128 0x02000000 0 0xe0000000
129 0 0x20000000
130
131 0x01000000 0 0x00000000
132 0x01000000 0 0x00000000
133 0 0x00010000>;
134 };
135 };
136
137 pci1: pcie@ffe201000 {
138 reg = <0xf 0xfe201000 0 0x1000>;
139 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
140 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141 pcie@0 {
142 ranges = <0x02000000 0 0xe0000000
143 0x02000000 0 0xe0000000
144 0 0x20000000
145
146 0x01000000 0 0x00000000
147 0x01000000 0 0x00000000
148 0 0x00010000>;
149 };
150 };
151
152 pci2: pcie@ffe202000 {
153 reg = <0xf 0xfe202000 0 0x1000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
155 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x20000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166};
diff --git a/arch/powerpc/boot/dts/p2040si.dtsi b/arch/powerpc/boot/dts/p2040si.dtsi
new file mode 100644
index 000000000000..5fdbb24c0763
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040si.dtsi
@@ -0,0 +1,623 @@
1/*
2 * P2040 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P2040";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 };
111
112 soc: soc@ffe000000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 device_type = "soc";
116 compatible = "simple-bus";
117 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
118 reg = <0xf 0xfe000000 0 0x00001000>;
119
120 soc-sram-error {
121 compatible = "fsl,soc-sram-error";
122 interrupts = <16 2 1 29>;
123 };
124
125 corenet-law@0 {
126 compatible = "fsl,corenet-law";
127 reg = <0x0 0x1000>;
128 fsl,num-laws = <32>;
129 };
130
131 memory-controller@8000 {
132 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
133 reg = <0x8000 0x1000>;
134 interrupts = <16 2 1 23>;
135 };
136
137 cpc: l3-cache-controller@10000 {
138 compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
139 reg = <0x10000 0x1000>;
140 interrupts = <16 2 1 27>;
141 };
142
143 corenet-cf@18000 {
144 compatible = "fsl,corenet-cf";
145 reg = <0x18000 0x1000>;
146 interrupts = <16 2 1 31>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,pamu-v1.0", "fsl,pamu";
153 reg = <0x20000 0x4000>;
154 interrupts = <
155 24 2 0 0
156 16 2 1 30>;
157 };
158
159 mpic: pic@40000 {
160 clock-frequency = <0>;
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <4>;
164 reg = <0x40000 0x40000>;
165 compatible = "fsl,mpic", "chrp,open-pic";
166 device_type = "open-pic";
167 };
168
169 msi0: msi@41600 {
170 compatible = "fsl,mpic-msi";
171 reg = <0x41600 0x200>;
172 msi-available-ranges = <0 0x100>;
173 interrupts = <
174 0xe0 0 0 0
175 0xe1 0 0 0
176 0xe2 0 0 0
177 0xe3 0 0 0
178 0xe4 0 0 0
179 0xe5 0 0 0
180 0xe6 0 0 0
181 0xe7 0 0 0>;
182 };
183
184 msi1: msi@41800 {
185 compatible = "fsl,mpic-msi";
186 reg = <0x41800 0x200>;
187 msi-available-ranges = <0 0x100>;
188 interrupts = <
189 0xe8 0 0 0
190 0xe9 0 0 0
191 0xea 0 0 0
192 0xeb 0 0 0
193 0xec 0 0 0
194 0xed 0 0 0
195 0xee 0 0 0
196 0xef 0 0 0>;
197 };
198
199 msi2: msi@41a00 {
200 compatible = "fsl,mpic-msi";
201 reg = <0x41a00 0x200>;
202 msi-available-ranges = <0 0x100>;
203 interrupts = <
204 0xf0 0 0 0
205 0xf1 0 0 0
206 0xf2 0 0 0
207 0xf3 0 0 0
208 0xf4 0 0 0
209 0xf5 0 0 0
210 0xf6 0 0 0
211 0xf7 0 0 0>;
212 };
213
214 guts: global-utilities@e0000 {
215 compatible = "fsl,qoriq-device-config-1.0";
216 reg = <0xe0000 0xe00>;
217 fsl,has-rstcr;
218 #sleep-cells = <1>;
219 fsl,liodn-bits = <12>;
220 };
221
222 pins: global-utilities@e0e00 {
223 compatible = "fsl,qoriq-pin-control-1.0";
224 reg = <0xe0e00 0x200>;
225 #sleep-cells = <2>;
226 };
227
228 clockgen: global-utilities@e1000 {
229 compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
230 reg = <0xe1000 0x1000>;
231 clock-frequency = <0>;
232 };
233
234 rcpm: global-utilities@e2000 {
235 compatible = "fsl,qoriq-rcpm-1.0";
236 reg = <0xe2000 0x1000>;
237 #sleep-cells = <1>;
238 };
239
240 sfp: sfp@e8000 {
241 compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
242 reg = <0xe8000 0x1000>;
243 };
244
245 serdes: serdes@ea000 {
246 compatible = "fsl,p2040-serdes";
247 reg = <0xea000 0x1000>;
248 };
249
250 dma0: dma@100300 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
254 reg = <0x100300 0x4>;
255 ranges = <0x0 0x100100 0x200>;
256 cell-index = <0>;
257 dma-channel@0 {
258 compatible = "fsl,p2040-dma-channel",
259 "fsl,eloplus-dma-channel";
260 reg = <0x0 0x80>;
261 cell-index = <0>;
262 interrupts = <28 2 0 0>;
263 };
264 dma-channel@80 {
265 compatible = "fsl,p2040-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x80 0x80>;
268 cell-index = <1>;
269 interrupts = <29 2 0 0>;
270 };
271 dma-channel@100 {
272 compatible = "fsl,p2040-dma-channel",
273 "fsl,eloplus-dma-channel";
274 reg = <0x100 0x80>;
275 cell-index = <2>;
276 interrupts = <30 2 0 0>;
277 };
278 dma-channel@180 {
279 compatible = "fsl,p2040-dma-channel",
280 "fsl,eloplus-dma-channel";
281 reg = <0x180 0x80>;
282 cell-index = <3>;
283 interrupts = <31 2 0 0>;
284 };
285 };
286
287 dma1: dma@101300 {
288 #address-cells = <1>;
289 #size-cells = <1>;
290 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
291 reg = <0x101300 0x4>;
292 ranges = <0x0 0x101100 0x200>;
293 cell-index = <1>;
294 dma-channel@0 {
295 compatible = "fsl,p2040-dma-channel",
296 "fsl,eloplus-dma-channel";
297 reg = <0x0 0x80>;
298 cell-index = <0>;
299 interrupts = <32 2 0 0>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,p2040-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <33 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,p2040-dma-channel",
310 "fsl,eloplus-dma-channel";
311 reg = <0x100 0x80>;
312 cell-index = <2>;
313 interrupts = <34 2 0 0>;
314 };
315 dma-channel@180 {
316 compatible = "fsl,p2040-dma-channel",
317 "fsl,eloplus-dma-channel";
318 reg = <0x180 0x80>;
319 cell-index = <3>;
320 interrupts = <35 2 0 0>;
321 };
322 };
323
324 spi@110000 {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
328 reg = <0x110000 0x1000>;
329 interrupts = <53 0x2 0 0>;
330 fsl,espi-num-chipselects = <4>;
331
332 };
333
334 sdhc: sdhc@114000 {
335 compatible = "fsl,p2040-esdhc", "fsl,esdhc";
336 reg = <0x114000 0x1000>;
337 interrupts = <48 2 0 0>;
338 sdhci,auto-cmd12;
339 clock-frequency = <0>;
340 };
341
342
343 i2c@118000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 cell-index = <0>;
347 compatible = "fsl-i2c";
348 reg = <0x118000 0x100>;
349 interrupts = <38 2 0 0>;
350 dfsrr;
351 };
352
353 i2c@118100 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 cell-index = <1>;
357 compatible = "fsl-i2c";
358 reg = <0x118100 0x100>;
359 interrupts = <38 2 0 0>;
360 dfsrr;
361 };
362
363 i2c@119000 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 cell-index = <2>;
367 compatible = "fsl-i2c";
368 reg = <0x119000 0x100>;
369 interrupts = <39 2 0 0>;
370 dfsrr;
371 };
372
373 i2c@119100 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 cell-index = <3>;
377 compatible = "fsl-i2c";
378 reg = <0x119100 0x100>;
379 interrupts = <39 2 0 0>;
380 dfsrr;
381 };
382
383 serial0: serial@11c500 {
384 cell-index = <0>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11c500 0x100>;
388 clock-frequency = <0>;
389 interrupts = <36 2 0 0>;
390 };
391
392 serial1: serial@11c600 {
393 cell-index = <1>;
394 device_type = "serial";
395 compatible = "ns16550";
396 reg = <0x11c600 0x100>;
397 clock-frequency = <0>;
398 interrupts = <36 2 0 0>;
399 };
400
401 serial2: serial@11d500 {
402 cell-index = <2>;
403 device_type = "serial";
404 compatible = "ns16550";
405 reg = <0x11d500 0x100>;
406 clock-frequency = <0>;
407 interrupts = <37 2 0 0>;
408 };
409
410 serial3: serial@11d600 {
411 cell-index = <3>;
412 device_type = "serial";
413 compatible = "ns16550";
414 reg = <0x11d600 0x100>;
415 clock-frequency = <0>;
416 interrupts = <37 2 0 0>;
417 };
418
419 gpio0: gpio@130000 {
420 compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
421 reg = <0x130000 0x1000>;
422 interrupts = <55 2 0 0>;
423 #gpio-cells = <2>;
424 gpio-controller;
425 };
426
427 usb0: usb@210000 {
428 compatible = "fsl,p2040-usb2-mph",
429 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
430 reg = <0x210000 0x1000>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 interrupts = <44 0x2 0 0>;
434 port0;
435 };
436
437 usb1: usb@211000 {
438 compatible = "fsl,p2040-usb2-dr",
439 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
440 reg = <0x211000 0x1000>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 interrupts = <45 0x2 0 0>;
444 };
445
446 sata@220000 {
447 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
448 reg = <0x220000 0x1000>;
449 interrupts = <68 0x2 0 0>;
450 };
451
452 sata@221000 {
453 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
454 reg = <0x221000 0x1000>;
455 interrupts = <69 0x2 0 0>;
456 };
457
458 crypto: crypto@300000 {
459 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
460 #address-cells = <1>;
461 #size-cells = <1>;
462 reg = <0x300000 0x10000>;
463 ranges = <0 0x300000 0x10000>;
464 interrupts = <92 2 0 0>;
465
466 sec_jr0: jr@1000 {
467 compatible = "fsl,sec-v4.2-job-ring",
468 "fsl,sec-v4.0-job-ring";
469 reg = <0x1000 0x1000>;
470 interrupts = <88 2 0 0>;
471 };
472
473 sec_jr1: jr@2000 {
474 compatible = "fsl,sec-v4.2-job-ring",
475 "fsl,sec-v4.0-job-ring";
476 reg = <0x2000 0x1000>;
477 interrupts = <89 2 0 0>;
478 };
479
480 sec_jr2: jr@3000 {
481 compatible = "fsl,sec-v4.2-job-ring",
482 "fsl,sec-v4.0-job-ring";
483 reg = <0x3000 0x1000>;
484 interrupts = <90 2 0 0>;
485 };
486
487 sec_jr3: jr@4000 {
488 compatible = "fsl,sec-v4.2-job-ring",
489 "fsl,sec-v4.0-job-ring";
490 reg = <0x4000 0x1000>;
491 interrupts = <91 2 0 0>;
492 };
493
494 rtic@6000 {
495 compatible = "fsl,sec-v4.2-rtic",
496 "fsl,sec-v4.0-rtic";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x6000 0x100>;
500 ranges = <0x0 0x6100 0xe00>;
501
502 rtic_a: rtic-a@0 {
503 compatible = "fsl,sec-v4.2-rtic-memory",
504 "fsl,sec-v4.0-rtic-memory";
505 reg = <0x00 0x20 0x100 0x80>;
506 };
507
508 rtic_b: rtic-b@20 {
509 compatible = "fsl,sec-v4.2-rtic-memory",
510 "fsl,sec-v4.0-rtic-memory";
511 reg = <0x20 0x20 0x200 0x80>;
512 };
513
514 rtic_c: rtic-c@40 {
515 compatible = "fsl,sec-v4.2-rtic-memory",
516 "fsl,sec-v4.0-rtic-memory";
517 reg = <0x40 0x20 0x300 0x80>;
518 };
519
520 rtic_d: rtic-d@60 {
521 compatible = "fsl,sec-v4.2-rtic-memory",
522 "fsl,sec-v4.0-rtic-memory";
523 reg = <0x60 0x20 0x500 0x80>;
524 };
525 };
526 };
527
528 sec_mon: sec_mon@314000 {
529 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
530 reg = <0x314000 0x1000>;
531 interrupts = <93 2 0 0>;
532 };
533
534 };
535
536 localbus@ffe124000 {
537 compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
538 interrupts = <25 2 0 0>;
539 #address-cells = <2>;
540 #size-cells = <1>;
541 };
542
543 pci0: pcie@ffe200000 {
544 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
545 device_type = "pci";
546 #size-cells = <2>;
547 #address-cells = <3>;
548 bus-range = <0x0 0xff>;
549 clock-frequency = <0x1fca055>;
550 fsl,msi = <&msi0>;
551 interrupts = <16 2 1 15>;
552 pcie@0 {
553 reg = <0 0 0 0 0>;
554 #interrupt-cells = <1>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 interrupts = <16 2 1 15>;
559 interrupt-map-mask = <0xf800 0 0 7>;
560 interrupt-map = <
561 /* IDSEL 0x0 */
562 0000 0 0 1 &mpic 40 1 0 0
563 0000 0 0 2 &mpic 1 1 0 0
564 0000 0 0 3 &mpic 2 1 0 0
565 0000 0 0 4 &mpic 3 1 0 0
566 >;
567 };
568 };
569
570 pci1: pcie@ffe201000 {
571 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
572 device_type = "pci";
573 #size-cells = <2>;
574 #address-cells = <3>;
575 bus-range = <0 0xff>;
576 clock-frequency = <0x1fca055>;
577 fsl,msi = <&msi1>;
578 interrupts = <16 2 1 14>;
579 pcie@0 {
580 reg = <0 0 0 0 0>;
581 #interrupt-cells = <1>;
582 #size-cells = <2>;
583 #address-cells = <3>;
584 device_type = "pci";
585 interrupts = <16 2 1 14>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 41 1 0 0
590 0000 0 0 2 &mpic 5 1 0 0
591 0000 0 0 3 &mpic 6 1 0 0
592 0000 0 0 4 &mpic 7 1 0 0
593 >;
594 };
595 };
596
597 pci2: pcie@ffe202000 {
598 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
599 device_type = "pci";
600 #size-cells = <2>;
601 #address-cells = <3>;
602 bus-range = <0x0 0xff>;
603 clock-frequency = <0x1fca055>;
604 fsl,msi = <&msi2>;
605 interrupts = <16 2 1 13>;
606 pcie@0 {
607 reg = <0 0 0 0 0>;
608 #interrupt-cells = <1>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 interrupts = <16 2 1 13>;
613 interrupt-map-mask = <0xf800 0 0 7>;
614 interrupt-map = <
615 /* IDSEL 0x0 */
616 0000 0 0 1 &mpic 42 1 0 0
617 0000 0 0 2 &mpic 9 1 0 0
618 0000 0 0 3 &mpic 10 1 0 0
619 0000 0 0 4 &mpic 11 1 0 0
620 >;
621 };
622 };
623};
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 421ade8b7465..10562a5c65b9 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODULE_UNLOAD=y
23CONFIG_MODULE_FORCE_UNLOAD=y 23CONFIG_MODULE_FORCE_UNLOAD=y
24CONFIG_MODVERSIONS=y 24CONFIG_MODVERSIONS=y
25# CONFIG_BLK_DEV_BSG is not set 25# CONFIG_BLK_DEV_BSG is not set
26CONFIG_P2040_RDB=y
26CONFIG_P3041_DS=y 27CONFIG_P3041_DS=y
27CONFIG_P4080_DS=y 28CONFIG_P4080_DS=y
28CONFIG_P5020_DS=y 29CONFIG_P5020_DS=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 4706c71c9435..498534cd5265 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -171,6 +171,18 @@ config SBC8560
171 help 171 help
172 This option enables support for the Wind River SBC8560 board 172 This option enables support for the Wind River SBC8560 board
173 173
174config P2040_RDB
175 bool "Freescale P2040 RDB"
176 select DEFAULT_UIMAGE
177 select PPC_E500MC
178 select PHYS_64BIT
179 select SWIOTLB
180 select MPC8xxx_GPIO
181 select HAS_RAPIDIO
182 select PPC_EPAPR_HV_PIC
183 help
184 This option enables support for the P2040 RDB board
185
174config P3041_DS 186config P3041_DS
175 bool "Freescale P3041 DS" 187 bool "Freescale P3041 DS"
176 select DEFAULT_UIMAGE 188 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 06b0c0877864..a971b32c5c0a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
13obj-$(CONFIG_P1010_RDB) += p1010rdb.o 13obj-$(CONFIG_P1010_RDB) += p1010rdb.o
14obj-$(CONFIG_P1022_DS) += p1022_ds.o 14obj-$(CONFIG_P1022_DS) += p1022_ds.o
15obj-$(CONFIG_P1023_RDS) += p1023_rds.o 15obj-$(CONFIG_P1023_RDS) += p1023_rds.o
16obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
16obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 17obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
17obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 18obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
18obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 19obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/p2040_rdb.c b/arch/powerpc/platforms/85xx/p2040_rdb.c
new file mode 100644
index 000000000000..32b56ac73dfb
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p2040_rdb.c
@@ -0,0 +1,88 @@
1/*
2 * P2040 RDB Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/kdev_t.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/phy.h>
18
19#include <asm/system.h>
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <linux/of_platform.h>
29#include <sysdev/fsl_soc.h>
30#include <sysdev/fsl_pci.h>
31#include <asm/ehv_pic.h>
32
33#include "corenet_ds.h"
34
35/*
36 * Called very early, device-tree isn't unflattened
37 */
38static int __init p2040_rdb_probe(void)
39{
40 unsigned long root = of_get_flat_dt_root();
41#ifdef CONFIG_SMP
42 extern struct smp_ops_t smp_85xx_ops;
43#endif
44
45 if (of_flat_dt_is_compatible(root, "fsl,P2040RDB"))
46 return 1;
47
48 /* Check if we're running under the Freescale hypervisor */
49 if (of_flat_dt_is_compatible(root, "fsl,P2040RDB-hv")) {
50 ppc_md.init_IRQ = ehv_pic_init;
51 ppc_md.get_irq = ehv_pic_get_irq;
52 ppc_md.restart = fsl_hv_restart;
53 ppc_md.power_off = fsl_hv_halt;
54 ppc_md.halt = fsl_hv_halt;
55#ifdef CONFIG_SMP
56 /*
57 * Disable the timebase sync operations because we can't write
58 * to the timebase registers under the hypervisor.
59 */
60 smp_85xx_ops.give_timebase = NULL;
61 smp_85xx_ops.take_timebase = NULL;
62#endif
63 return 1;
64 }
65
66 return 0;
67}
68
69define_machine(p2040_rdb) {
70 .name = "P2040 RDB",
71 .probe = p2040_rdb_probe,
72 .setup_arch = corenet_ds_setup_arch,
73 .init_IRQ = corenet_ds_pic_init,
74#ifdef CONFIG_PCI
75 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
76#endif
77 .get_irq = mpic_get_coreint_irq,
78 .restart = fsl_rstcr_restart,
79 .calibrate_decr = generic_calibrate_decr,
80 .progress = udbg_progress,
81 .power_save = e500_idle,
82};
83
84machine_device_initcall(p2040_rdb, corenet_ds_publish_devices);
85
86#ifdef CONFIG_SWIOTLB
87machine_arch_initcall(p2040_rdb, swiotlb_setup_bus_notifier);
88#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 21:44:00 -0500