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authorSam Ravnborg <sam@ravnborg.org>2008-06-05 14:48:20 -0400
committerDavid S. Miller <davem@davemloft.net>2008-07-18 00:38:42 -0400
commit3f261e829f56185eee3b224615636b99d54c3b3e (patch)
tree70e260aa842b7ac79293e1993bcaf3c249d5396d
parentfc491d7da88b02275ad9ed7459006ca09b55953b (diff)
sparc: Merge include/asm-sparc{,64}/perfctr.h
Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--include/asm-sparc64/perfctr.h174
1 files changed, 1 insertions, 173 deletions
diff --git a/include/asm-sparc64/perfctr.h b/include/asm-sparc64/perfctr.h
index 836873002b75..52073a9f8e30 100644
--- a/include/asm-sparc64/perfctr.h
+++ b/include/asm-sparc64/perfctr.h
@@ -1,173 +1 @@
1/*---------------------------------------- #include <asm-sparc/perfctr.h>
2 PERFORMANCE INSTRUMENTATION
3 Guillaume Thouvenin 08/10/98
4 David S. Miller 10/06/98
5 ---------------------------------------*/
6#ifndef PERF_COUNTER_API
7#define PERF_COUNTER_API
8
9/* sys_perfctr() interface. First arg is operation code
10 * from enumeration below. The meaning of further arguments
11 * are determined by the operation code.
12 *
13 * int sys_perfctr(int opcode, unsigned long arg0,
14 * unsigned long arg1, unsigned long arg2)
15 *
16 * Pointers which are passed by the user are pointers to 64-bit
17 * integers.
18 *
19 * Once enabled, performance counter state is retained until the
20 * process either exits or performs an exec. That is, performance
21 * counters remain enabled for fork/clone children.
22 */
23enum perfctr_opcode {
24 /* Enable UltraSparc performance counters, ARG0 is pointer
25 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
26 * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
27 * the initial PCR register value to use.
28 */
29 PERFCTR_ON,
30
31 /* Disable UltraSparc performance counters. The PCR is written
32 * with zero and the user counter accumulator pointers and
33 * working PCR register value are forgotten.
34 */
35 PERFCTR_OFF,
36
37 /* Add current D0 and D1 PIC values into user pointers given
38 * in PERFCTR_ON operation. The PIC is cleared before returning.
39 */
40 PERFCTR_READ,
41
42 /* Clear the PIC register. */
43 PERFCTR_CLRPIC,
44
45 /* Begin using a new PCR value, the pointer to which is passed
46 * in ARG0. The PIC is also cleared after the new PCR value is
47 * written.
48 */
49 PERFCTR_SETPCR,
50
51 /* Store in pointer given in ARG0 the current PCR register value
52 * being used.
53 */
54 PERFCTR_GETPCR
55};
56
57/* I don't want the kernel's namespace to be polluted with this
58 * stuff when this file is included. --DaveM
59 */
60#ifndef __KERNEL__
61
62#define PRIV 0x00000001
63#define SYS 0x00000002
64#define USR 0x00000004
65
66/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
67#define CYCLE_CNT 0x00000000
68#define INSTR_CNT 0x00000010
69#define DISPATCH0_IC_MISS 0x00000020
70#define DISPATCH0_STOREBUF 0x00000030
71#define IC_REF 0x00000080
72#define DC_RD 0x00000090
73#define DC_WR 0x000000A0
74#define LOAD_USE 0x000000B0
75#define EC_REF 0x000000C0
76#define EC_WRITE_HIT_RDO 0x000000D0
77#define EC_SNOOP_INV 0x000000E0
78#define EC_RD_HIT 0x000000F0
79
80/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
81#define US3_CYCLE_CNT 0x00000000
82#define US3_INSTR_CNT 0x00000010
83#define US3_DISPATCH0_IC_MISS 0x00000020
84#define US3_DISPATCH0_BR_TGT 0x00000030
85#define US3_DISPATCH0_2ND_BR 0x00000040
86#define US3_RSTALL_STOREQ 0x00000050
87#define US3_RSTALL_IU_USE 0x00000060
88#define US3_IC_REF 0x00000080
89#define US3_DC_RD 0x00000090
90#define US3_DC_WR 0x000000a0
91#define US3_EC_REF 0x000000c0
92#define US3_EC_WR_HIT_RTO 0x000000d0
93#define US3_EC_SNOOP_INV 0x000000e0
94#define US3_EC_RD_MISS 0x000000f0
95#define US3_PC_PORT0_RD 0x00000100
96#define US3_SI_SNOOP 0x00000110
97#define US3_SI_CIQ_FLOW 0x00000120
98#define US3_SI_OWNED 0x00000130
99#define US3_SW_COUNT_0 0x00000140
100#define US3_IU_BR_MISS_TAKEN 0x00000150
101#define US3_IU_BR_COUNT_TAKEN 0x00000160
102#define US3_DISP_RS_MISPRED 0x00000170
103#define US3_FA_PIPE_COMPL 0x00000180
104#define US3_MC_READS_0 0x00000200
105#define US3_MC_READS_1 0x00000210
106#define US3_MC_READS_2 0x00000220
107#define US3_MC_READS_3 0x00000230
108#define US3_MC_STALLS_0 0x00000240
109#define US3_MC_STALLS_2 0x00000250
110
111/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
112#define CYCLE_CNT_D1 0x00000000
113#define INSTR_CNT_D1 0x00000800
114#define DISPATCH0_IC_MISPRED 0x00001000
115#define DISPATCH0_FP_USE 0x00001800
116#define IC_HIT 0x00004000
117#define DC_RD_HIT 0x00004800
118#define DC_WR_HIT 0x00005000
119#define LOAD_USE_RAW 0x00005800
120#define EC_HIT 0x00006000
121#define EC_WB 0x00006800
122#define EC_SNOOP_CB 0x00007000
123#define EC_IT_HIT 0x00007800
124
125/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
126#define US3_CYCLE_CNT_D1 0x00000000
127#define US3_INSTR_CNT_D1 0x00000800
128#define US3_DISPATCH0_MISPRED 0x00001000
129#define US3_IC_MISS_CANCELLED 0x00001800
130#define US3_RE_ENDIAN_MISS 0x00002000
131#define US3_RE_FPU_BYPASS 0x00002800
132#define US3_RE_DC_MISS 0x00003000
133#define US3_RE_EC_MISS 0x00003800
134#define US3_IC_MISS 0x00004000
135#define US3_DC_RD_MISS 0x00004800
136#define US3_DC_WR_MISS 0x00005000
137#define US3_RSTALL_FP_USE 0x00005800
138#define US3_EC_MISSES 0x00006000
139#define US3_EC_WB 0x00006800
140#define US3_EC_SNOOP_CB 0x00007000
141#define US3_EC_IC_MISS 0x00007800
142#define US3_RE_PC_MISS 0x00008000
143#define US3_ITLB_MISS 0x00008800
144#define US3_DTLB_MISS 0x00009000
145#define US3_WC_MISS 0x00009800
146#define US3_WC_SNOOP_CB 0x0000a000
147#define US3_WC_SCRUBBED 0x0000a800
148#define US3_WC_WB_WO_READ 0x0000b000
149#define US3_PC_SOFT_HIT 0x0000c000
150#define US3_PC_SNOOP_INV 0x0000c800
151#define US3_PC_HARD_HIT 0x0000d000
152#define US3_PC_PORT1_RD 0x0000d800
153#define US3_SW_COUNT_1 0x0000e000
154#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
155#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
156#define US3_PC_MS_MISSES 0x0000f800
157#define US3_MC_WRITES_0 0x00010800
158#define US3_MC_WRITES_1 0x00011000
159#define US3_MC_WRITES_2 0x00011800
160#define US3_MC_WRITES_3 0x00012000
161#define US3_MC_STALLS_1 0x00012800
162#define US3_MC_STALLS_3 0x00013000
163#define US3_RE_RAW_MISS 0x00013800
164#define US3_FM_PIPE_COMPLETION 0x00014000
165
166struct vcounter_struct {
167 unsigned long long vcnt0;
168 unsigned long long vcnt1;
169};
170
171#endif /* !(__KERNEL__) */
172
173#endif /* !(PERF_COUNTER_API) */
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