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authorJoonyoung Shim <jy0922.shim@samsung.com>2012-03-16 05:47:03 -0400
committerDave Airlie <airlied@redhat.com>2012-03-20 05:40:20 -0400
commit3ecd70b18cad5a5e04981f2a1d71e183f5d6ebc0 (patch)
tree1f933966ea366f6039efe9d77967434c906dceba
parent22b21ae6b84f7df62e77f05f58bb4360146c5414 (diff)
drm/exynos: add HDMI version 1.4 support
Later Exynos series from Exynos4X12 support HDMI version 1.4. We will distinguish to use which version via platform data. This patch supports only default features of HDMI version 1.4(The 3D, sound and etc don't support yet) Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c1152
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.h10
-rw-r--r--drivers/gpu/drm/exynos/regs-hdmi.h306
-rw-r--r--include/drm/exynos_drm.h2
4 files changed, 1325 insertions, 145 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 3429d3fd93f3..1cfe86e5d10e 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -43,42 +43,43 @@
43#define HDMI_OVERLAY_NUMBER 3 43#define HDMI_OVERLAY_NUMBER 3
44#define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev)) 44#define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev))
45 45
46static const u8 hdmiphy_conf27[32] = { 46/* HDMI Version 1.3 */
47static const u8 hdmiphy_v13_conf27[32] = {
47 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 48 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
48 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 49 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
49 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 50 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
50 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, 51 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
51}; 52};
52 53
53static const u8 hdmiphy_conf27_027[32] = { 54static const u8 hdmiphy_v13_conf27_027[32] = {
54 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 55 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
55 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 56 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
56 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 57 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
57 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, 58 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
58}; 59};
59 60
60static const u8 hdmiphy_conf74_175[32] = { 61static const u8 hdmiphy_v13_conf74_175[32] = {
61 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 62 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
62 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 63 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
63 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 64 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
64 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00, 65 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
65}; 66};
66 67
67static const u8 hdmiphy_conf74_25[32] = { 68static const u8 hdmiphy_v13_conf74_25[32] = {
68 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 69 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
69 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 70 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
70 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 71 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
71 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00, 72 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
72}; 73};
73 74
74static const u8 hdmiphy_conf148_5[32] = { 75static const u8 hdmiphy_v13_conf148_5[32] = {
75 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 76 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
76 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 77 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
77 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 78 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
78 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00, 79 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
79}; 80};
80 81
81struct hdmi_tg_regs { 82struct hdmi_v13_tg_regs {
82 u8 cmd; 83 u8 cmd;
83 u8 h_fsz_l; 84 u8 h_fsz_l;
84 u8 h_fsz_h; 85 u8 h_fsz_h;
@@ -110,7 +111,7 @@ struct hdmi_tg_regs {
110 u8 field_bot_hdmi_h; 111 u8 field_bot_hdmi_h;
111}; 112};
112 113
113struct hdmi_core_regs { 114struct hdmi_v13_core_regs {
114 u8 h_blank[2]; 115 u8 h_blank[2];
115 u8 v_blank[3]; 116 u8 v_blank[3];
116 u8 h_v_line[3]; 117 u8 h_v_line[3];
@@ -123,12 +124,21 @@ struct hdmi_core_regs {
123 u8 v_sync_gen3[3]; 124 u8 v_sync_gen3[3];
124}; 125};
125 126
126struct hdmi_preset_conf { 127struct hdmi_v13_preset_conf {
127 struct hdmi_core_regs core; 128 struct hdmi_v13_core_regs core;
128 struct hdmi_tg_regs tg; 129 struct hdmi_v13_tg_regs tg;
130};
131
132struct hdmi_v13_conf {
133 int width;
134 int height;
135 int vrefresh;
136 bool interlace;
137 const u8 *hdmiphy_data;
138 const struct hdmi_v13_preset_conf *conf;
129}; 139};
130 140
131static const struct hdmi_preset_conf hdmi_conf_480p = { 141static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
132 .core = { 142 .core = {
133 .h_blank = {0x8a, 0x00}, 143 .h_blank = {0x8a, 0x00},
134 .v_blank = {0x0d, 0x6a, 0x01}, 144 .v_blank = {0x0d, 0x6a, 0x01},
@@ -154,7 +164,7 @@ static const struct hdmi_preset_conf hdmi_conf_480p = {
154 }, 164 },
155}; 165};
156 166
157static const struct hdmi_preset_conf hdmi_conf_720p60 = { 167static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
158 .core = { 168 .core = {
159 .h_blank = {0x72, 0x01}, 169 .h_blank = {0x72, 0x01},
160 .v_blank = {0xee, 0xf2, 0x00}, 170 .v_blank = {0xee, 0xf2, 0x00},
@@ -182,7 +192,7 @@ static const struct hdmi_preset_conf hdmi_conf_720p60 = {
182 }, 192 },
183}; 193};
184 194
185static const struct hdmi_preset_conf hdmi_conf_1080i50 = { 195static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
186 .core = { 196 .core = {
187 .h_blank = {0xd0, 0x02}, 197 .h_blank = {0xd0, 0x02},
188 .v_blank = {0x32, 0xB2, 0x00}, 198 .v_blank = {0x32, 0xB2, 0x00},
@@ -210,7 +220,7 @@ static const struct hdmi_preset_conf hdmi_conf_1080i50 = {
210 }, 220 },
211}; 221};
212 222
213static const struct hdmi_preset_conf hdmi_conf_1080p50 = { 223static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
214 .core = { 224 .core = {
215 .h_blank = {0xd0, 0x02}, 225 .h_blank = {0xd0, 0x02},
216 .v_blank = {0x65, 0x6c, 0x01}, 226 .v_blank = {0x65, 0x6c, 0x01},
@@ -238,7 +248,7 @@ static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
238 }, 248 },
239}; 249};
240 250
241static const struct hdmi_preset_conf hdmi_conf_1080i60 = { 251static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
242 .core = { 252 .core = {
243 .h_blank = {0x18, 0x01}, 253 .h_blank = {0x18, 0x01},
244 .v_blank = {0x32, 0xB2, 0x00}, 254 .v_blank = {0x32, 0xB2, 0x00},
@@ -266,7 +276,7 @@ static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
266 }, 276 },
267}; 277};
268 278
269static const struct hdmi_preset_conf hdmi_conf_1080p60 = { 279static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
270 .core = { 280 .core = {
271 .h_blank = {0x18, 0x01}, 281 .h_blank = {0x18, 0x01},
272 .v_blank = {0x65, 0x6c, 0x01}, 282 .v_blank = {0x65, 0x6c, 0x01},
@@ -294,13 +304,530 @@ static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
294 }, 304 },
295}; 305};
296 306
307static const struct hdmi_v13_conf hdmi_v13_confs[] = {
308 { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
309 { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
310 { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
311 { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
312 { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
313 &hdmi_v13_conf_1080p50 },
314 { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
315 { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
316 &hdmi_v13_conf_1080p60 },
317};
318
319/* HDMI Version 1.4 */
320static const u8 hdmiphy_conf27_027[32] = {
321 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
322 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
323 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
324 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
325};
326
327static const u8 hdmiphy_conf74_25[32] = {
328 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
329 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
330 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
331 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
332};
333
334static const u8 hdmiphy_conf148_5[32] = {
335 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
336 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
337 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
338 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
339};
340
341struct hdmi_tg_regs {
342 u8 cmd;
343 u8 h_fsz_l;
344 u8 h_fsz_h;
345 u8 hact_st_l;
346 u8 hact_st_h;
347 u8 hact_sz_l;
348 u8 hact_sz_h;
349 u8 v_fsz_l;
350 u8 v_fsz_h;
351 u8 vsync_l;
352 u8 vsync_h;
353 u8 vsync2_l;
354 u8 vsync2_h;
355 u8 vact_st_l;
356 u8 vact_st_h;
357 u8 vact_sz_l;
358 u8 vact_sz_h;
359 u8 field_chg_l;
360 u8 field_chg_h;
361 u8 vact_st2_l;
362 u8 vact_st2_h;
363 u8 vact_st3_l;
364 u8 vact_st3_h;
365 u8 vact_st4_l;
366 u8 vact_st4_h;
367 u8 vsync_top_hdmi_l;
368 u8 vsync_top_hdmi_h;
369 u8 vsync_bot_hdmi_l;
370 u8 vsync_bot_hdmi_h;
371 u8 field_top_hdmi_l;
372 u8 field_top_hdmi_h;
373 u8 field_bot_hdmi_l;
374 u8 field_bot_hdmi_h;
375 u8 tg_3d;
376};
377
378struct hdmi_core_regs {
379 u8 h_blank[2];
380 u8 v2_blank[2];
381 u8 v1_blank[2];
382 u8 v_line[2];
383 u8 h_line[2];
384 u8 hsync_pol[1];
385 u8 vsync_pol[1];
386 u8 int_pro_mode[1];
387 u8 v_blank_f0[2];
388 u8 v_blank_f1[2];
389 u8 h_sync_start[2];
390 u8 h_sync_end[2];
391 u8 v_sync_line_bef_2[2];
392 u8 v_sync_line_bef_1[2];
393 u8 v_sync_line_aft_2[2];
394 u8 v_sync_line_aft_1[2];
395 u8 v_sync_line_aft_pxl_2[2];
396 u8 v_sync_line_aft_pxl_1[2];
397 u8 v_blank_f2[2]; /* for 3D mode */
398 u8 v_blank_f3[2]; /* for 3D mode */
399 u8 v_blank_f4[2]; /* for 3D mode */
400 u8 v_blank_f5[2]; /* for 3D mode */
401 u8 v_sync_line_aft_3[2];
402 u8 v_sync_line_aft_4[2];
403 u8 v_sync_line_aft_5[2];
404 u8 v_sync_line_aft_6[2];
405 u8 v_sync_line_aft_pxl_3[2];
406 u8 v_sync_line_aft_pxl_4[2];
407 u8 v_sync_line_aft_pxl_5[2];
408 u8 v_sync_line_aft_pxl_6[2];
409 u8 vact_space_1[2];
410 u8 vact_space_2[2];
411 u8 vact_space_3[2];
412 u8 vact_space_4[2];
413 u8 vact_space_5[2];
414 u8 vact_space_6[2];
415};
416
417struct hdmi_preset_conf {
418 struct hdmi_core_regs core;
419 struct hdmi_tg_regs tg;
420};
421
422struct hdmi_conf {
423 int width;
424 int height;
425 int vrefresh;
426 bool interlace;
427 const u8 *hdmiphy_data;
428 const struct hdmi_preset_conf *conf;
429};
430
431static const struct hdmi_preset_conf hdmi_conf_480p60 = {
432 .core = {
433 .h_blank = {0x8a, 0x00},
434 .v2_blank = {0x0d, 0x02},
435 .v1_blank = {0x2d, 0x00},
436 .v_line = {0x0d, 0x02},
437 .h_line = {0x5a, 0x03},
438 .hsync_pol = {0x01},
439 .vsync_pol = {0x01},
440 .int_pro_mode = {0x00},
441 .v_blank_f0 = {0xff, 0xff},
442 .v_blank_f1 = {0xff, 0xff},
443 .h_sync_start = {0x0e, 0x00},
444 .h_sync_end = {0x4c, 0x00},
445 .v_sync_line_bef_2 = {0x0f, 0x00},
446 .v_sync_line_bef_1 = {0x09, 0x00},
447 .v_sync_line_aft_2 = {0xff, 0xff},
448 .v_sync_line_aft_1 = {0xff, 0xff},
449 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
450 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
451 .v_blank_f2 = {0xff, 0xff},
452 .v_blank_f3 = {0xff, 0xff},
453 .v_blank_f4 = {0xff, 0xff},
454 .v_blank_f5 = {0xff, 0xff},
455 .v_sync_line_aft_3 = {0xff, 0xff},
456 .v_sync_line_aft_4 = {0xff, 0xff},
457 .v_sync_line_aft_5 = {0xff, 0xff},
458 .v_sync_line_aft_6 = {0xff, 0xff},
459 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
460 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
461 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
462 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
463 .vact_space_1 = {0xff, 0xff},
464 .vact_space_2 = {0xff, 0xff},
465 .vact_space_3 = {0xff, 0xff},
466 .vact_space_4 = {0xff, 0xff},
467 .vact_space_5 = {0xff, 0xff},
468 .vact_space_6 = {0xff, 0xff},
469 /* other don't care */
470 },
471 .tg = {
472 0x00, /* cmd */
473 0x5a, 0x03, /* h_fsz */
474 0x8a, 0x00, 0xd0, 0x02, /* hact */
475 0x0d, 0x02, /* v_fsz */
476 0x01, 0x00, 0x33, 0x02, /* vsync */
477 0x2d, 0x00, 0xe0, 0x01, /* vact */
478 0x33, 0x02, /* field_chg */
479 0x48, 0x02, /* vact_st2 */
480 0x00, 0x00, /* vact_st3 */
481 0x00, 0x00, /* vact_st4 */
482 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
483 0x01, 0x00, 0x33, 0x02, /* field top/bot */
484 0x00, /* 3d FP */
485 },
486};
487
488static const struct hdmi_preset_conf hdmi_conf_720p50 = {
489 .core = {
490 .h_blank = {0xbc, 0x02},
491 .v2_blank = {0xee, 0x02},
492 .v1_blank = {0x1e, 0x00},
493 .v_line = {0xee, 0x02},
494 .h_line = {0xbc, 0x07},
495 .hsync_pol = {0x00},
496 .vsync_pol = {0x00},
497 .int_pro_mode = {0x00},
498 .v_blank_f0 = {0xff, 0xff},
499 .v_blank_f1 = {0xff, 0xff},
500 .h_sync_start = {0xb6, 0x01},
501 .h_sync_end = {0xde, 0x01},
502 .v_sync_line_bef_2 = {0x0a, 0x00},
503 .v_sync_line_bef_1 = {0x05, 0x00},
504 .v_sync_line_aft_2 = {0xff, 0xff},
505 .v_sync_line_aft_1 = {0xff, 0xff},
506 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
507 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
508 .v_blank_f2 = {0xff, 0xff},
509 .v_blank_f3 = {0xff, 0xff},
510 .v_blank_f4 = {0xff, 0xff},
511 .v_blank_f5 = {0xff, 0xff},
512 .v_sync_line_aft_3 = {0xff, 0xff},
513 .v_sync_line_aft_4 = {0xff, 0xff},
514 .v_sync_line_aft_5 = {0xff, 0xff},
515 .v_sync_line_aft_6 = {0xff, 0xff},
516 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
517 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
518 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
519 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
520 .vact_space_1 = {0xff, 0xff},
521 .vact_space_2 = {0xff, 0xff},
522 .vact_space_3 = {0xff, 0xff},
523 .vact_space_4 = {0xff, 0xff},
524 .vact_space_5 = {0xff, 0xff},
525 .vact_space_6 = {0xff, 0xff},
526 /* other don't care */
527 },
528 .tg = {
529 0x00, /* cmd */
530 0xbc, 0x07, /* h_fsz */
531 0xbc, 0x02, 0x00, 0x05, /* hact */
532 0xee, 0x02, /* v_fsz */
533 0x01, 0x00, 0x33, 0x02, /* vsync */
534 0x1e, 0x00, 0xd0, 0x02, /* vact */
535 0x33, 0x02, /* field_chg */
536 0x48, 0x02, /* vact_st2 */
537 0x00, 0x00, /* vact_st3 */
538 0x00, 0x00, /* vact_st4 */
539 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
540 0x01, 0x00, 0x33, 0x02, /* field top/bot */
541 0x00, /* 3d FP */
542 },
543};
544
545static const struct hdmi_preset_conf hdmi_conf_720p60 = {
546 .core = {
547 .h_blank = {0x72, 0x01},
548 .v2_blank = {0xee, 0x02},
549 .v1_blank = {0x1e, 0x00},
550 .v_line = {0xee, 0x02},
551 .h_line = {0x72, 0x06},
552 .hsync_pol = {0x00},
553 .vsync_pol = {0x00},
554 .int_pro_mode = {0x00},
555 .v_blank_f0 = {0xff, 0xff},
556 .v_blank_f1 = {0xff, 0xff},
557 .h_sync_start = {0x6c, 0x00},
558 .h_sync_end = {0x94, 0x00},
559 .v_sync_line_bef_2 = {0x0a, 0x00},
560 .v_sync_line_bef_1 = {0x05, 0x00},
561 .v_sync_line_aft_2 = {0xff, 0xff},
562 .v_sync_line_aft_1 = {0xff, 0xff},
563 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
564 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
565 .v_blank_f2 = {0xff, 0xff},
566 .v_blank_f3 = {0xff, 0xff},
567 .v_blank_f4 = {0xff, 0xff},
568 .v_blank_f5 = {0xff, 0xff},
569 .v_sync_line_aft_3 = {0xff, 0xff},
570 .v_sync_line_aft_4 = {0xff, 0xff},
571 .v_sync_line_aft_5 = {0xff, 0xff},
572 .v_sync_line_aft_6 = {0xff, 0xff},
573 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
574 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
575 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
576 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
577 .vact_space_1 = {0xff, 0xff},
578 .vact_space_2 = {0xff, 0xff},
579 .vact_space_3 = {0xff, 0xff},
580 .vact_space_4 = {0xff, 0xff},
581 .vact_space_5 = {0xff, 0xff},
582 .vact_space_6 = {0xff, 0xff},
583 /* other don't care */
584 },
585 .tg = {
586 0x00, /* cmd */
587 0x72, 0x06, /* h_fsz */
588 0x72, 0x01, 0x00, 0x05, /* hact */
589 0xee, 0x02, /* v_fsz */
590 0x01, 0x00, 0x33, 0x02, /* vsync */
591 0x1e, 0x00, 0xd0, 0x02, /* vact */
592 0x33, 0x02, /* field_chg */
593 0x48, 0x02, /* vact_st2 */
594 0x00, 0x00, /* vact_st3 */
595 0x00, 0x00, /* vact_st4 */
596 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
597 0x01, 0x00, 0x33, 0x02, /* field top/bot */
598 0x00, /* 3d FP */
599 },
600};
601
602static const struct hdmi_preset_conf hdmi_conf_1080i50 = {
603 .core = {
604 .h_blank = {0xd0, 0x02},
605 .v2_blank = {0x32, 0x02},
606 .v1_blank = {0x16, 0x00},
607 .v_line = {0x65, 0x04},
608 .h_line = {0x50, 0x0a},
609 .hsync_pol = {0x00},
610 .vsync_pol = {0x00},
611 .int_pro_mode = {0x01},
612 .v_blank_f0 = {0x49, 0x02},
613 .v_blank_f1 = {0x65, 0x04},
614 .h_sync_start = {0x0e, 0x02},
615 .h_sync_end = {0x3a, 0x02},
616 .v_sync_line_bef_2 = {0x07, 0x00},
617 .v_sync_line_bef_1 = {0x02, 0x00},
618 .v_sync_line_aft_2 = {0x39, 0x02},
619 .v_sync_line_aft_1 = {0x34, 0x02},
620 .v_sync_line_aft_pxl_2 = {0x38, 0x07},
621 .v_sync_line_aft_pxl_1 = {0x38, 0x07},
622 .v_blank_f2 = {0xff, 0xff},
623 .v_blank_f3 = {0xff, 0xff},
624 .v_blank_f4 = {0xff, 0xff},
625 .v_blank_f5 = {0xff, 0xff},
626 .v_sync_line_aft_3 = {0xff, 0xff},
627 .v_sync_line_aft_4 = {0xff, 0xff},
628 .v_sync_line_aft_5 = {0xff, 0xff},
629 .v_sync_line_aft_6 = {0xff, 0xff},
630 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
631 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
632 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
633 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
634 .vact_space_1 = {0xff, 0xff},
635 .vact_space_2 = {0xff, 0xff},
636 .vact_space_3 = {0xff, 0xff},
637 .vact_space_4 = {0xff, 0xff},
638 .vact_space_5 = {0xff, 0xff},
639 .vact_space_6 = {0xff, 0xff},
640 /* other don't care */
641 },
642 .tg = {
643 0x00, /* cmd */
644 0x50, 0x0a, /* h_fsz */
645 0xd0, 0x02, 0x80, 0x07, /* hact */
646 0x65, 0x04, /* v_fsz */
647 0x01, 0x00, 0x33, 0x02, /* vsync */
648 0x16, 0x00, 0x1c, 0x02, /* vact */
649 0x33, 0x02, /* field_chg */
650 0x49, 0x02, /* vact_st2 */
651 0x00, 0x00, /* vact_st3 */
652 0x00, 0x00, /* vact_st4 */
653 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
654 0x01, 0x00, 0x33, 0x02, /* field top/bot */
655 0x00, /* 3d FP */
656 },
657};
658
659static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
660 .core = {
661 .h_blank = {0x18, 0x01},
662 .v2_blank = {0x32, 0x02},
663 .v1_blank = {0x16, 0x00},
664 .v_line = {0x65, 0x04},
665 .h_line = {0x98, 0x08},
666 .hsync_pol = {0x00},
667 .vsync_pol = {0x00},
668 .int_pro_mode = {0x01},
669 .v_blank_f0 = {0x49, 0x02},
670 .v_blank_f1 = {0x65, 0x04},
671 .h_sync_start = {0x56, 0x00},
672 .h_sync_end = {0x82, 0x00},
673 .v_sync_line_bef_2 = {0x07, 0x00},
674 .v_sync_line_bef_1 = {0x02, 0x00},
675 .v_sync_line_aft_2 = {0x39, 0x02},
676 .v_sync_line_aft_1 = {0x34, 0x02},
677 .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
678 .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
679 .v_blank_f2 = {0xff, 0xff},
680 .v_blank_f3 = {0xff, 0xff},
681 .v_blank_f4 = {0xff, 0xff},
682 .v_blank_f5 = {0xff, 0xff},
683 .v_sync_line_aft_3 = {0xff, 0xff},
684 .v_sync_line_aft_4 = {0xff, 0xff},
685 .v_sync_line_aft_5 = {0xff, 0xff},
686 .v_sync_line_aft_6 = {0xff, 0xff},
687 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
688 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
689 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
690 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
691 .vact_space_1 = {0xff, 0xff},
692 .vact_space_2 = {0xff, 0xff},
693 .vact_space_3 = {0xff, 0xff},
694 .vact_space_4 = {0xff, 0xff},
695 .vact_space_5 = {0xff, 0xff},
696 .vact_space_6 = {0xff, 0xff},
697 /* other don't care */
698 },
699 .tg = {
700 0x00, /* cmd */
701 0x98, 0x08, /* h_fsz */
702 0x18, 0x01, 0x80, 0x07, /* hact */
703 0x65, 0x04, /* v_fsz */
704 0x01, 0x00, 0x33, 0x02, /* vsync */
705 0x16, 0x00, 0x1c, 0x02, /* vact */
706 0x33, 0x02, /* field_chg */
707 0x49, 0x02, /* vact_st2 */
708 0x00, 0x00, /* vact_st3 */
709 0x00, 0x00, /* vact_st4 */
710 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
711 0x01, 0x00, 0x33, 0x02, /* field top/bot */
712 0x00, /* 3d FP */
713 },
714};
715
716static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
717 .core = {
718 .h_blank = {0xd0, 0x02},
719 .v2_blank = {0x65, 0x04},
720 .v1_blank = {0x2d, 0x00},
721 .v_line = {0x65, 0x04},
722 .h_line = {0x50, 0x0a},
723 .hsync_pol = {0x00},
724 .vsync_pol = {0x00},
725 .int_pro_mode = {0x00},
726 .v_blank_f0 = {0xff, 0xff},
727 .v_blank_f1 = {0xff, 0xff},
728 .h_sync_start = {0x0e, 0x02},
729 .h_sync_end = {0x3a, 0x02},
730 .v_sync_line_bef_2 = {0x09, 0x00},
731 .v_sync_line_bef_1 = {0x04, 0x00},
732 .v_sync_line_aft_2 = {0xff, 0xff},
733 .v_sync_line_aft_1 = {0xff, 0xff},
734 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
735 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
736 .v_blank_f2 = {0xff, 0xff},
737 .v_blank_f3 = {0xff, 0xff},
738 .v_blank_f4 = {0xff, 0xff},
739 .v_blank_f5 = {0xff, 0xff},
740 .v_sync_line_aft_3 = {0xff, 0xff},
741 .v_sync_line_aft_4 = {0xff, 0xff},
742 .v_sync_line_aft_5 = {0xff, 0xff},
743 .v_sync_line_aft_6 = {0xff, 0xff},
744 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
745 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
746 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
747 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
748 .vact_space_1 = {0xff, 0xff},
749 .vact_space_2 = {0xff, 0xff},
750 .vact_space_3 = {0xff, 0xff},
751 .vact_space_4 = {0xff, 0xff},
752 .vact_space_5 = {0xff, 0xff},
753 .vact_space_6 = {0xff, 0xff},
754 /* other don't care */
755 },
756 .tg = {
757 0x00, /* cmd */
758 0x50, 0x0a, /* h_fsz */
759 0xd0, 0x02, 0x80, 0x07, /* hact */
760 0x65, 0x04, /* v_fsz */
761 0x01, 0x00, 0x33, 0x02, /* vsync */
762 0x2d, 0x00, 0x38, 0x04, /* vact */
763 0x33, 0x02, /* field_chg */
764 0x48, 0x02, /* vact_st2 */
765 0x00, 0x00, /* vact_st3 */
766 0x00, 0x00, /* vact_st4 */
767 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
768 0x01, 0x00, 0x33, 0x02, /* field top/bot */
769 0x00, /* 3d FP */
770 },
771};
772
773static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
774 .core = {
775 .h_blank = {0x18, 0x01},
776 .v2_blank = {0x65, 0x04},
777 .v1_blank = {0x2d, 0x00},
778 .v_line = {0x65, 0x04},
779 .h_line = {0x98, 0x08},
780 .hsync_pol = {0x00},
781 .vsync_pol = {0x00},
782 .int_pro_mode = {0x00},
783 .v_blank_f0 = {0xff, 0xff},
784 .v_blank_f1 = {0xff, 0xff},
785 .h_sync_start = {0x56, 0x00},
786 .h_sync_end = {0x82, 0x00},
787 .v_sync_line_bef_2 = {0x09, 0x00},
788 .v_sync_line_bef_1 = {0x04, 0x00},
789 .v_sync_line_aft_2 = {0xff, 0xff},
790 .v_sync_line_aft_1 = {0xff, 0xff},
791 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
792 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
793 .v_blank_f2 = {0xff, 0xff},
794 .v_blank_f3 = {0xff, 0xff},
795 .v_blank_f4 = {0xff, 0xff},
796 .v_blank_f5 = {0xff, 0xff},
797 .v_sync_line_aft_3 = {0xff, 0xff},
798 .v_sync_line_aft_4 = {0xff, 0xff},
799 .v_sync_line_aft_5 = {0xff, 0xff},
800 .v_sync_line_aft_6 = {0xff, 0xff},
801 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
802 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
803 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
804 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
805 /* other don't care */
806 },
807 .tg = {
808 0x00, /* cmd */
809 0x98, 0x08, /* h_fsz */
810 0x18, 0x01, 0x80, 0x07, /* hact */
811 0x65, 0x04, /* v_fsz */
812 0x01, 0x00, 0x33, 0x02, /* vsync */
813 0x2d, 0x00, 0x38, 0x04, /* vact */
814 0x33, 0x02, /* field_chg */
815 0x48, 0x02, /* vact_st2 */
816 0x00, 0x00, /* vact_st3 */
817 0x00, 0x00, /* vact_st4 */
818 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
819 0x01, 0x00, 0x33, 0x02, /* field top/bot */
820 0x00, /* 3d FP */
821 },
822};
823
297static const struct hdmi_conf hdmi_confs[] = { 824static const struct hdmi_conf hdmi_confs[] = {
825 { 720, 480, 60, false, hdmiphy_conf27_027, &hdmi_conf_480p60 },
826 { 1280, 720, 50, false, hdmiphy_conf74_25, &hdmi_conf_720p50 },
298 { 1280, 720, 60, false, hdmiphy_conf74_25, &hdmi_conf_720p60 }, 827 { 1280, 720, 60, false, hdmiphy_conf74_25, &hdmi_conf_720p60 },
299 { 1280, 720, 50, false, hdmiphy_conf74_25, &hdmi_conf_720p60 },
300 { 720, 480, 60, false, hdmiphy_conf27_027, &hdmi_conf_480p },
301 { 1920, 1080, 50, true, hdmiphy_conf74_25, &hdmi_conf_1080i50 }, 828 { 1920, 1080, 50, true, hdmiphy_conf74_25, &hdmi_conf_1080i50 },
302 { 1920, 1080, 50, false, hdmiphy_conf148_5, &hdmi_conf_1080p50 },
303 { 1920, 1080, 60, true, hdmiphy_conf74_25, &hdmi_conf_1080i60 }, 829 { 1920, 1080, 60, true, hdmiphy_conf74_25, &hdmi_conf_1080i60 },
830 { 1920, 1080, 50, false, hdmiphy_conf148_5, &hdmi_conf_1080p50 },
304 { 1920, 1080, 60, false, hdmiphy_conf148_5, &hdmi_conf_1080p60 }, 831 { 1920, 1080, 60, false, hdmiphy_conf148_5, &hdmi_conf_1080p60 },
305}; 832};
306 833
@@ -324,7 +851,7 @@ static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
324 writel(value, hdata->regs + reg_id); 851 writel(value, hdata->regs + reg_id);
325} 852}
326 853
327static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix) 854static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
328{ 855{
329#define DUMPREG(reg_id) \ 856#define DUMPREG(reg_id) \
330 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \ 857 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
@@ -333,6 +860,101 @@ static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
333 DUMPREG(HDMI_INTC_FLAG); 860 DUMPREG(HDMI_INTC_FLAG);
334 DUMPREG(HDMI_INTC_CON); 861 DUMPREG(HDMI_INTC_CON);
335 DUMPREG(HDMI_HPD_STATUS); 862 DUMPREG(HDMI_HPD_STATUS);
863 DUMPREG(HDMI_V13_PHY_RSTOUT);
864 DUMPREG(HDMI_V13_PHY_VPLL);
865 DUMPREG(HDMI_V13_PHY_CMU);
866 DUMPREG(HDMI_V13_CORE_RSTOUT);
867
868 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
869 DUMPREG(HDMI_CON_0);
870 DUMPREG(HDMI_CON_1);
871 DUMPREG(HDMI_CON_2);
872 DUMPREG(HDMI_SYS_STATUS);
873 DUMPREG(HDMI_V13_PHY_STATUS);
874 DUMPREG(HDMI_STATUS_EN);
875 DUMPREG(HDMI_HPD);
876 DUMPREG(HDMI_MODE_SEL);
877 DUMPREG(HDMI_V13_HPD_GEN);
878 DUMPREG(HDMI_V13_DC_CONTROL);
879 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
880
881 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
882 DUMPREG(HDMI_H_BLANK_0);
883 DUMPREG(HDMI_H_BLANK_1);
884 DUMPREG(HDMI_V13_V_BLANK_0);
885 DUMPREG(HDMI_V13_V_BLANK_1);
886 DUMPREG(HDMI_V13_V_BLANK_2);
887 DUMPREG(HDMI_V13_H_V_LINE_0);
888 DUMPREG(HDMI_V13_H_V_LINE_1);
889 DUMPREG(HDMI_V13_H_V_LINE_2);
890 DUMPREG(HDMI_VSYNC_POL);
891 DUMPREG(HDMI_INT_PRO_MODE);
892 DUMPREG(HDMI_V13_V_BLANK_F_0);
893 DUMPREG(HDMI_V13_V_BLANK_F_1);
894 DUMPREG(HDMI_V13_V_BLANK_F_2);
895 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
896 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
897 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
898 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
899 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
900 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
901 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
902 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
903 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
904 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
905 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
906 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
907
908 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
909 DUMPREG(HDMI_TG_CMD);
910 DUMPREG(HDMI_TG_H_FSZ_L);
911 DUMPREG(HDMI_TG_H_FSZ_H);
912 DUMPREG(HDMI_TG_HACT_ST_L);
913 DUMPREG(HDMI_TG_HACT_ST_H);
914 DUMPREG(HDMI_TG_HACT_SZ_L);
915 DUMPREG(HDMI_TG_HACT_SZ_H);
916 DUMPREG(HDMI_TG_V_FSZ_L);
917 DUMPREG(HDMI_TG_V_FSZ_H);
918 DUMPREG(HDMI_TG_VSYNC_L);
919 DUMPREG(HDMI_TG_VSYNC_H);
920 DUMPREG(HDMI_TG_VSYNC2_L);
921 DUMPREG(HDMI_TG_VSYNC2_H);
922 DUMPREG(HDMI_TG_VACT_ST_L);
923 DUMPREG(HDMI_TG_VACT_ST_H);
924 DUMPREG(HDMI_TG_VACT_SZ_L);
925 DUMPREG(HDMI_TG_VACT_SZ_H);
926 DUMPREG(HDMI_TG_FIELD_CHG_L);
927 DUMPREG(HDMI_TG_FIELD_CHG_H);
928 DUMPREG(HDMI_TG_VACT_ST2_L);
929 DUMPREG(HDMI_TG_VACT_ST2_H);
930 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
931 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
932 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
933 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
934 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
935 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
936 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
937 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
938#undef DUMPREG
939}
940
941static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
942{
943 int i;
944
945#define DUMPREG(reg_id) \
946 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
947 readl(hdata->regs + reg_id))
948
949 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
950 DUMPREG(HDMI_INTC_CON);
951 DUMPREG(HDMI_INTC_FLAG);
952 DUMPREG(HDMI_HPD_STATUS);
953 DUMPREG(HDMI_INTC_CON_1);
954 DUMPREG(HDMI_INTC_FLAG_1);
955 DUMPREG(HDMI_PHY_STATUS_0);
956 DUMPREG(HDMI_PHY_STATUS_PLL);
957 DUMPREG(HDMI_PHY_CON_0);
336 DUMPREG(HDMI_PHY_RSTOUT); 958 DUMPREG(HDMI_PHY_RSTOUT);
337 DUMPREG(HDMI_PHY_VPLL); 959 DUMPREG(HDMI_PHY_VPLL);
338 DUMPREG(HDMI_PHY_CMU); 960 DUMPREG(HDMI_PHY_CMU);
@@ -343,40 +965,93 @@ static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
343 DUMPREG(HDMI_CON_1); 965 DUMPREG(HDMI_CON_1);
344 DUMPREG(HDMI_CON_2); 966 DUMPREG(HDMI_CON_2);
345 DUMPREG(HDMI_SYS_STATUS); 967 DUMPREG(HDMI_SYS_STATUS);
346 DUMPREG(HDMI_PHY_STATUS); 968 DUMPREG(HDMI_PHY_STATUS_0);
347 DUMPREG(HDMI_STATUS_EN); 969 DUMPREG(HDMI_STATUS_EN);
348 DUMPREG(HDMI_HPD); 970 DUMPREG(HDMI_HPD);
349 DUMPREG(HDMI_MODE_SEL); 971 DUMPREG(HDMI_MODE_SEL);
350 DUMPREG(HDMI_HPD_GEN); 972 DUMPREG(HDMI_ENC_EN);
351 DUMPREG(HDMI_DC_CONTROL); 973 DUMPREG(HDMI_DC_CONTROL);
352 DUMPREG(HDMI_VIDEO_PATTERN_GEN); 974 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
353 975
354 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix); 976 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
355 DUMPREG(HDMI_H_BLANK_0); 977 DUMPREG(HDMI_H_BLANK_0);
356 DUMPREG(HDMI_H_BLANK_1); 978 DUMPREG(HDMI_H_BLANK_1);
357 DUMPREG(HDMI_V_BLANK_0); 979 DUMPREG(HDMI_V2_BLANK_0);
358 DUMPREG(HDMI_V_BLANK_1); 980 DUMPREG(HDMI_V2_BLANK_1);
359 DUMPREG(HDMI_V_BLANK_2); 981 DUMPREG(HDMI_V1_BLANK_0);
360 DUMPREG(HDMI_H_V_LINE_0); 982 DUMPREG(HDMI_V1_BLANK_1);
361 DUMPREG(HDMI_H_V_LINE_1); 983 DUMPREG(HDMI_V_LINE_0);
362 DUMPREG(HDMI_H_V_LINE_2); 984 DUMPREG(HDMI_V_LINE_1);
985 DUMPREG(HDMI_H_LINE_0);
986 DUMPREG(HDMI_H_LINE_1);
987 DUMPREG(HDMI_HSYNC_POL);
988
363 DUMPREG(HDMI_VSYNC_POL); 989 DUMPREG(HDMI_VSYNC_POL);
364 DUMPREG(HDMI_INT_PRO_MODE); 990 DUMPREG(HDMI_INT_PRO_MODE);
365 DUMPREG(HDMI_V_BLANK_F_0); 991 DUMPREG(HDMI_V_BLANK_F0_0);
366 DUMPREG(HDMI_V_BLANK_F_1); 992 DUMPREG(HDMI_V_BLANK_F0_1);
367 DUMPREG(HDMI_V_BLANK_F_2); 993 DUMPREG(HDMI_V_BLANK_F1_0);
368 DUMPREG(HDMI_H_SYNC_GEN_0); 994 DUMPREG(HDMI_V_BLANK_F1_1);
369 DUMPREG(HDMI_H_SYNC_GEN_1); 995
370 DUMPREG(HDMI_H_SYNC_GEN_2); 996 DUMPREG(HDMI_H_SYNC_START_0);
371 DUMPREG(HDMI_V_SYNC_GEN_1_0); 997 DUMPREG(HDMI_H_SYNC_START_1);
372 DUMPREG(HDMI_V_SYNC_GEN_1_1); 998 DUMPREG(HDMI_H_SYNC_END_0);
373 DUMPREG(HDMI_V_SYNC_GEN_1_2); 999 DUMPREG(HDMI_H_SYNC_END_1);
374 DUMPREG(HDMI_V_SYNC_GEN_2_0); 1000
375 DUMPREG(HDMI_V_SYNC_GEN_2_1); 1001 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
376 DUMPREG(HDMI_V_SYNC_GEN_2_2); 1002 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
377 DUMPREG(HDMI_V_SYNC_GEN_3_0); 1003 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
378 DUMPREG(HDMI_V_SYNC_GEN_3_1); 1004 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
379 DUMPREG(HDMI_V_SYNC_GEN_3_2); 1005
1006 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
1007 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
1008 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
1009 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
1010
1011 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
1012 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
1013 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
1014 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
1015
1016 DUMPREG(HDMI_V_BLANK_F2_0);
1017 DUMPREG(HDMI_V_BLANK_F2_1);
1018 DUMPREG(HDMI_V_BLANK_F3_0);
1019 DUMPREG(HDMI_V_BLANK_F3_1);
1020 DUMPREG(HDMI_V_BLANK_F4_0);
1021 DUMPREG(HDMI_V_BLANK_F4_1);
1022 DUMPREG(HDMI_V_BLANK_F5_0);
1023 DUMPREG(HDMI_V_BLANK_F5_1);
1024
1025 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
1026 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
1027 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
1028 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
1029 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
1030 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
1031 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
1032 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
1033
1034 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
1035 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
1036 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
1037 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
1038 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
1039 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
1040 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
1041 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
1042
1043 DUMPREG(HDMI_VACT_SPACE_1_0);
1044 DUMPREG(HDMI_VACT_SPACE_1_1);
1045 DUMPREG(HDMI_VACT_SPACE_2_0);
1046 DUMPREG(HDMI_VACT_SPACE_2_1);
1047 DUMPREG(HDMI_VACT_SPACE_3_0);
1048 DUMPREG(HDMI_VACT_SPACE_3_1);
1049 DUMPREG(HDMI_VACT_SPACE_4_0);
1050 DUMPREG(HDMI_VACT_SPACE_4_1);
1051 DUMPREG(HDMI_VACT_SPACE_5_0);
1052 DUMPREG(HDMI_VACT_SPACE_5_1);
1053 DUMPREG(HDMI_VACT_SPACE_6_0);
1054 DUMPREG(HDMI_VACT_SPACE_6_1);
380 1055
381 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix); 1056 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
382 DUMPREG(HDMI_TG_CMD); 1057 DUMPREG(HDMI_TG_CMD);
@@ -400,6 +1075,10 @@ static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
400 DUMPREG(HDMI_TG_FIELD_CHG_H); 1075 DUMPREG(HDMI_TG_FIELD_CHG_H);
401 DUMPREG(HDMI_TG_VACT_ST2_L); 1076 DUMPREG(HDMI_TG_VACT_ST2_L);
402 DUMPREG(HDMI_TG_VACT_ST2_H); 1077 DUMPREG(HDMI_TG_VACT_ST2_H);
1078 DUMPREG(HDMI_TG_VACT_ST3_L);
1079 DUMPREG(HDMI_TG_VACT_ST3_H);
1080 DUMPREG(HDMI_TG_VACT_ST4_L);
1081 DUMPREG(HDMI_TG_VACT_ST4_H);
403 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L); 1082 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
404 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H); 1083 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
405 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L); 1084 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
@@ -408,10 +1087,49 @@ static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
408 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H); 1087 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
409 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L); 1088 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
410 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H); 1089 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
1090 DUMPREG(HDMI_TG_3D);
1091
1092 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
1093 DUMPREG(HDMI_AVI_CON);
1094 DUMPREG(HDMI_AVI_HEADER0);
1095 DUMPREG(HDMI_AVI_HEADER1);
1096 DUMPREG(HDMI_AVI_HEADER2);
1097 DUMPREG(HDMI_AVI_CHECK_SUM);
1098 DUMPREG(HDMI_VSI_CON);
1099 DUMPREG(HDMI_VSI_HEADER0);
1100 DUMPREG(HDMI_VSI_HEADER1);
1101 DUMPREG(HDMI_VSI_HEADER2);
1102 for (i = 0; i < 7; ++i)
1103 DUMPREG(HDMI_VSI_DATA(i));
1104
411#undef DUMPREG 1105#undef DUMPREG
412} 1106}
413 1107
414static int hdmi_conf_index(struct drm_display_mode *mode) 1108static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
1109{
1110 if (hdata->is_v13)
1111 hdmi_v13_regs_dump(hdata, prefix);
1112 else
1113 hdmi_v14_regs_dump(hdata, prefix);
1114}
1115
1116static int hdmi_v13_conf_index(struct drm_display_mode *mode)
1117{
1118 int i;
1119
1120 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
1121 if (hdmi_v13_confs[i].width == mode->hdisplay &&
1122 hdmi_v13_confs[i].height == mode->vdisplay &&
1123 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
1124 hdmi_v13_confs[i].interlace ==
1125 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
1126 true : false))
1127 return i;
1128
1129 return -1;
1130}
1131
1132static int hdmi_v14_conf_index(struct drm_display_mode *mode)
415{ 1133{
416 int i; 1134 int i;
417 1135
@@ -427,6 +1145,15 @@ static int hdmi_conf_index(struct drm_display_mode *mode)
427 return -1; 1145 return -1;
428} 1146}
429 1147
1148static int hdmi_conf_index(struct hdmi_context *hdata,
1149 struct drm_display_mode *mode)
1150{
1151 if (hdata->is_v13)
1152 return hdmi_v13_conf_index(mode);
1153 else
1154 return hdmi_v14_conf_index(mode);
1155}
1156
430static bool hdmi_is_connected(void *ctx) 1157static bool hdmi_is_connected(void *ctx)
431{ 1158{
432 struct hdmi_context *hdata = (struct hdmi_context *)ctx; 1159 struct hdmi_context *hdata = (struct hdmi_context *)ctx;
@@ -462,16 +1189,25 @@ static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
462 return 0; 1189 return 0;
463} 1190}
464 1191
465static int hdmi_check_timing(void *ctx, void *timing) 1192static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
466{ 1193{
467 struct fb_videomode *check_timing = timing;
468 int i; 1194 int i;
469 1195
470 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1196 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
1197 if (hdmi_v13_confs[i].width == check_timing->xres &&
1198 hdmi_v13_confs[i].height == check_timing->yres &&
1199 hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
1200 hdmi_v13_confs[i].interlace ==
1201 ((check_timing->vmode & FB_VMODE_INTERLACED) ?
1202 true : false))
1203 return 0;
471 1204
472 DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres, 1205 return -EINVAL;
473 check_timing->yres, check_timing->refresh, 1206}
474 check_timing->vmode); 1207
1208static int hdmi_v14_check_timing(struct fb_videomode *check_timing)
1209{
1210 int i;
475 1211
476 for (i = 0; i < ARRAY_SIZE(hdmi_confs); ++i) 1212 for (i = 0; i < ARRAY_SIZE(hdmi_confs); ++i)
477 if (hdmi_confs[i].width == check_timing->xres && 1213 if (hdmi_confs[i].width == check_timing->xres &&
@@ -485,6 +1221,23 @@ static int hdmi_check_timing(void *ctx, void *timing)
485 return -EINVAL; 1221 return -EINVAL;
486} 1222}
487 1223
1224static int hdmi_check_timing(void *ctx, void *timing)
1225{
1226 struct hdmi_context *hdata = (struct hdmi_context *)ctx;
1227 struct fb_videomode *check_timing = timing;
1228
1229 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1230
1231 DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1232 check_timing->yres, check_timing->refresh,
1233 check_timing->vmode);
1234
1235 if (hdata->is_v13)
1236 return hdmi_v13_check_timing(check_timing);
1237 else
1238 return hdmi_v14_check_timing(check_timing);
1239}
1240
488static int hdmi_display_power_on(void *ctx, int mode) 1241static int hdmi_display_power_on(void *ctx, int mode)
489{ 1242{
490 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1243 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
@@ -516,13 +1269,20 @@ static struct exynos_hdmi_display_ops display_ops = {
516 1269
517static void hdmi_conf_reset(struct hdmi_context *hdata) 1270static void hdmi_conf_reset(struct hdmi_context *hdata)
518{ 1271{
1272 u32 reg;
1273
519 /* disable hpd handle for drm */ 1274 /* disable hpd handle for drm */
520 hdata->hpd_handle = false; 1275 hdata->hpd_handle = false;
521 1276
1277 if (hdata->is_v13)
1278 reg = HDMI_V13_CORE_RSTOUT;
1279 else
1280 reg = HDMI_CORE_RSTOUT;
1281
522 /* resetting HDMI core */ 1282 /* resetting HDMI core */
523 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, HDMI_CORE_SW_RSTOUT); 1283 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
524 mdelay(10); 1284 mdelay(10);
525 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT); 1285 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
526 mdelay(10); 1286 mdelay(10);
527 1287
528 /* enable hpd handle for drm */ 1288 /* enable hpd handle for drm */
@@ -546,27 +1306,126 @@ static void hdmi_conf_init(struct hdmi_context *hdata)
546 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1306 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
547 /* disable bluescreen */ 1307 /* disable bluescreen */
548 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1308 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
549 /* choose bluescreen (fecal) color */ 1309
550 hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_0, 0x12); 1310 if (hdata->is_v13) {
551 hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_1, 0x34); 1311 /* choose bluescreen (fecal) color */
552 hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_2, 0x56); 1312 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
553 /* enable AVI packet every vsync, fixes purple line problem */ 1313 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
554 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 0x02); 1314 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
555 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1315
556 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(0), 0 << 5); 1316 /* enable AVI packet every vsync, fixes purple line problem */
557 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1317 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
558 1318 /* force RGB, look to CEA-861-D, table 7 for more detail */
559 hdmi_reg_writeb(hdata, HDMI_SPD_CON, 0x02); 1319 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
560 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02); 1320 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
561 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 0x04); 1321
1322 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1323 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1324 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1325 } else {
1326 /* enable AVI packet every vsync, fixes purple line problem */
1327 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 0x02);
1328 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 2 << 5);
1329 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1330 }
562 1331
563 /* enable hpd handle for drm */ 1332 /* enable hpd handle for drm */
564 hdata->hpd_handle = true; 1333 hdata->hpd_handle = true;
565} 1334}
566 1335
567static void hdmi_timing_apply(struct hdmi_context *hdata, 1336static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
568 const struct hdmi_preset_conf *conf)
569{ 1337{
1338 const struct hdmi_v13_preset_conf *conf =
1339 hdmi_v13_confs[hdata->cur_conf].conf;
1340 const struct hdmi_v13_core_regs *core = &conf->core;
1341 const struct hdmi_v13_tg_regs *tg = &conf->tg;
1342 int tries;
1343
1344 /* setting core registers */
1345 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1346 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1347 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1348 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1349 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1350 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1351 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1352 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1353 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1354 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1355 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1356 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1357 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1358 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1359 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1360 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1361 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1362 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1363 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1364 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1365 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1366 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1367 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1368 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1369 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1370 /* Timing generator registers */
1371 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1372 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1373 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1374 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1375 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1376 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1377 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1378 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1379 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1380 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1381 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1382 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1383 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1384 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1385 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1386 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1387 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1388 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1389 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1390 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1391 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1392 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1393 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1394 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1395 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1396 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1397 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1398 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1399
1400 /* waiting for HDMIPHY's PLL to get to steady state */
1401 for (tries = 100; tries; --tries) {
1402 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1403 if (val & HDMI_PHY_STATUS_READY)
1404 break;
1405 mdelay(1);
1406 }
1407 /* steady state not achieved */
1408 if (tries == 0) {
1409 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1410 hdmi_regs_dump(hdata, "timing apply");
1411 }
1412
1413 clk_disable(hdata->res.sclk_hdmi);
1414 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1415 clk_enable(hdata->res.sclk_hdmi);
1416
1417 /* enable HDMI and timing generator */
1418 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1419 if (core->int_pro_mode[0])
1420 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1421 HDMI_FIELD_EN);
1422 else
1423 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1424}
1425
1426static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1427{
1428 const struct hdmi_preset_conf *conf = hdmi_confs[hdata->cur_conf].conf;
570 const struct hdmi_core_regs *core = &conf->core; 1429 const struct hdmi_core_regs *core = &conf->core;
571 const struct hdmi_tg_regs *tg = &conf->tg; 1430 const struct hdmi_tg_regs *tg = &conf->tg;
572 int tries; 1431 int tries;
@@ -574,29 +1433,102 @@ static void hdmi_timing_apply(struct hdmi_context *hdata,
574 /* setting core registers */ 1433 /* setting core registers */
575 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]); 1434 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
576 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]); 1435 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
577 hdmi_reg_writeb(hdata, HDMI_V_BLANK_0, core->v_blank[0]); 1436 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
578 hdmi_reg_writeb(hdata, HDMI_V_BLANK_1, core->v_blank[1]); 1437 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
579 hdmi_reg_writeb(hdata, HDMI_V_BLANK_2, core->v_blank[2]); 1438 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
580 hdmi_reg_writeb(hdata, HDMI_H_V_LINE_0, core->h_v_line[0]); 1439 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
581 hdmi_reg_writeb(hdata, HDMI_H_V_LINE_1, core->h_v_line[1]); 1440 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
582 hdmi_reg_writeb(hdata, HDMI_H_V_LINE_2, core->h_v_line[2]); 1441 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1442 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1443 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1444 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
583 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]); 1445 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
584 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]); 1446 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
585 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F_0, core->v_blank_f[0]); 1447 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
586 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F_1, core->v_blank_f[1]); 1448 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
587 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F_2, core->v_blank_f[2]); 1449 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
588 hdmi_reg_writeb(hdata, HDMI_H_SYNC_GEN_0, core->h_sync_gen[0]); 1450 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
589 hdmi_reg_writeb(hdata, HDMI_H_SYNC_GEN_1, core->h_sync_gen[1]); 1451 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
590 hdmi_reg_writeb(hdata, HDMI_H_SYNC_GEN_2, core->h_sync_gen[2]); 1452 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
591 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_1_0, core->v_sync_gen1[0]); 1453 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
592 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_1_1, core->v_sync_gen1[1]); 1454 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
593 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_1_2, core->v_sync_gen1[2]); 1455 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
594 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_2_0, core->v_sync_gen2[0]); 1456 core->v_sync_line_bef_2[0]);
595 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_2_1, core->v_sync_gen2[1]); 1457 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
596 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_2_2, core->v_sync_gen2[2]); 1458 core->v_sync_line_bef_2[1]);
597 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_3_0, core->v_sync_gen3[0]); 1459 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
598 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_3_1, core->v_sync_gen3[1]); 1460 core->v_sync_line_bef_1[0]);
599 hdmi_reg_writeb(hdata, HDMI_V_SYNC_GEN_3_2, core->v_sync_gen3[2]); 1461 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1462 core->v_sync_line_bef_1[1]);
1463 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1464 core->v_sync_line_aft_2[0]);
1465 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1466 core->v_sync_line_aft_2[1]);
1467 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1468 core->v_sync_line_aft_1[0]);
1469 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1470 core->v_sync_line_aft_1[1]);
1471 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1472 core->v_sync_line_aft_pxl_2[0]);
1473 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1474 core->v_sync_line_aft_pxl_2[1]);
1475 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1476 core->v_sync_line_aft_pxl_1[0]);
1477 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1478 core->v_sync_line_aft_pxl_1[1]);
1479 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1480 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1481 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1482 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1483 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1484 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1485 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1486 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1487 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1488 core->v_sync_line_aft_3[0]);
1489 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1490 core->v_sync_line_aft_3[1]);
1491 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1492 core->v_sync_line_aft_4[0]);
1493 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1494 core->v_sync_line_aft_4[1]);
1495 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1496 core->v_sync_line_aft_5[0]);
1497 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1498 core->v_sync_line_aft_5[1]);
1499 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1500 core->v_sync_line_aft_6[0]);
1501 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1502 core->v_sync_line_aft_6[1]);
1503 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1504 core->v_sync_line_aft_pxl_3[0]);
1505 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1506 core->v_sync_line_aft_pxl_3[1]);
1507 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1508 core->v_sync_line_aft_pxl_4[0]);
1509 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1510 core->v_sync_line_aft_pxl_4[1]);
1511 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1512 core->v_sync_line_aft_pxl_5[0]);
1513 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1514 core->v_sync_line_aft_pxl_5[1]);
1515 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1516 core->v_sync_line_aft_pxl_6[0]);
1517 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1518 core->v_sync_line_aft_pxl_6[1]);
1519 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1520 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1521 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1522 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1523 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1524 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1525 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1526 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1527 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1528 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1529 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1530 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1531
600 /* Timing generator registers */ 1532 /* Timing generator registers */
601 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l); 1533 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
602 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h); 1534 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
@@ -618,6 +1550,10 @@ static void hdmi_timing_apply(struct hdmi_context *hdata,
618 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h); 1550 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
619 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l); 1551 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
620 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h); 1552 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1553 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3_l);
1554 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3_h);
1555 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4_l);
1556 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4_h);
621 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l); 1557 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
622 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h); 1558 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
623 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l); 1559 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
@@ -626,10 +1562,11 @@ static void hdmi_timing_apply(struct hdmi_context *hdata,
626 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h); 1562 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
627 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l); 1563 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
628 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h); 1564 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1565 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d);
629 1566
630 /* waiting for HDMIPHY's PLL to get to steady state */ 1567 /* waiting for HDMIPHY's PLL to get to steady state */
631 for (tries = 100; tries; --tries) { 1568 for (tries = 100; tries; --tries) {
632 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); 1569 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
633 if (val & HDMI_PHY_STATUS_READY) 1570 if (val & HDMI_PHY_STATUS_READY)
634 break; 1571 break;
635 mdelay(1); 1572 mdelay(1);
@@ -653,9 +1590,18 @@ static void hdmi_timing_apply(struct hdmi_context *hdata,
653 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN); 1590 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
654} 1591}
655 1592
1593static void hdmi_timing_apply(struct hdmi_context *hdata)
1594{
1595 if (hdata->is_v13)
1596 hdmi_v13_timing_apply(hdata);
1597 else
1598 hdmi_v14_timing_apply(hdata);
1599}
1600
656static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1601static void hdmiphy_conf_reset(struct hdmi_context *hdata)
657{ 1602{
658 u8 buffer[2]; 1603 u8 buffer[2];
1604 u32 reg;
659 1605
660 clk_disable(hdata->res.sclk_hdmi); 1606 clk_disable(hdata->res.sclk_hdmi);
661 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel); 1607 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
@@ -668,15 +1614,21 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
668 if (hdata->hdmiphy_port) 1614 if (hdata->hdmiphy_port)
669 i2c_master_send(hdata->hdmiphy_port, buffer, 2); 1615 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
670 1616
1617 if (hdata->is_v13)
1618 reg = HDMI_V13_PHY_RSTOUT;
1619 else
1620 reg = HDMI_PHY_RSTOUT;
1621
671 /* reset hdmiphy */ 1622 /* reset hdmiphy */
672 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1623 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
673 mdelay(10); 1624 mdelay(10);
674 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1625 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
675 mdelay(10); 1626 mdelay(10);
676} 1627}
677 1628
678static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1629static void hdmiphy_conf_apply(struct hdmi_context *hdata)
679{ 1630{
1631 const u8 *hdmiphy_data;
680 u8 buffer[32]; 1632 u8 buffer[32];
681 u8 operation[2]; 1633 u8 operation[2];
682 u8 read_buffer[32] = {0, }; 1634 u8 read_buffer[32] = {0, };
@@ -689,7 +1641,12 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
689 } 1641 }
690 1642
691 /* pixel clock */ 1643 /* pixel clock */
692 memcpy(buffer, hdmi_confs[hdata->cur_conf].hdmiphy_data, 32); 1644 if (hdata->is_v13)
1645 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1646 else
1647 hdmiphy_data = hdmi_confs[hdata->cur_conf].hdmiphy_data;
1648
1649 memcpy(buffer, hdmiphy_data, 32);
693 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); 1650 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
694 if (ret != 32) { 1651 if (ret != 32) {
695 DRM_ERROR("failed to configure HDMIPHY via I2C\n"); 1652 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
@@ -721,9 +1678,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
721 1678
722static void hdmi_conf_apply(struct hdmi_context *hdata) 1679static void hdmi_conf_apply(struct hdmi_context *hdata)
723{ 1680{
724 const struct hdmi_preset_conf *conf =
725 hdmi_confs[hdata->cur_conf].conf;
726
727 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1681 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
728 1682
729 hdmiphy_conf_reset(hdata); 1683 hdmiphy_conf_reset(hdata);
@@ -733,7 +1687,7 @@ static void hdmi_conf_apply(struct hdmi_context *hdata)
733 hdmi_conf_init(hdata); 1687 hdmi_conf_init(hdata);
734 1688
735 /* setting core registers */ 1689 /* setting core registers */
736 hdmi_timing_apply(hdata, conf); 1690 hdmi_timing_apply(hdata);
737 1691
738 hdmi_regs_dump(hdata, "start"); 1692 hdmi_regs_dump(hdata, "start");
739} 1693}
@@ -745,8 +1699,8 @@ static void hdmi_mode_set(void *ctx, void *mode)
745 1699
746 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1700 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
747 1701
748 conf_idx = hdmi_conf_index(mode); 1702 conf_idx = hdmi_conf_index(hdata, mode);
749 if (conf_idx >= 0 && conf_idx < ARRAY_SIZE(hdmi_confs)) 1703 if (conf_idx >= 0)
750 hdata->cur_conf = conf_idx; 1704 hdata->cur_conf = conf_idx;
751 else 1705 else
752 DRM_DEBUG_KMS("not supported mode\n"); 1706 DRM_DEBUG_KMS("not supported mode\n");
@@ -926,7 +1880,6 @@ static void hdmi_resource_poweron(struct hdmi_context *hdata)
926 hdmiphy_conf_reset(hdata); 1880 hdmiphy_conf_reset(hdata);
927 hdmi_conf_reset(hdata); 1881 hdmi_conf_reset(hdata);
928 hdmi_conf_init(hdata); 1882 hdmi_conf_init(hdata);
929
930} 1883}
931 1884
932static void hdmi_resource_poweroff(struct hdmi_context *hdata) 1885static void hdmi_resource_poweroff(struct hdmi_context *hdata)
@@ -1022,6 +1975,7 @@ static int __devinit hdmi_probe(struct platform_device *pdev)
1022 1975
1023 platform_set_drvdata(pdev, drm_hdmi_ctx); 1976 platform_set_drvdata(pdev, drm_hdmi_ctx);
1024 1977
1978 hdata->is_v13 = pdata->is_v13;
1025 hdata->default_win = pdata->default_win; 1979 hdata->default_win = pdata->default_win;
1026 hdata->default_timing = &pdata->timing; 1980 hdata->default_timing = &pdata->timing;
1027 hdata->default_bpp = pdata->bpp; 1981 hdata->default_bpp = pdata->bpp;
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.h b/drivers/gpu/drm/exynos/exynos_hdmi.h
index 31d6cf84c1aa..040ecadb912e 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.h
@@ -28,15 +28,6 @@
28#ifndef _EXYNOS_HDMI_H_ 28#ifndef _EXYNOS_HDMI_H_
29#define _EXYNOS_HDMI_H_ 29#define _EXYNOS_HDMI_H_
30 30
31struct hdmi_conf {
32 int width;
33 int height;
34 int vrefresh;
35 bool interlace;
36 const u8 *hdmiphy_data;
37 const struct hdmi_preset_conf *conf;
38};
39
40struct hdmi_resources { 31struct hdmi_resources {
41 struct clk *hdmi; 32 struct clk *hdmi;
42 struct clk *sclk_hdmi; 33 struct clk *sclk_hdmi;
@@ -51,6 +42,7 @@ struct hdmi_context {
51 struct device *dev; 42 struct device *dev;
52 struct drm_device *drm_dev; 43 struct drm_device *drm_dev;
53 struct fb_videomode *default_timing; 44 struct fb_videomode *default_timing;
45 unsigned int is_v13:1;
54 unsigned int default_win; 46 unsigned int default_win;
55 unsigned int default_bpp; 47 unsigned int default_bpp;
56 bool hpd_handle; 48 bool hpd_handle;
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h
index 72e6b52be740..6b287158f76e 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -19,6 +19,7 @@
19 * Register part 19 * Register part
20*/ 20*/
21 21
22/* HDMI Version 1.3 & Common */
22#define HDMI_CTRL_BASE(x) ((x) + 0x00000000) 23#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
23#define HDMI_CORE_BASE(x) ((x) + 0x00010000) 24#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
24#define HDMI_TG_BASE(x) ((x) + 0x00050000) 25#define HDMI_TG_BASE(x) ((x) + 0x00050000)
@@ -27,56 +28,57 @@
27#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) 28#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
28#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) 29#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
29#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) 30#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
30#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) 31#define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
31#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018) 32#define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)
32#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C) 33#define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)
33#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) 34#define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
34 35
35/* Core registers */ 36/* Core registers */
36#define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 37#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
37#define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 38#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
38#define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 39#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
39#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 40#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
40#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014) 41#define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014)
41#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 42#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
42#define HDMI_HPD HDMI_CORE_BASE(0x0030) 43#define HDMI_HPD HDMI_CORE_BASE(0x0030)
43#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 44#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
44#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 45#define HDMI_ENC_EN HDMI_CORE_BASE(0x0044)
45#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 46#define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
46#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 47#define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
48#define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
47#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 49#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
48#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 50#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
49#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 51#define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
50#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 52#define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
51#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 53#define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
52#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 54#define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
53#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 55#define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
54#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 56#define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
55#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 57#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
56#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 58#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
57#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 59#define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
58#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 60#define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
59#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 61#define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
60#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 62#define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
61#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 63#define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
62#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 64#define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
63#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 65#define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
64#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 66#define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
65#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 67#define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
66#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 68#define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
67#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 69#define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
68#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 70#define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
69#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 71#define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
70#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 72#define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
71#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 73#define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
72#define HDMI_ACR_CON HDMI_CORE_BASE(0x0180) 74#define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180)
73#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300) 75#define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300)
74#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 76#define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
75#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0) 77#define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0)
76#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 78#define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
77#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8) 79#define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8)
78#define HDMI_AUI_CON HDMI_CORE_BASE(0x0360) 80#define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360)
79#define HDMI_SPD_CON HDMI_CORE_BASE(0x0400) 81#define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400)
80 82
81/* Timing generator registers */ 83/* Timing generator registers */
82#define HDMI_TG_CMD HDMI_TG_BASE(0x0000) 84#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
@@ -144,4 +146,234 @@
144#define HDMI_TG_EN (1 << 0) 146#define HDMI_TG_EN (1 << 0)
145#define HDMI_FIELD_EN (1 << 1) 147#define HDMI_FIELD_EN (1 << 1)
146 148
149
150/* HDMI Version 1.4 */
151/* Control registers */
152/* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */
153/* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */
154#define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008)
155/* #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) */
156#define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010)
157#define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014)
158#define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020)
159#define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024)
160#define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028)
161#define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030)
162#define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040)
163#define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044)
164#define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050)
165#define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070)
166#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0074)
167#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078)
168#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C)
169#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)
170
171/* Video related registers */
172#define HDMI_YMAX HDMI_CORE_BASE(0x0060)
173#define HDMI_YMIN HDMI_CORE_BASE(0x0064)
174#define HDMI_CMAX HDMI_CORE_BASE(0x0068)
175#define HDMI_CMIN HDMI_CORE_BASE(0x006C)
176
177#define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0)
178#define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4)
179#define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8)
180#define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC)
181
182#define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0)
183#define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4)
184#define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8)
185#define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC)
186
187#define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0)
188
189#define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110)
190#define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114)
191#define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118)
192#define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C)
193
194#define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120)
195#define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124)
196#define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128)
197#define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C)
198
199#define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130)
200#define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134)
201#define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138)
202#define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C)
203
204#define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140)
205#define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144)
206#define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148)
207#define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C)
208
209#define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150)
210#define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154)
211#define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158)
212#define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C)
213
214#define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160)
215#define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164)
216#define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168)
217#define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C)
218#define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170)
219#define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174)
220#define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178)
221#define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C)
222
223#define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180)
224#define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184)
225#define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188)
226#define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C)
227#define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190)
228#define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194)
229#define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198)
230#define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C)
231
232#define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0)
233#define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4)
234#define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8)
235#define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC)
236#define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0)
237#define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4)
238#define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8)
239#define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC)
240
241#define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0)
242#define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4)
243#define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8)
244#define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC)
245#define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0)
246#define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4)
247#define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8)
248#define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC)
249#define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0)
250#define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4)
251#define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8)
252#define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC)
253
254#define HDMI_GCP_CON HDMI_CORE_BASE(0x0200)
255#define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210)
256#define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214)
257#define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218)
258
259/* Audio related registers */
260#define HDMI_ASP_CON HDMI_CORE_BASE(0x0300)
261#define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304)
262#define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310)
263#define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314)
264#define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318)
265#define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C)
266
267#define HDMI_ACR_CON HDMI_CORE_BASE(0x0400)
268#define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410)
269#define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414)
270#define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418)
271#define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430)
272#define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434)
273#define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438)
274
275/* Packet related registers */
276#define HDMI_ACP_CON HDMI_CORE_BASE(0x0500)
277#define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514)
278#define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n))
279
280#define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600)
281#define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614)
282#define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n))
283#define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n))
284
285#define HDMI_AVI_CON HDMI_CORE_BASE(0x0700)
286#define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710)
287#define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)
288#define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)
289#define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)
290#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n))
291
292#define HDMI_AUI_CON HDMI_CORE_BASE(0x0800)
293#define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)
294#define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)
295#define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)
296#define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)
297#define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n))
298
299#define HDMI_MPG_CON HDMI_CORE_BASE(0x0900)
300#define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)
301#define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n))
302
303#define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00)
304#define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10)
305#define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14)
306#define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18)
307#define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n))
308
309#define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00)
310#define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10)
311#define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14)
312#define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18)
313#define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n))
314
315#define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00)
316#define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10)
317#define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14)
318#define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18)
319#define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n))
320
321#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00)
322#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04)
323
324#define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48)
325#define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58)
326#define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C)
327#define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)
328#define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)
329
330/* HDCP related registers */
331#define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n))
332#define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n))
333
334#define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064)
335#define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070)
336#define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080)
337#define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084)
338#define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090)
339#define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n))
340#define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n))
341#define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n))
342
343#define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100)
344#define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110)
345#define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114)
346#define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140)
347#define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144)
348#define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180)
349#define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190)
350#define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0)
351#define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0)
352#define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0)
353#define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4)
354#define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0)
355
356#define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500)
357#define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504)
358#define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508)
359#define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C)
360#define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510)
361#define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514)
362#define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518)
363
364#define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520)
365#define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524)
366#define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528)
367#define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C)
368#define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530)
369#define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)
370
371/* Timing generator registers */
372/* TG configure/status registers */
373#define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068)
374#define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c)
375#define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070)
376#define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074)
377#define HDMI_TG_3D HDMI_TG_BASE(0x00F0)
378
147#endif /* SAMSUNG_REGS_HDMI_H */ 379#endif /* SAMSUNG_REGS_HDMI_H */
diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h
index 1ed3aae893a5..aff2313c1274 100644
--- a/include/drm/exynos_drm.h
+++ b/include/drm/exynos_drm.h
@@ -147,11 +147,13 @@ struct exynos_drm_common_hdmi_pd {
147 * @timing: default video mode for initializing 147 * @timing: default video mode for initializing
148 * @default_win: default window layer number to be used for UI. 148 * @default_win: default window layer number to be used for UI.
149 * @bpp: default bit per pixel. 149 * @bpp: default bit per pixel.
150 * @is_v13: set if hdmi version 13 is.
150 */ 151 */
151struct exynos_drm_hdmi_pdata { 152struct exynos_drm_hdmi_pdata {
152 struct fb_videomode timing; 153 struct fb_videomode timing;
153 unsigned int default_win; 154 unsigned int default_win;
154 unsigned int bpp; 155 unsigned int bpp;
156 unsigned int is_v13:1;
155}; 157};
156 158
157#endif /* __KERNEL__ */ 159#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 22:57:47 -0400