diff options
author | Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2011-04-11 07:09:40 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-04-12 16:59:37 -0400 |
commit | 3dfd7f606645279c788f48cfdfdf9565ec72c4f0 (patch) | |
tree | 939a11aeb3af4249babe73aff313dcff24cf073f | |
parent | 228bdfca9a09c1263c24509b4bc23a67be168e1a (diff) |
ath9k: Implement integer mode for AR9485
This fixes random disconnect.
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 15 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 45 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/phy.h | 1 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 31 |
4 files changed, 67 insertions, 25 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 93398de0bf67..1bc33f51e466 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -75,9 +75,18 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |||
75 | freq = centers.synth_center; | 75 | freq = centers.synth_center; |
76 | 76 | ||
77 | if (freq < 4800) { /* 2 GHz, fractional mode */ | 77 | if (freq < 4800) { /* 2 GHz, fractional mode */ |
78 | if (AR_SREV_9485(ah)) | 78 | if (AR_SREV_9485(ah)) { |
79 | channelSel = CHANSEL_2G_9485(freq); | 79 | u32 chan_frac; |
80 | else | 80 | |
81 | /* | ||
82 | * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0 | ||
83 | * ndiv = ((chan_mhz * 4) / 3) / freq_ref; | ||
84 | * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 | ||
85 | */ | ||
86 | channelSel = (freq * 4) / 120; | ||
87 | chan_frac = (((freq * 4) % 120) * 0x20000) / 120; | ||
88 | channelSel = (channelSel << 17) | chan_frac; | ||
89 | } else | ||
81 | channelSel = CHANSEL_2G(freq); | 90 | channelSel = CHANSEL_2G(freq); |
82 | /* Set to 2G mode */ | 91 | /* Set to 2G mode */ |
83 | bMode = 1; | 92 | bMode = 1; |
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 1b5bd13b0a6c..3a8c41c782e9 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -676,42 +676,55 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) | |||
676 | } | 676 | } |
677 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); | 677 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); |
678 | 678 | ||
679 | #define DPLL2_KD_VAL 0x3D | 679 | #define DPLL3_PHASE_SHIFT_VAL 0x1 |
680 | #define DPLL2_KI_VAL 0x06 | ||
681 | #define DPLL3_PHASE_SHIFT_VAL 0x1 | ||
682 | |||
683 | static void ath9k_hw_init_pll(struct ath_hw *ah, | 680 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
684 | struct ath9k_channel *chan) | 681 | struct ath9k_channel *chan) |
685 | { | 682 | { |
686 | u32 pll; | 683 | u32 pll; |
687 | 684 | ||
688 | if (AR_SREV_9485(ah)) { | 685 | if (AR_SREV_9485(ah)) { |
689 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); | ||
690 | REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01); | ||
691 | |||
692 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, | ||
693 | AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); | ||
694 | 686 | ||
695 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); | 687 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
696 | udelay(1000); | 688 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
689 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); | ||
690 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | ||
691 | AR_CH0_DPLL2_KD, 0x40); | ||
692 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | ||
693 | AR_CH0_DPLL2_KI, 0x4); | ||
697 | 694 | ||
698 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); | 695 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
696 | AR_CH0_BB_DPLL1_REFDIV, 0x5); | ||
697 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | ||
698 | AR_CH0_BB_DPLL1_NINI, 0x58); | ||
699 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | ||
700 | AR_CH0_BB_DPLL1_NFRAC, 0x0); | ||
699 | 701 | ||
700 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | 702 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
701 | AR_CH0_DPLL2_KD, DPLL2_KD_VAL); | 703 | AR_CH0_BB_DPLL2_OUTDIV, 0x1); |
704 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | ||
705 | AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); | ||
702 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | 706 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
703 | AR_CH0_DPLL2_KI, DPLL2_KI_VAL); | 707 | AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); |
704 | 708 | ||
709 | /* program BB PLL phase_shift to 0x6 */ | ||
705 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, | 710 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, |
706 | AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); | 711 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); |
707 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c); | 712 | |
713 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | ||
714 | AR_CH0_BB_DPLL2_PLL_PWD, 0x0); | ||
708 | udelay(1000); | 715 | udelay(1000); |
716 | |||
717 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, | ||
718 | AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); | ||
709 | } | 719 | } |
710 | 720 | ||
711 | pll = ath9k_hw_compute_pll_control(ah, chan); | 721 | pll = ath9k_hw_compute_pll_control(ah, chan); |
712 | 722 | ||
713 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); | 723 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
714 | 724 | ||
725 | if (AR_SREV_9485(ah)) | ||
726 | udelay(1000); | ||
727 | |||
715 | /* Switch the core clock for ar9271 to 117Mhz */ | 728 | /* Switch the core clock for ar9271 to 117Mhz */ |
716 | if (AR_SREV_9271(ah)) { | 729 | if (AR_SREV_9271(ah)) { |
717 | udelay(500); | 730 | udelay(500); |
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h index f50e2c29f71e..8e5fe9d7f174 100644 --- a/drivers/net/wireless/ath/ath9k/phy.h +++ b/drivers/net/wireless/ath/ath9k/phy.h | |||
@@ -19,7 +19,6 @@ | |||
19 | 19 | ||
20 | #define CHANSEL_DIV 15 | 20 | #define CHANSEL_DIV 15 |
21 | #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) | 21 | #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) |
22 | #define CHANSEL_2G_9485(_freq) ((((_freq) * 0x10000) - 215) / CHANSEL_DIV) | ||
23 | #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) | 22 | #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) |
24 | 23 | ||
25 | #define AR_PHY_BASE 0x9800 | 24 | #define AR_PHY_BASE 0x9800 |
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 2fbbe8842bb9..6acbf0e2240b 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
@@ -1086,14 +1086,35 @@ enum { | |||
1086 | #define AR_ENT_OTP 0x40d8 | 1086 | #define AR_ENT_OTP 0x40d8 |
1087 | #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 | 1087 | #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 |
1088 | #define AR_ENT_OTP_MPSD 0x00800000 | 1088 | #define AR_ENT_OTP_MPSD 0x00800000 |
1089 | #define AR_CH0_BB_DPLL2 0x16184 | 1089 | |
1090 | #define AR_CH0_BB_DPLL1 0x16180 | ||
1091 | #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000 | ||
1092 | #define AR_CH0_BB_DPLL1_REFDIV_S 27 | ||
1093 | #define AR_CH0_BB_DPLL1_NINI 0x07FC0000 | ||
1094 | #define AR_CH0_BB_DPLL1_NINI_S 18 | ||
1095 | #define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF | ||
1096 | #define AR_CH0_BB_DPLL1_NFRAC_S 0 | ||
1097 | |||
1098 | #define AR_CH0_BB_DPLL2 0x16184 | ||
1099 | #define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000 | ||
1100 | #define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30 | ||
1101 | #define AR_CH0_DPLL2_KI 0x3C000000 | ||
1102 | #define AR_CH0_DPLL2_KI_S 26 | ||
1103 | #define AR_CH0_DPLL2_KD 0x03F80000 | ||
1104 | #define AR_CH0_DPLL2_KD_S 19 | ||
1105 | #define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000 | ||
1106 | #define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18 | ||
1107 | #define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000 | ||
1108 | #define AR_CH0_BB_DPLL2_PLL_PWD_S 16 | ||
1109 | #define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000 | ||
1110 | #define AR_CH0_BB_DPLL2_OUTDIV_S 13 | ||
1111 | |||
1090 | #define AR_CH0_BB_DPLL3 0x16188 | 1112 | #define AR_CH0_BB_DPLL3 0x16188 |
1113 | #define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000 | ||
1114 | #define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23 | ||
1115 | |||
1091 | #define AR_CH0_DDR_DPLL2 0x16244 | 1116 | #define AR_CH0_DDR_DPLL2 0x16244 |
1092 | #define AR_CH0_DDR_DPLL3 0x16248 | 1117 | #define AR_CH0_DDR_DPLL3 0x16248 |
1093 | #define AR_CH0_DPLL2_KD 0x03F80000 | ||
1094 | #define AR_CH0_DPLL2_KD_S 19 | ||
1095 | #define AR_CH0_DPLL2_KI 0x3C000000 | ||
1096 | #define AR_CH0_DPLL2_KI_S 26 | ||
1097 | #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000 | 1118 | #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000 |
1098 | #define AR_CH0_DPLL3_PHASE_SHIFT_S 23 | 1119 | #define AR_CH0_DPLL3_PHASE_SHIFT_S 23 |
1099 | #define AR_PHY_CCA_NOM_VAL_2GHZ -118 | 1120 | #define AR_PHY_CCA_NOM_VAL_2GHZ -118 |