aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authoreric miao <eric.miao@marvell.com>2007-11-30 05:26:56 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 10:07:51 -0500
commit3dcb00ea58f6b5dc62b89bbfd54353a06e6af921 (patch)
tree8fee306ba100c646ede0c8736f5b2a5194461915
parent0aea1fd565857f002e873a506d67c92ff913f1af (diff)
[ARM] pxa: use __raw_writel()/__raw_readl() for ssp_xxxx()
1. change SSP register definitions from absolute virtual addresses to offsets 2. use __raw_writel()/__raw_readl() for functions of ssp_xxxx() Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-pxa/ssp.c77
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h89
2 files changed, 63 insertions, 103 deletions
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 0225ee016f2d..b6d37fa7b85f 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -48,9 +48,11 @@
48static irqreturn_t ssp_interrupt(int irq, void *dev_id) 48static irqreturn_t ssp_interrupt(int irq, void *dev_id)
49{ 49{
50 struct ssp_dev *dev = (struct ssp_dev*) dev_id; 50 struct ssp_dev *dev = (struct ssp_dev*) dev_id;
51 unsigned int status = SSSR_P(dev->port); 51 struct ssp_device *ssp = dev->ssp;
52 unsigned int status;
52 53
53 SSSR_P(dev->port) = status; /* clear status bits */ 54 status = __raw_readl(ssp->mmio_base + SSSR);
55 __raw_writel(status, ssp->mmio_base + SSSR);
54 56
55 if (status & SSSR_ROR) 57 if (status & SSSR_ROR)
56 printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port); 58 printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
@@ -79,15 +81,16 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id)
79 */ 81 */
80int ssp_write_word(struct ssp_dev *dev, u32 data) 82int ssp_write_word(struct ssp_dev *dev, u32 data)
81{ 83{
84 struct ssp_device *ssp = dev->ssp;
82 int timeout = TIMEOUT; 85 int timeout = TIMEOUT;
83 86
84 while (!(SSSR_P(dev->port) & SSSR_TNF)) { 87 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
85 if (!--timeout) 88 if (!--timeout)
86 return -ETIMEDOUT; 89 return -ETIMEDOUT;
87 cpu_relax(); 90 cpu_relax();
88 } 91 }
89 92
90 SSDR_P(dev->port) = data; 93 __raw_writel(data, ssp->mmio_base + SSDR);
91 94
92 return 0; 95 return 0;
93} 96}
@@ -109,15 +112,16 @@ int ssp_write_word(struct ssp_dev *dev, u32 data)
109 */ 112 */
110int ssp_read_word(struct ssp_dev *dev, u32 *data) 113int ssp_read_word(struct ssp_dev *dev, u32 *data)
111{ 114{
115 struct ssp_device *ssp = dev->ssp;
112 int timeout = TIMEOUT; 116 int timeout = TIMEOUT;
113 117
114 while (!(SSSR_P(dev->port) & SSSR_RNE)) { 118 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
115 if (!--timeout) 119 if (!--timeout)
116 return -ETIMEDOUT; 120 return -ETIMEDOUT;
117 cpu_relax(); 121 cpu_relax();
118 } 122 }
119 123
120 *data = SSDR_P(dev->port); 124 *data = __raw_readl(ssp->mmio_base + SSDR);
121 return 0; 125 return 0;
122} 126}
123 127
@@ -131,17 +135,18 @@ int ssp_read_word(struct ssp_dev *dev, u32 *data)
131 */ 135 */
132int ssp_flush(struct ssp_dev *dev) 136int ssp_flush(struct ssp_dev *dev)
133{ 137{
138 struct ssp_device *ssp = dev->ssp;
134 int timeout = TIMEOUT * 2; 139 int timeout = TIMEOUT * 2;
135 140
136 do { 141 do {
137 while (SSSR_P(dev->port) & SSSR_RNE) { 142 while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
138 if (!--timeout) 143 if (!--timeout)
139 return -ETIMEDOUT; 144 return -ETIMEDOUT;
140 (void) SSDR_P(dev->port); 145 (void)__raw_readl(ssp->mmio_base + SSDR);
141 } 146 }
142 if (!--timeout) 147 if (!--timeout)
143 return -ETIMEDOUT; 148 return -ETIMEDOUT;
144 } while (SSSR_P(dev->port) & SSSR_BSY); 149 } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
145 150
146 return 0; 151 return 0;
147} 152}
@@ -153,7 +158,12 @@ int ssp_flush(struct ssp_dev *dev)
153 */ 158 */
154void ssp_enable(struct ssp_dev *dev) 159void ssp_enable(struct ssp_dev *dev)
155{ 160{
156 SSCR0_P(dev->port) |= SSCR0_SSE; 161 struct ssp_device *ssp = dev->ssp;
162 uint32_t sscr0;
163
164 sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
165 sscr0 |= SSCR0_SSE;
166 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
157} 167}
158 168
159/** 169/**
@@ -163,7 +173,12 @@ void ssp_enable(struct ssp_dev *dev)
163 */ 173 */
164void ssp_disable(struct ssp_dev *dev) 174void ssp_disable(struct ssp_dev *dev)
165{ 175{
166 SSCR0_P(dev->port) &= ~SSCR0_SSE; 176 struct ssp_device *ssp = dev->ssp;
177 uint32_t sscr0;
178
179 sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
180 sscr0 &= ~SSCR0_SSE;
181 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
167} 182}
168 183
169/** 184/**
@@ -172,14 +187,16 @@ void ssp_disable(struct ssp_dev *dev)
172 * 187 *
173 * Save the configured SSP state for suspend. 188 * Save the configured SSP state for suspend.
174 */ 189 */
175void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp) 190void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
176{ 191{
177 ssp->cr0 = SSCR0_P(dev->port); 192 struct ssp_device *ssp = dev->ssp;
178 ssp->cr1 = SSCR1_P(dev->port); 193
179 ssp->to = SSTO_P(dev->port); 194 state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
180 ssp->psp = SSPSP_P(dev->port); 195 state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
196 state->to = __raw_readl(ssp->mmio_base + SSTO);
197 state->psp = __raw_readl(ssp->mmio_base + SSPSP);
181 198
182 SSCR0_P(dev->port) &= ~SSCR0_SSE; 199 ssp_disable(dev);
183} 200}
184 201
185/** 202/**
@@ -188,16 +205,18 @@ void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
188 * 205 *
189 * Restore the SSP configuration saved previously by ssp_save_state. 206 * Restore the SSP configuration saved previously by ssp_save_state.
190 */ 207 */
191void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp) 208void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
192{ 209{
193 SSSR_P(dev->port) = SSSR_ROR | SSSR_TUR | SSSR_BCE; 210 struct ssp_device *ssp = dev->ssp;
211 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
194 212
195 SSCR0_P(dev->port) = ssp->cr0 & ~SSCR0_SSE; 213 __raw_writel(sssr, ssp->mmio_base + SSSR);
196 SSCR1_P(dev->port) = ssp->cr1;
197 SSTO_P(dev->port) = ssp->to;
198 SSPSP_P(dev->port) = ssp->psp;
199 214
200 SSCR0_P(dev->port) = ssp->cr0; 215 __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
216 __raw_writel(state->cr1, ssp->mmio_base + SSCR1);
217 __raw_writel(state->to, ssp->mmio_base + SSTO);
218 __raw_writel(state->psp, ssp->mmio_base + SSPSP);
219 __raw_writel(state->cr0, ssp->mmio_base + SSCR0);
201} 220}
202 221
203/** 222/**
@@ -211,15 +230,17 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
211 */ 230 */
212int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed) 231int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
213{ 232{
233 struct ssp_device *ssp = dev->ssp;
234
214 dev->mode = mode; 235 dev->mode = mode;
215 dev->flags = flags; 236 dev->flags = flags;
216 dev->psp_flags = psp_flags; 237 dev->psp_flags = psp_flags;
217 dev->speed = speed; 238 dev->speed = speed;
218 239
219 /* set up port type, speed, port settings */ 240 /* set up port type, speed, port settings */
220 SSCR0_P(dev->port) = (dev->speed | dev->mode); 241 __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
221 SSCR1_P(dev->port) = dev->flags; 242 __raw_writel(dev->flags, ssp->mmio_base + SSCR1);
222 SSPSP_P(dev->port) = dev->psp_flags; 243 __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
223 244
224 return 0; 245 return 0;
225} 246}
@@ -274,7 +295,7 @@ void ssp_exit(struct ssp_dev *dev)
274{ 295{
275 struct ssp_device *ssp = dev->ssp; 296 struct ssp_device *ssp = dev->ssp;
276 297
277 SSCR0_P(dev->port) &= ~SSCR0_SSE; 298 ssp_disable(dev);
278 free_irq(dev->irq, dev); 299 free_irq(dev->irq, dev);
279 clk_disable(ssp->clk); 300 clk_disable(ssp->clk);
280 ssp_free(ssp); 301 ssp_free(ssp);
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 687ade109113..991cb688db75 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -7,7 +7,20 @@
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits. 7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */ 8 */
9 9
10 /* Common PXA2xx bits first */ 10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23/* Common PXA2xx bits first */
11#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
12#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
13#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ 26#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
@@ -96,78 +109,4 @@
96#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 109#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
97#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 110#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
98 111
99#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
100#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
101#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
102#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
103#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
104
105/* Support existing PXA25x drivers */
106#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
107#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
108#define SSSR SSSR_P1 /* SSP Status Register */
109#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
110#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
111
112/* PXA27x ports */
113#if defined (CONFIG_PXA27x)
114#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
115#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
116#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
117#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
118#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
119#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
120#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
121#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
122#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
123#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
124#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
125#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
126#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
127#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
128#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
129#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
130#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
131#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
132#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
133#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
134#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
135#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
136#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
137#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
138#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
139#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
140#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
141#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
142#else /* PXA255 (only port 2) and PXA26x ports*/
143#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
144#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
145#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
146#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
147#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
148#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
149#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
150#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
151#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
152#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
153#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
154#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
155#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
156#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
157#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
158#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
159#endif
160
161#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
162#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
163#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
164#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
165#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
166#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
167#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
168#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
169#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
170#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
171#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
172
173#endif /* __ASM_ARCH_REGS_SSP_H */ 112#endif /* __ASM_ARCH_REGS_SSP_H */