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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 14:48:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 14:48:03 -0400
commit3dbde57ad941c55345fd7fac0ee3f70f204b02d8 (patch)
tree237c6de64d05da3f61b9ac1724e37a5c1f014b71
parenta6e6d863cf68bba886acfe47dbdc8f245cce588f (diff)
parent2207a4e1ca6a1bb126360b6d0c236af6664532f2 (diff)
Merge tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij: - A large slew of improvements of the Genric pin configuration support, and deployment in four different platforms: Rockchip, Super-H PFC, ABx500 and TZ1090. Support BIAS_BUS_HOLD, get device tree parsing and debugfs support into shape. - We also have device tree support with generic naming conventions for the generic pin configuration. - Delete the unused and confusing direct pinconf API. Now state transitions is *the* way to control pins and multiplexing. - New drivers for Rockchip, TZ1090, and TZ1090 PDC. - Two pin control states related to power management are now handled in the device core: "sleep" and "idle", removing a lot of boilerplate code in drivers. We do not yet know if this is the final word for pin PM, but it already make things a lot easier to handle. - Handle sparse GPIO ranges passing a list of disparate pins, and utilize these in the new BayTrail (x86 Atom SoC) driver. - Make the sunxi (AllWinner) driver handle external interrupts. - Make it possible for pinctrl-single to handle the case where several pins are managed by a single register, and augment it to handle sleep modes. - Cleanups and improvements for the abx500 drivers. - Move Sirf pin control drivers to their own directory, support save/restore of context and add support for the SiRFatlas6 SoC. - PMU muxing for the Dove pinctrl driver. - Finalization and support for VF610 in the i.MX6 pinctrl driver. - Smoothen out various Exynos rough edges. - Generic cleanups of various kinds. * tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe() pinctrl: remove bindings for pinconf options needing more thought pinctrl: remove slew-rate parameter from tz1090 pinctrl: set unit for debounce time pinconfig to usec pinctrl: more clarifications for generic pull configs pinctrl: rip out the direct pinconf API pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver pinctrl-tz1090: add TZ1090 pinctrl driver pinctrl: samsung: Staticize drvdata_list pinctrl: rockchip: Add missing irq_gc_unlock() call before return error pinctrl: abx500: rework error path pinctrl: abx500: suppress hardcoded value pinctrl: abx500: factorize code pinctrl: abx500: fix abx500_gpio_get() pinctrl: abx500: fix abx500_pin_config_set() pinctrl: abx500: Add device tree support sh-pfc: Guard DT parsing with #ifdef CONFIG_OF pinctrl: add Intel BayTrail GPIO/pinctrl support pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc pinctrl: Staticize local symbols ... Conflicts: drivers/net/ethernet/ti/davinci_mdio.c drivers/pinctrl/Makefile
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt41
-rw-r--r--Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt127
-rw-r--r--Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt227
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt49
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt48
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt153
-rw-r--r--Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt97
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ste,abx500.txt352
-rw-r--r--Documentation/pinctrl.txt39
-rw-r--r--MAINTAINERS10
-rw-r--r--drivers/base/pinctrl.c19
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c90
-rw-r--r--drivers/net/ethernet/ti/cpsw.c11
-rw-r--r--drivers/net/ethernet/ti/davinci_mdio.c10
-rw-r--r--drivers/pinctrl/Kconfig38
-rw-r--r--drivers/pinctrl/Makefile8
-rw-r--r--drivers/pinctrl/core.c171
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c244
-rw-r--r--drivers/pinctrl/pinconf-generic.c104
-rw-r--r--drivers/pinctrl/pinconf.c174
-rw-r--r--drivers/pinctrl/pinconf.h6
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c481
-rw-r--r--drivers/pinctrl/pinctrl-at91.c7
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c543
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c2
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c1
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c86
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c13
-rw-r--r--drivers/pinctrl/pinctrl-imx.c53
-rw-r--r--drivers/pinctrl/pinctrl-imx.h4
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c2
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c6
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c1394
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-single.c242
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h2023
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c1520
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.h68
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c1024
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c2072
-rw-r--r--drivers/pinctrl/pinctrl-u300.c1
-rw-r--r--drivers/pinctrl/pinctrl-vf610.c338
-rw-r--r--drivers/pinctrl/sh-pfc/core.c65
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c205
-rw-r--r--drivers/pinctrl/sirf/Makefile5
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c947
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c (renamed from drivers/pinctrl/pinctrl-sirf.c)949
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c929
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h116
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c9
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c8
-rw-r--r--drivers/spi/spi-pl022.c70
-rw-r--r--drivers/tty/serial/amba-pl011.c42
-rw-r--r--include/dt-bindings/pinctrl/rockchip.h32
-rw-r--r--include/linux/pinctrl/consumer.h77
-rw-r--r--include/linux/pinctrl/devinfo.h4
-rw-r--r--include/linux/pinctrl/pinconf-generic.h25
-rw-r--r--include/linux/pinctrl/pinconf.h2
-rw-r--r--include/linux/pinctrl/pinctrl.h4
60 files changed, 12447 insertions, 2945 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
new file mode 100644
index 000000000000..ddcdeb697c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
@@ -0,0 +1,41 @@
1Freescale Vybrid VF610 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,vf610-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
10 a pin working on a specific function, CONFIG is the pad setting value
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
12 datasheet for the valid pad config settings.
13
14CONFIG bits definition:
15PAD_CTL_SPEED_LOW (1 << 12)
16PAD_CTL_SPEED_MED (2 << 12)
17PAD_CTL_SPEED_HIGH (3 << 12)
18PAD_CTL_SRE_FAST (1 << 11)
19PAD_CTL_SRE_SLOW (0 << 11)
20PAD_CTL_ODE (1 << 10)
21PAD_CTL_HYS (1 << 9)
22PAD_CTL_DSE_DISABLE (0 << 6)
23PAD_CTL_DSE_150ohm (1 << 6)
24PAD_CTL_DSE_75ohm (2 << 6)
25PAD_CTL_DSE_50ohm (3 << 6)
26PAD_CTL_DSE_37ohm (4 << 6)
27PAD_CTL_DSE_30ohm (5 << 6)
28PAD_CTL_DSE_25ohm (6 << 6)
29PAD_CTL_DSE_20ohm (7 << 6)
30PAD_CTL_PUS_100K_DOWN (0 << 4)
31PAD_CTL_PUS_47K_UP (1 << 4)
32PAD_CTL_PUS_100K_UP (2 << 4)
33PAD_CTL_PUS_22K_UP (3 << 4)
34PAD_CTL_PKE (1 << 3)
35PAD_CTL_PUE (1 << 2)
36PAD_CTL_OBE_ENABLE (1 << 1)
37PAD_CTL_IBE_ENABLE (1 << 0)
38PAD_CTL_OBE_IBE_ENABLE (3 << 0)
39
40Please refer to vf610-pinfunc.h in device tree source folder
41for all available PIN_FUNC_ID for Vybrid VF610.
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
new file mode 100644
index 000000000000..a186181c402b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
@@ -0,0 +1,127 @@
1ImgTec TZ1090 PDC pin controller
2
3Required properties:
4- compatible: "img,tz1090-pdc-pinctrl"
5- reg: Should contain the register physical address and length of the
6 SOC_GPIO_CONTROL registers in the PDC register region.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
13of subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function. For this reason, even seemingly boolean
26values are actually tristates in this binding: unspecified, off, or on.
27Unspecified is represented as an absent property, and off/on are represented as
28integer values 0 and 1.
29
30Required subnode-properties:
31- tz1090,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- tz1090,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below, including
37 which pingroups can be muxed to them.
38- supported generic pinconfig properties (for further details see
39 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
40 - bias-disable
41 - bias-high-impedance
42 - bias-bus-hold
43 - bias-pull-up
44 - bias-pull-down
45 - input-schmitt-enable
46 - input-schmitt-disable
47 - drive-strength: Integer, control drive strength of pins in mA.
48 2: 2mA
49 4: 4mA
50 8: 8mA
51 12: 12mA
52 - low-power-enable: Flag, power-on-start weak pull-down for invalid power.
53 - low-power-disable: Flag, power-on-start weak pull-down disabled.
54
55Note that many of these properties are only valid for certain specific pins
56or groups. See the TZ1090 TRM for complete details regarding which groups
57support which functionality. The Linux pinctrl driver may also be a useful
58reference.
59
60Valid values for pin and group names are:
61
62 pins:
63
64 These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
65 bias-bus-hold (which can also be provided to any of the groups below to set
66 it for all gpio pins in that group).
67
68 gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
69
70 mux groups:
71
72 These all support function.
73
74 gpio0
75 pins: gpio0.
76 function: ir_mod_stable_out.
77 gpio1
78 pins: gpio1.
79 function: ir_mod_power_out.
80
81 drive groups:
82
83 These support input-schmitt-enable, input-schmitt-disable,
84 drive-strength, low-power-enable, and low-power-disable.
85
86 pdc
87 pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
88 ext_power.
89
90Example:
91
92 pinctrl_pdc: pinctrl@02006500 {
93 #gpio-range-cells = <3>;
94 compatible = "img,tz1090-pdc-pinctrl";
95 reg = <0x02006500 0x100>;
96 };
97
98Example board file extracts:
99
100 &pinctrl_pdc {
101 pinctrl-names = "default";
102 pinctrl-0 = <&syswake_default>;
103
104 syswake_default: syswakes {
105 syswake_cfg {
106 tz1090,pins = "sys_wake0",
107 "sys_wake1",
108 "sys_wake2";
109 pull-up;
110 };
111 };
112 irmod_default: irmod {
113 gpio0_cfg {
114 tz1090,pins = "gpio0";
115 tz1090,function = "ir_mod_stable_out";
116 };
117 gpio1_cfg {
118 tz1090,pins = "gpio1";
119 tz1090,function = "ir_mod_power_out";
120 };
121 };
122 };
123
124 ir: ir@02006200 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&irmod_default>;
127 };
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
new file mode 100644
index 000000000000..4b27c99f7f9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
@@ -0,0 +1,227 @@
1ImgTec TZ1090 pin controller
2
3Required properties:
4- compatible: "img,tz1090-pinctrl"
5- reg: Should contain the register physical address and length of the pad
6 configuration registers (CR_PADS_* and CR_IF_CTL0).
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12TZ1090's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function. For this reason, even seemingly boolean
26values are actually tristates in this binding: unspecified, off, or on.
27Unspecified is represented as an absent property, and off/on are represented as
28integer values 0 and 1.
29
30Required subnode-properties:
31- tz1090,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- tz1090,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below, including
37 which pingroups can be muxed to them.
38- supported generic pinconfig properties (for further details see
39 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
40 - bias-disable
41 - bias-high-impedance
42 - bias-bus-hold
43 - bias-pull-up
44 - bias-pull-down
45 - input-schmitt-enable
46 - input-schmitt-disable
47 - drive-strength: Integer, control drive strength of pins in mA.
48 2: 2mA
49 4: 4mA
50 8: 8mA
51 12: 12mA
52
53
54Note that many of these properties are only valid for certain specific pins
55or groups. See the TZ1090 TRM for complete details regarding which groups
56support which functionality. The Linux pinctrl driver may also be a useful
57reference.
58
59Valid values for pin and group names are:
60
61 gpio pins:
62
63 These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
64 bias-bus-hold (which can also be provided to any of the groups below to set
65 it for all pins in that group).
66
67 They also all support the some form of muxing. Any pins which are contained
68 in one of the mux groups (see below) can be muxed only to the functions
69 supported by the mux group. All other pins can be muxed to the "perip"
70 function which which enables them with their intended peripheral.
71
72 Different pins in the same mux group cannot be muxed to different functions,
73 however it is possible to mux only a subset of the pins in a mux group to a
74 particular function and leave the remaining pins unmuxed. This is useful if
75 the board connects certain pins in a group to other devices to be controlled
76 by GPIO, and you don't want the usual peripheral to have any control of the
77 pin.
78
79 ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
80 i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
81 i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
82 scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
83 sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
84 spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
85 spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
86 tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
87 tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
88 tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
89 tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
90 tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
91 uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
92
93 bias-high-impediance: supported.
94 bias-pull-up: supported.
95 bias-pull-down: supported.
96 bias-bus-hold: supported.
97 function: perip or those supported by pin's mux group.
98
99 other pins:
100
101 These other pins are part of various pin groups below, but can't be
102 controlled as GPIOs. They do however support bias-high-impediance,
103 bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
104 to any of the groups below to set it for all pins in that group).
105
106 clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
107
108 bias-high-impediance: supported.
109 bias-pull-up: supported.
110 bias-pull-down: supported.
111 bias-bus-hold: supported.
112
113 mux groups:
114
115 These all support function, and some support drive configs.
116
117 afe
118 pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
119 ant_sel1, gain0, gain1, gain2, gain3, gain4,
120 gain5, gain6, gain7.
121 function: afe, ts_out_0.
122 input-schmitt-enable: supported.
123 input-schmitt-disable: supported.
124 drive-strength: supported.
125 pdm_d
126 pins: pdm_d.
127 function: pdm_dac, usb_vbus.
128 sdh
129 pins: sdh_cd, sdh_wp, sdh_clk_in.
130 function: sdh, sdio.
131 sdio
132 pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
133 sdio_d3.
134 function: sdio, sdh.
135 spi1_cs2
136 pins: spi1_cs2.
137 function: spi1_cs2, usb_vbus.
138 tft
139 pins: tft_red0, tft_red1, tft_red2, tft_red3,
140 tft_red4, tft_red5, tft_red6, tft_red7,
141 tft_green0, tft_green1, tft_green2, tft_green3,
142 tft_green4, tft_green5, tft_green6, tft_green7,
143 tft_blue0, tft_blue1, tft_blue2, tft_blue3,
144 tft_blue4, tft_blue5, tft_blue6, tft_blue7,
145 tft_vdden_gd, tft_panelclk, tft_blank_ls,
146 tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
147 tft_pwrsave.
148 function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
149 lcd_trace, phy_ringosc.
150 input-schmitt-enable: supported.
151 input-schmitt-disable: supported.
152 drive-strength: supported.
153
154 drive groups:
155
156 These all support input-schmitt-enable, input-schmitt-disable,
157 and drive-strength.
158
159 jtag
160 pins: tck, trst, tdi, tdo, tms.
161 scb1
162 pins: scb1_sdat, scb1_sclk.
163 scb2
164 pins: scb2_sdat, scb2_sclk.
165 spi0
166 pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
167 spi1
168 pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
169 uart
170 pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
171 uart1_txd, uart1_rxd.
172 drive_i2s
173 pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
174 i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
175 drive_pdm
176 pins: clk_out0, pdm_b, pdm_a.
177 drive_scb0
178 pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
179 drive_sdio
180 pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
181 sdh_wp, sdh_cd, sdh_clk_in.
182
183 convenience groups:
184
185 These are just convenient groupings of pins and don't support any drive
186 configs.
187
188 uart0
189 pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
190 uart1
191 pins: uart1_rxd, uart1_txd.
192 scb0
193 pins: scb0_sclk, scb0_sdat.
194 i2s
195 pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
196 i2s_lrclk_out, i2s_mclk.
197
198Example:
199
200 pinctrl: pinctrl@02005800 {
201 #gpio-range-cells = <3>;
202 compatible = "img,tz1090-pinctrl";
203 reg = <0x02005800 0xe4>;
204 };
205
206Example board file extract:
207
208 &pinctrl {
209 uart0_default: uart0 {
210 uart0_cfg {
211 tz1090,pins = "uart0_rxd",
212 "uart0_txd";
213 tz1090,function = "perip";
214 };
215 };
216 tft_default: tft {
217 tft_cfg {
218 tz1090,pins = "tft";
219 tz1090,function = "tft";
220 };
221 };
222 };
223
224 uart@02004b00 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&uart0_default>;
227 };
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index a648aaad6110..50ec3512a292 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -10,29 +10,31 @@ Required properties:
10Available mpp pins/groups and functions: 10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given 11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document. 12only for more detailed description in this document.
13Note: pmu* also allows for Power Management functions listed below
13 14
14name pins functions 15name pins functions
15================================================================================ 16================================================================================
16mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm) 17mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
17mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm) 18mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
18mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), 19mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
19 uart1(rts) 20 uart1(rts), pmu*
20mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), 21mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
21 uart1(cts), lcd-spi(cs1) 22 uart1(cts), lcd-spi(cs1), pmu*
22mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso) 23mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
23mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs) 24mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
24mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi) 25mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
25mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck) 26mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
26mpp8 8 gpio, pmu, watchdog(rstout) 27mpp8 8 gpio, pmu, watchdog(rstout), pmu*
27mpp9 9 gpio, pmu, pex1(clkreq) 28mpp9 9 gpio, pmu, pex1(clkreq), pmu*
28mpp10 10 gpio, pmu, ssp(sclk) 29mpp10 10 gpio, pmu, ssp(sclk), pmu*
29mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), 30mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
30 sdio1(ledctrl), pex0(clkreq) 31 sdio1(ledctrl), pex0(clkreq), pmu*
31mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act) 32mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
33 sata(act), pmu*
32mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), 34mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
33 ssp(extclk) 35 ssp(extclk), pmu*
34mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd) 36mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
35mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm) 37mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
36mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) 38mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
37mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), 39mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
38 ac97-1(sysclko) 40 ac97-1(sysclko)
@@ -57,6 +59,21 @@ mpp_nand 64-71 gpo, nand
57audio0 - i2s, ac97 59audio0 - i2s, ac97
58twsi - none, opt1, opt2, opt3 60twsi - none, opt1, opt2, opt3
59 61
62Power Management functions (pmu*):
63pmu-nc Pin not driven by any PM function
64pmu-low Pin driven low (0)
65pmu-high Pin driven high (1)
66pmic(sdi) Pin is used for PMIC SDI
67cpu-pwr-down Pin is used for CPU_PWRDWN
68standby-pwr-down Pin is used for STBY_PWRDWN
69core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
70cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
71bat-fault Pin is used for BATTERY_FAULT
72ext0-wakeup Pin is used for EXT0_WU
73ext1-wakeup Pin is used for EXT0_WU
74ext2-wakeup Pin is used for EXT0_WU
75pmu-blink Pin is used for blink function
76
60Notes: 77Notes:
61* group "mpp_audio1" allows the following functions and gpio pins: 78* group "mpp_audio1" allows the following functions and gpio pins:
62 - gpio : gpio on pins 52-57 79 - gpio : gpio on pins 52-57
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index c95ea8278f87..aeb3c995cc04 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -126,3 +126,51 @@ device; they may be grandchildren, for example. Whether this is legal, and
126whether there is any interaction between the child and intermediate parent 126whether there is any interaction between the child and intermediate parent
127nodes, is again defined entirely by the binding for the individual pin 127nodes, is again defined entirely by the binding for the individual pin
128controller device. 128controller device.
129
130== Using generic pinconfig options ==
131
132Generic pinconfig parameters can be used by defining a separate node containing
133the applicable parameters (and optional values), like:
134
135pcfg_pull_up: pcfg_pull_up {
136 bias-pull-up;
137 drive-strength = <20>;
138};
139
140This node should then be referenced in the appropriate pinctrl node as a phandle
141and parsed in the driver using the pinconf_generic_parse_dt_config function.
142
143Supported configuration parameters are:
144
145bias-disable - disable any pin bias
146bias-high-impedance - high impedance mode ("third-state", "floating")
147bias-bus-hold - latch weakly
148bias-pull-up - pull up the pin
149bias-pull-down - pull down the pin
150bias-pull-pin-default - use pin-default pull state
151drive-push-pull - drive actively high and low
152drive-open-drain - drive with open drain
153drive-open-source - drive with open source
154drive-strength - sink or source at most X mA
155input-schmitt-enable - enable schmitt-trigger mode
156input-schmitt-disable - disable schmitt-trigger mode
157input-debounce - debounce mode with debound time X
158low-power-enable - enable low power mode
159low-power-disable - disable low power mode
160output-low - set the pin to output mode with low level
161output-high - set the pin to output mode with high level
162
163Arguments for parameters:
164
165- bias-pull-up, -down and -pin-default take as optional argument on hardware
166 supporting it the pull strength in Ohm. bias-disable will disable the pull.
167
168- drive-strength takes as argument the target strength in mA.
169
170- input-debounce takes the debounce time in usec as argument
171 or 0 to disable debouncing
172
173All parameters not listed here, do not take an argument.
174
175More in-depth documentation on these parameters can be found in
176<include/linux/pinctrl/pinconfig-generic.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 08f0c3d01575..5a02e30dd262 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -18,7 +18,8 @@ Optional properties:
18 pin functions is ignored 18 pin functions is ignored
19 19
20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls 20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
21 more than one pin 21 more than one pin, for which "pinctrl-single,function-mask" property specifies
22 position mask of pin.
22 23
23- pinctrl-single,drive-strength : array of value that are used to configure 24- pinctrl-single,drive-strength : array of value that are used to configure
24 drive strength in the pinmux register. They're value of drive strength 25 drive strength in the pinmux register. They're value of drive strength
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 000000000000..d5dac7b843a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,153 @@
1* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
2
3The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
4SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
5
6
7Pin Control
8-----------
9
10Required Properties:
11
12 - compatible: should be one of the following.
13 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
14 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
15 - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
16 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
17 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
18 - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
19 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
20
21 - reg: Base address and length of each memory resource used by the pin
22 controller hardware module.
23
24Optional properties:
25
26 - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
27 otherwise. Should be 3.
28
29The PFC node also acts as a container for pin configuration nodes. Please refer
30to pinctrl-bindings.txt in this directory for the definition of the term "pin
31configuration node" and for the common pinctrl bindings used by client devices.
32
33Each pin configuration node represents a desired configuration for a pin, a
34pin group, or a list of pins or pin groups. The configuration can include the
35function to select on those pin(s) and pin configuration parameters (such as
36pull-up and pull-down).
37
38Pin configuration nodes contain pin configuration properties, either directly
39or grouped in child subnodes. Both pin muxing and configuration parameters can
40be grouped in that way and referenced as a single pin configuration node by
41client devices.
42
43A configuration node or subnode must reference at least one pin (through the
44pins or pin groups properties) and contain at least a function or one
45configuration parameter. When the function is present only pin groups can be
46used to reference pins.
47
48All pin configuration nodes and subnodes names are ignored. All of those nodes
49are parsed through phandles and processed purely based on their content.
50
51Pin Configuration Node Properties:
52
53- renesas,pins : An array of strings, each string containing the name of a pin.
54- renesas,groups : An array of strings, each string containing the name of a pin
55 group.
56
57- renesas,function: A string containing the name of the function to mux to the
58 pin group(s) specified by the renesas,groups property
59
60 Valid values for pin, group and function names can be found in the group and
61 function arrays of the PFC data file corresponding to the SoC
62 (drivers/pinctrl/sh-pfc/pfc-*.c)
63
64The pin configuration parameters use the generic pinconf bindings defined in
65pinctrl-bindings.txt in this directory. The supported parameters are
66bias-disable, bias-pull-up and bias-pull-down.
67
68
69GPIO
70----
71
72On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
73node.
74
75Required Properties:
76
77 - gpio-controller: Marks the device node as a gpio controller.
78
79 - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
80 cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
81 GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
82
83The syntax of the gpio specifier used by client nodes should be the following
84with values derived from the SoC user manual.
85
86 <[phandle of the gpio controller node]
87 [pin number within the gpio controller]
88 [flags]>
89
90On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
91Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
92for documentation of the GPIO device tree bindings on those platforms.
93
94
95Examples
96--------
97
98Example 1: SH73A0 (SH-Mobile AG5) pin controller node
99
100 pfc: pfc@e6050000 {
101 compatible = "renesas,pfc-sh73a0";
102 reg = <0xe6050000 0x8000>,
103 <0xe605801c 0x1c>;
104 gpio-controller;
105 #gpio-cells = <2>;
106 };
107
108Example 2: A GPIO LED node that references a GPIO
109
110 #include <dt-bindings/gpio/gpio.h>
111
112 leds {
113 compatible = "gpio-leds";
114 led1 {
115 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
116 };
117 };
118
119Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
120 for the MMCIF and SCIFA4 devices
121
122 &pfc {
123 pinctrl-0 = <&scifa4_pins>;
124 pinctrl-names = "default";
125
126 mmcif_pins: mmcif {
127 mux {
128 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
129 renesas,function = "mmc0";
130 };
131 cfg {
132 renesas,groups = "mmc0_data8_0";
133 renesas,pins = "PORT279";
134 bias-pull-up;
135 };
136 };
137
138 scifa4_pins: scifa4 {
139 renesas,groups = "scifa4_data", "scifa4_ctrl";
140 renesas,function = "scifa4";
141 };
142 };
143
144Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
145
146 &mmcif {
147 pinctrl-0 = <&mmcif_pins>;
148 pinctrl-names = "default";
149
150 bus-width = <8>;
151 vmmc-supply = <&reg_1p8v>;
152 status = "okay";
153 };
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
new file mode 100644
index 000000000000..b0fb1018d7ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -0,0 +1,97 @@
1* Rockchip Pinmux Controller
2
3The Rockchip Pinmux Controller, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
64 muxing options with option 0 being the use as a GPIO.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12The Rockchip pin configuration node is a node of a group of pins which can be
13used for a specific device or function. This node represents both mux and
14config of the pins in that group. The 'pins' selects the function mode(also
15named pin mode) this pin can work on and the 'config' configures various pad
16settings such as pull-up, etc.
17
18The pins are grouped into up to 5 individual pin banks which need to be
19defined as gpio sub-nodes of the pinmux controller.
20
21Required properties for iomux controller:
22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24
25Required properties for gpio sub nodes:
26 - compatible: "rockchip,gpio-bank"
27 - reg: register of the gpio bank (different than the iomux registerset)
28 - interrupts: base interrupt of the gpio bank in the interrupt controller
29 - clocks: clock that drives this bank
30 - gpio-controller: identifies the node as a gpio controller and pin bank.
31 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
32 binding is used, the amount of cells must be specified as 2. See generic
33 GPIO binding documentation for description of particular cells.
34 - interrupt-controller: identifies the controller node as interrupt-parent.
35 - #interrupt-cells: the value of this property should be 2 and the interrupt
36 cells should use the standard two-cell scheme described in
37 bindings/interrupt-controller/interrupts.txt
38
39Required properties for pin configuration node:
40 - rockchip,pins: 3 integers array, represents a group of pins mux and config
41 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
42 The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
43 The phandle of a node containing the generic pinconfig options
44 to use, as described in pinctrl-bindings.txt in this directory.
45
46Examples:
47
48#include <dt-bindings/pinctrl/rockchip.h>
49
50...
51
52pinctrl@20008000 {
53 compatible = "rockchip,rk3066a-pinctrl";
54 reg = <0x20008000 0x150>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 gpio0: gpio0@20034000 {
60 compatible = "rockchip,gpio-bank";
61 reg = <0x20034000 0x100>;
62 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_gates8 9>;
64
65 gpio-controller;
66 #gpio-cells = <2>;
67
68 interrupt-controller;
69 #interrupt-cells = <2>;
70 };
71
72 ...
73
74 pcfg_pull_default: pcfg_pull_default {
75 bias-pull-pin-default
76 };
77
78 uart2 {
79 uart2_xfer: uart2-xfer {
80 rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
81 <RK_GPIO1 9 1 &pcfg_pull_default>;
82 };
83 };
84};
85
86uart2: serial@20064000 {
87 compatible = "snps,dw-apb-uart";
88 reg = <0x20064000 0x400>;
89 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
90 reg-shift = <2>;
91 reg-io-width = <1>;
92 clocks = <&mux_uart2>;
93 status = "okay";
94
95 pinctrl-names = "default";
96 pinctrl-0 = <&uart2_xfer>;
97};
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
new file mode 100644
index 000000000000..e3865e136067
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
@@ -0,0 +1,352 @@
1ST Ericsson abx500 pinmux controller
2
3Required properties:
4- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
5 "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
6
7Please refer to pinctrl-bindings.txt in this directory for details of the
8common pinctrl bindings used by client devices, including the meaning of the
9phrase "pin configuration node".
10
11ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
12subnodes. Each of these subnodes represents some desired configuration for a
13pin, a group, or a list of pins or groups. This configuration can include the
14mux function to select on those pin(s)/group(s), and various pin configuration
15parameters, such as input, output, pull up, pull down...
16
17The name of each subnode is not important; all subnodes should be enumerated
18and processed purely based on their content.
19
20Required subnode-properties:
21- ste,pins : An array of strings. Each string contains the name of a pin or
22 group.
23
24Optional subnode-properties:
25- ste,function: A string containing the name of the function to mux to the
26 pin or group.
27
28- generic pin configuration option to use. Example :
29
30 default_cfg {
31 ste,pins = "GPIO1";
32 bias-disable;
33 };
34
35- ste,config: Handle of pin configuration node containing the generic
36 pinconfig options to use, as described in pinctrl-bindings.txt in
37 this directory. Example :
38
39 pcfg_bias_disable: pcfg_bias_disable {
40 bias-disable;
41 };
42
43 default_cfg {
44 ste,pins = "GPIO1";
45 ste.config = <&pcfg_bias_disable>;
46 };
47
48Example board file extract:
49
50&pinctrl_abx500 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>;
53
54 sysclkreq2 {
55 sysclkreq2_default_mode: sysclkreq2_default {
56 default_mux {
57 ste,function = "sysclkreq";
58 ste,pins = "sysclkreq2_d_1";
59 };
60 default_cfg {
61 ste,pins = "GPIO1";
62 bias-disable;
63 };
64 };
65 };
66 sysclkreq3 {
67 sysclkreq3_default_mode: sysclkreq3_default {
68 default_mux {
69 ste,function = "sysclkreq";
70 ste,pins = "sysclkreq3_d_1";
71 };
72 default_cfg {
73 ste,pins = "GPIO2";
74 output-low;
75 };
76 };
77 };
78 gpio3 {
79 gpio3_default_mode: gpio3_default {
80 default_mux {
81 ste,function = "gpio";
82 ste,pins = "gpio3_a_1";
83 };
84 default_cfg {
85 ste,pins = "GPIO3";
86 output-low;
87 };
88 };
89 };
90 sysclkreq6 {
91 sysclkreq6_default_mode: sysclkreq6_default {
92 default_mux {
93 ste,function = "sysclkreq";
94 ste,pins = "sysclkreq6_d_1";
95 };
96 default_cfg {
97 ste,pins = "GPIO4";
98 bias-disable;
99 };
100 };
101 };
102 pwmout1 {
103 pwmout1_default_mode: pwmout1_default {
104 default_mux {
105 ste,function = "pwmout";
106 ste,pins = "pwmout1_d_1";
107 };
108 default_cfg {
109 ste,pins = "GPIO14";
110 output-low;
111 };
112 };
113 };
114 pwmout2 {
115 pwmout2_default_mode: pwmout2_default {
116 pwmout2_default_mux {
117 ste,function = "pwmout";
118 ste,pins = "pwmout2_d_1";
119 };
120 pwmout2_default_cfg {
121 ste,pins = "GPIO15";
122 output-low;
123 };
124 };
125 };
126 pwmout3 {
127 pwmout3_default_mode: pwmout3_default {
128 pwmout3_default_mux {
129 ste,function = "pwmout";
130 ste,pins = "pwmout3_d_1";
131 };
132 pwmout3_default_cfg {
133 ste,pins = "GPIO16";
134 output-low;
135 };
136 };
137 };
138 adi1 {
139
140 adi1_default_mode: adi1_default {
141 adi1_default_mux {
142 ste,function = "adi1";
143 ste,pins = "adi1_d_1";
144 };
145 adi1_default_cfg1 {
146 ste,pins = "GPIO17","GPIO19","GPIO20";
147 bias-disable;
148 };
149 adi1_default_cfg2 {
150 ste,pins = "GPIO18";
151 output-low;
152 };
153 };
154 };
155 dmic12 {
156 dmic12_default_mode: dmic12_default {
157 dmic12_default_mux {
158 ste,function = "dmic";
159 ste,pins = "dmic12_d_1";
160 };
161 dmic12_default_cfg1 {
162 ste,pins = "GPIO27";
163 output-low;
164 };
165 dmic12_default_cfg2 {
166 ste,pins = "GPIO28";
167 bias-disable;
168 };
169 };
170 };
171 dmic34 {
172 dmic34_default_mode: dmic34_default {
173 dmic34_default_mux {
174 ste,function = "dmic";
175 ste,pins = "dmic34_d_1";
176 };
177 dmic34_default_cfg1 {
178 ste,pins = "GPIO29";
179 output-low;
180 };
181 dmic34_default_cfg2 {
182 ste,pins = "GPIO30";
183 bias-disable;{
184
185 };
186 };
187 };
188 dmic56 {
189 dmic56_default_mode: dmic56_default {
190 dmic56_default_mux {
191 ste,function = "dmic";
192 ste,pins = "dmic56_d_1";
193 };
194 dmic56_default_cfg1 {
195 ste,pins = "GPIO31";
196 output-low;
197 };
198 dmic56_default_cfg2 {
199 ste,pins = "GPIO32";
200 bias-disable;
201 };
202 };
203 };
204 sysclkreq5 {
205 sysclkreq5_default_mode: sysclkreq5_default {
206 sysclkreq5_default_mux {
207 ste,function = "sysclkreq";
208 ste,pins = "sysclkreq5_d_1";
209 };
210 sysclkreq5_default_cfg {
211 ste,pins = "GPIO42";
212 output-low;
213 };
214 };
215 };
216 batremn {
217 batremn_default_mode: batremn_default {
218 batremn_default_mux {
219 ste,function = "batremn";
220 ste,pins = "batremn_d_1";
221 };
222 batremn_default_cfg {
223 ste,pins = "GPIO43";
224 bias-disable;
225 };
226 };
227 };
228 service {
229 service_default_mode: service_default {
230 service_default_mux {
231 ste,function = "service";
232 ste,pins = "service_d_1";
233 };
234 service_default_cfg {
235 ste,pins = "GPIO44";
236 bias-disable;
237 };
238 };
239 };
240 pwrctrl0 {
241 pwrctrl0_default_mux: pwrctrl0_mux {
242 pwrctrl0_default_mux {
243 ste,function = "pwrctrl";
244 ste,pins = "pwrctrl0_d_1";
245 };
246 };
247 pwrctrl0_default_mode: pwrctrl0_default {
248 pwrctrl0_default_cfg {
249 ste,pins = "GPIO45";
250 bias-disable;
251 };
252 };
253 };
254 pwrctrl1 {
255 pwrctrl1_default_mux: pwrctrl1_mux {
256 pwrctrl1_default_mux {
257 ste,function = "pwrctrl";
258 ste,pins = "pwrctrl1_d_1";
259 };
260 };
261 pwrctrl1_default_mode: pwrctrl1_default {
262 pwrctrl1_default_cfg {
263 ste,pins = "GPIO46";
264 bias-disable;
265 };
266 };
267 };
268 pwmextvibra1 {
269 pwmextvibra1_default_mode: pwmextvibra1_default {
270 pwmextvibra1_default_mux {
271 ste,function = "pwmextvibra";
272 ste,pins = "pwmextvibra1_d_1";
273 };
274 pwmextvibra1_default_cfg {
275 ste,pins = "GPIO47";
276 bias-disable;
277 };
278 };
279 };
280 pwmextvibra2 {
281 pwmextvibra2_default_mode: pwmextvibra2_default {
282 pwmextvibra2_default_mux {
283 ste,function = "pwmextvibra";
284 ste,pins = "pwmextvibra2_d_1";
285 };
286 pwmextvibra1_default_cfg {
287 ste,pins = "GPIO48";
288 bias-disable;
289 };
290 };
291 };
292 gpio51 {
293 gpio51_default_mode: gpio51_default {
294 gpio51_default_mux {
295 ste,function = "gpio";
296 ste,pins = "gpio51_a_1";
297 };
298 gpio51_default_cfg {
299 ste,pins = "GPIO51";
300 output-low;
301 };
302 };
303 };
304 gpio52 {
305 gpio52_default_mode: gpio52_default {
306 gpio52_default_mux {
307 ste,function = "gpio";
308 ste,pins = "gpio52_a_1";
309 };
310 gpio52_default_cfg {
311 ste,pins = "GPIO52";
312 bias-pull-down;
313 };
314 };
315 };
316 gpio53 {
317 gpio53_default_mode: gpio53_default {
318 gpio53_default_mux {
319 ste,function = "gpio";
320 ste,pins = "gpio53_a_1";
321 };
322 gpio53_default_cfg {
323 ste,pins = "GPIO53";
324 bias-pull-down;
325 };
326 };
327 };
328 gpio54 {
329 gpio54_default_mode: gpio54_default {
330 gpio54_default_mux {
331 ste,function = "gpio";
332 ste,pins = "gpio54_a_1";
333 };
334 gpio54_default_cfg {
335 ste,pins = "GPIO54";
336 output-low;
337 };
338 };
339 };
340 pdmclkdat {
341 pdmclkdat_default_mode: pdmclkdat_default {
342 pdmclkdat_default_mux {
343 ste,function = "pdm";
344 ste,pins = "pdmclkdat_d_1";
345 };
346 pdmclkdat_default_cfg {
347 ste,pins = "GPIO55", "GPIO56";
348 bias-disable;
349 };
350 };
351 };
352};
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index 447fd4cd54ec..c5948c7d662a 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -203,15 +203,8 @@ using a certain resistor value - pull up and pull down - so that the pin has a
203stable value when nothing is driving the rail it is connected to, or when it's 203stable value when nothing is driving the rail it is connected to, or when it's
204unconnected. 204unconnected.
205 205
206Pin configuration can be programmed either using the explicit APIs described 206Pin configuration can be programmed by adding configuration entries into the
207immediately below, or by adding configuration entries into the mapping table; 207mapping table; see section "Board/machine configuration" below.
208see section "Board/machine configuration" below.
209
210For example, a platform may do the following to pull up a pin to VDD:
211
212#include <linux/pinctrl/consumer.h>
213
214ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
215 208
216The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP 209The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
217above, is entirely defined by the pin controller driver. 210above, is entirely defined by the pin controller driver.
@@ -350,6 +343,23 @@ chip b:
350 - GPIO range : [48 .. 55] 343 - GPIO range : [48 .. 55]
351 - pin range : [64 .. 71] 344 - pin range : [64 .. 71]
352 345
346The above examples assume the mapping between the GPIOs and pins is
347linear. If the mapping is sparse or haphazard, an array of arbitrary pin
348numbers can be encoded in the range like this:
349
350static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
351
352static struct pinctrl_gpio_range gpio_range = {
353 .name = "chip",
354 .id = 0,
355 .base = 32,
356 .pins = &range_pins,
357 .npins = ARRAY_SIZE(range_pins),
358 .gc = &chip;
359};
360
361In this case the pin_base property will be ignored.
362
353When GPIO-specific functions in the pin control subsystem are called, these 363When GPIO-specific functions in the pin control subsystem are called, these
354ranges will be used to look up the appropriate pin controller by inspecting 364ranges will be used to look up the appropriate pin controller by inspecting
355and matching the pin to the pin ranges across all controllers. When a 365and matching the pin to the pin ranges across all controllers. When a
@@ -357,9 +367,9 @@ pin controller handling the matching range is found, GPIO-specific functions
357will be called on that specific pin controller. 367will be called on that specific pin controller.
358 368
359For all functionalities dealing with pin biasing, pin muxing etc, the pin 369For all functionalities dealing with pin biasing, pin muxing etc, the pin
360controller subsystem will subtract the range's .base offset from the passed 370controller subsystem will look up the corresponding pin number from the passed
361in gpio number, and add the ranges's .pin_base offset to retrive a pin number. 371in gpio number, and use the range's internals to retrive a pin number. After
362After that, the subsystem passes it on to the pin control driver, so the driver 372that, the subsystem passes it on to the pin control driver, so the driver
363will get an pin number into its handled number range. Further it is also passed 373will get an pin number into its handled number range. Further it is also passed
364the range ID value, so that the pin controller knows which range it should 374the range ID value, so that the pin controller knows which range it should
365deal with. 375deal with.
@@ -368,6 +378,7 @@ Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
368section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind 378section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
369pinctrl and gpio drivers. 379pinctrl and gpio drivers.
370 380
381
371PINMUX interfaces 382PINMUX interfaces
372================= 383=================
373 384
@@ -1226,8 +1237,8 @@ setting up the config and muxing for the pins right before the device is
1226probing, nevertheless orthogonal to the GPIO subsystem. 1237probing, nevertheless orthogonal to the GPIO subsystem.
1227 1238
1228But there are also situations where it makes sense for the GPIO subsystem 1239But there are also situations where it makes sense for the GPIO subsystem
1229to communicate directly with with the pinctrl subsystem, using the latter 1240to communicate directly with the pinctrl subsystem, using the latter as a
1230as a back-end. This is when the GPIO driver may call out to the functions 1241back-end. This is when the GPIO driver may call out to the functions
1231described in the section "Pin control interaction with the GPIO subsystem" 1242described in the section "Pin control interaction with the GPIO subsystem"
1232above. This only involves per-pin multiplexing, and will be completely 1243above. This only involves per-pin multiplexing, and will be completely
1233hidden behind the gpio_*() function namespace. In this case, the driver 1244hidden behind the gpio_*() function namespace. In this case, the driver
diff --git a/MAINTAINERS b/MAINTAINERS
index a98219eb132a..ff105830de63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6295,6 +6295,16 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6295S: Maintained 6295S: Maintained
6296F: drivers/pinctrl/pinctrl-at91.c 6296F: drivers/pinctrl/pinctrl-at91.c
6297 6297
6298PIN CONTROLLER - SAMSUNG
6299M: Tomasz Figa <t.figa@samsung.com>
6300M: Thomas Abraham <thomas.abraham@linaro.org>
6301L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
6302L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
6303S: Maintained
6304F: drivers/pinctrl/pinctrl-exynos.*
6305F: drivers/pinctrl/pinctrl-s3c*
6306F: drivers/pinctrl/pinctrl-samsung.*
6307
6298PIN CONTROLLER - ST SPEAR 6308PIN CONTROLLER - ST SPEAR
6299M: Viresh Kumar <viresh.linux@gmail.com> 6309M: Viresh Kumar <viresh.linux@gmail.com>
6300L: spear-devel@list.st.com 6310L: spear-devel@list.st.com
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
index 67a274e86727..5fb74b43848e 100644
--- a/drivers/base/pinctrl.c
+++ b/drivers/base/pinctrl.c
@@ -48,6 +48,25 @@ int pinctrl_bind_pins(struct device *dev)
48 goto cleanup_get; 48 goto cleanup_get;
49 } 49 }
50 50
51#ifdef CONFIG_PM
52 /*
53 * If power management is enabled, we also look for the optional
54 * sleep and idle pin states, with semantics as defined in
55 * <linux/pinctrl/pinctrl-state.h>
56 */
57 dev->pins->sleep_state = pinctrl_lookup_state(dev->pins->p,
58 PINCTRL_STATE_SLEEP);
59 if (IS_ERR(dev->pins->sleep_state))
60 /* Not supplying this state is perfectly legal */
61 dev_dbg(dev, "no sleep pinctrl state\n");
62
63 dev->pins->idle_state = pinctrl_lookup_state(dev->pins->p,
64 PINCTRL_STATE_IDLE);
65 if (IS_ERR(dev->pins->idle_state))
66 /* Not supplying this state is perfectly legal */
67 dev_dbg(dev, "no idle pinctrl state\n");
68#endif
69
51 return 0; 70 return 0;
52 71
53 /* 72 /*
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 650293ff4d62..c7e3b0c1a1ca 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -148,10 +148,6 @@ struct i2c_nmk_client {
148 * @stop: stop condition. 148 * @stop: stop condition.
149 * @xfer_complete: acknowledge completion for a I2C message. 149 * @xfer_complete: acknowledge completion for a I2C message.
150 * @result: controller propogated result. 150 * @result: controller propogated result.
151 * @pinctrl: pinctrl handle.
152 * @pins_default: default state for the pins.
153 * @pins_idle: idle state for the pins.
154 * @pins_sleep: sleep state for the pins.
155 * @busy: Busy doing transfer. 151 * @busy: Busy doing transfer.
156 */ 152 */
157struct nmk_i2c_dev { 153struct nmk_i2c_dev {
@@ -165,11 +161,6 @@ struct nmk_i2c_dev {
165 int stop; 161 int stop;
166 struct completion xfer_complete; 162 struct completion xfer_complete;
167 int result; 163 int result;
168 /* Three pin states - default, idle & sleep */
169 struct pinctrl *pinctrl;
170 struct pinctrl_state *pins_default;
171 struct pinctrl_state *pins_idle;
172 struct pinctrl_state *pins_sleep;
173 bool busy; 164 bool busy;
174}; 165};
175 166
@@ -645,13 +636,7 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
645 } 636 }
646 637
647 /* Optionaly enable pins to be muxed in and configured */ 638 /* Optionaly enable pins to be muxed in and configured */
648 if (!IS_ERR(dev->pins_default)) { 639 pinctrl_pm_select_default_state(&dev->adev->dev);
649 status = pinctrl_select_state(dev->pinctrl,
650 dev->pins_default);
651 if (status)
652 dev_err(&dev->adev->dev,
653 "could not set default pins\n");
654 }
655 640
656 status = init_hw(dev); 641 status = init_hw(dev);
657 if (status) 642 if (status)
@@ -681,13 +666,7 @@ out:
681 clk_disable_unprepare(dev->clk); 666 clk_disable_unprepare(dev->clk);
682out_clk: 667out_clk:
683 /* Optionally let pins go into idle state */ 668 /* Optionally let pins go into idle state */
684 if (!IS_ERR(dev->pins_idle)) { 669 pinctrl_pm_select_idle_state(&dev->adev->dev);
685 status = pinctrl_select_state(dev->pinctrl,
686 dev->pins_idle);
687 if (status)
688 dev_err(&dev->adev->dev,
689 "could not set pins to idle state\n");
690 }
691 670
692 pm_runtime_put_sync(&dev->adev->dev); 671 pm_runtime_put_sync(&dev->adev->dev);
693 672
@@ -882,41 +861,22 @@ static int nmk_i2c_suspend(struct device *dev)
882{ 861{
883 struct amba_device *adev = to_amba_device(dev); 862 struct amba_device *adev = to_amba_device(dev);
884 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 863 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
885 int ret;
886 864
887 if (nmk_i2c->busy) 865 if (nmk_i2c->busy)
888 return -EBUSY; 866 return -EBUSY;
889 867
890 if (!IS_ERR(nmk_i2c->pins_sleep)) { 868 pinctrl_pm_select_sleep_state(dev);
891 ret = pinctrl_select_state(nmk_i2c->pinctrl,
892 nmk_i2c->pins_sleep);
893 if (ret)
894 dev_err(dev, "could not set pins to sleep state\n");
895 }
896 869
897 return 0; 870 return 0;
898} 871}
899 872
900static int nmk_i2c_resume(struct device *dev) 873static int nmk_i2c_resume(struct device *dev)
901{ 874{
902 struct amba_device *adev = to_amba_device(dev);
903 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
904 int ret;
905
906 /* First go to the default state */ 875 /* First go to the default state */
907 if (!IS_ERR(nmk_i2c->pins_default)) { 876 pinctrl_pm_select_default_state(dev);
908 ret = pinctrl_select_state(nmk_i2c->pinctrl,
909 nmk_i2c->pins_default);
910 if (ret)
911 dev_err(dev, "could not set pins to default state\n");
912 }
913 /* Then let's idle the pins until the next transfer happens */ 877 /* Then let's idle the pins until the next transfer happens */
914 if (!IS_ERR(nmk_i2c->pins_idle)) { 878 pinctrl_pm_select_idle_state(dev);
915 ret = pinctrl_select_state(nmk_i2c->pinctrl, 879
916 nmk_i2c->pins_idle);
917 if (ret)
918 dev_err(dev, "could not set pins to idle state\n");
919 }
920 return 0; 880 return 0;
921} 881}
922#else 882#else
@@ -1004,39 +964,10 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1004 dev->adev = adev; 964 dev->adev = adev;
1005 amba_set_drvdata(adev, dev); 965 amba_set_drvdata(adev, dev);
1006 966
1007 dev->pinctrl = devm_pinctrl_get(&adev->dev); 967 /* Select default pin state */
1008 if (IS_ERR(dev->pinctrl)) { 968 pinctrl_pm_select_default_state(&adev->dev);
1009 ret = PTR_ERR(dev->pinctrl); 969 /* If possible, let's go to idle until the first transfer */
1010 goto err_pinctrl; 970 pinctrl_pm_select_idle_state(&adev->dev);
1011 }
1012
1013 dev->pins_default = pinctrl_lookup_state(dev->pinctrl,
1014 PINCTRL_STATE_DEFAULT);
1015 if (IS_ERR(dev->pins_default)) {
1016 dev_err(&adev->dev, "could not get default pinstate\n");
1017 } else {
1018 ret = pinctrl_select_state(dev->pinctrl,
1019 dev->pins_default);
1020 if (ret)
1021 dev_dbg(&adev->dev, "could not set default pinstate\n");
1022 }
1023
1024 dev->pins_idle = pinctrl_lookup_state(dev->pinctrl,
1025 PINCTRL_STATE_IDLE);
1026 if (IS_ERR(dev->pins_idle)) {
1027 dev_dbg(&adev->dev, "could not get idle pinstate\n");
1028 } else {
1029 /* If possible, let's go to idle until the first transfer */
1030 ret = pinctrl_select_state(dev->pinctrl,
1031 dev->pins_idle);
1032 if (ret)
1033 dev_dbg(&adev->dev, "could not set idle pinstate\n");
1034 }
1035
1036 dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl,
1037 PINCTRL_STATE_SLEEP);
1038 if (IS_ERR(dev->pins_sleep))
1039 dev_dbg(&adev->dev, "could not get sleep pinstate\n");
1040 971
1041 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 972 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
1042 if (!dev->virtbase) { 973 if (!dev->virtbase) {
@@ -1106,7 +1037,6 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1106 iounmap(dev->virtbase); 1037 iounmap(dev->virtbase);
1107 err_no_ioremap: 1038 err_no_ioremap:
1108 kfree(dev); 1039 kfree(dev);
1109 err_pinctrl:
1110 err_no_mem: 1040 err_no_mem:
1111 1041
1112 return ret; 1042 return ret;
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index d1a769f35f9d..da4415d9dee6 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
35#include <linux/if_vlan.h> 35#include <linux/if_vlan.h>
36 36
37#include <linux/platform_data/cpsw.h> 37#include <linux/platform_data/cpsw.h>
38#include <linux/pinctrl/consumer.h>
38 39
39#include "cpsw_ale.h" 40#include "cpsw_ale.h"
40#include "cpts.h" 41#include "cpts.h"
@@ -1689,6 +1690,9 @@ static int cpsw_probe(struct platform_device *pdev)
1689 */ 1690 */
1690 pm_runtime_enable(&pdev->dev); 1691 pm_runtime_enable(&pdev->dev);
1691 1692
1693 /* Select default pin state */
1694 pinctrl_pm_select_default_state(&pdev->dev);
1695
1692 if (cpsw_probe_dt(&priv->data, pdev)) { 1696 if (cpsw_probe_dt(&priv->data, pdev)) {
1693 pr_err("cpsw: platform data missing\n"); 1697 pr_err("cpsw: platform data missing\n");
1694 ret = -ENODEV; 1698 ret = -ENODEV;
@@ -1981,6 +1985,9 @@ static int cpsw_suspend(struct device *dev)
1981 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); 1985 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
1982 pm_runtime_put_sync(&pdev->dev); 1986 pm_runtime_put_sync(&pdev->dev);
1983 1987
1988 /* Select sleep pin state */
1989 pinctrl_pm_select_sleep_state(&pdev->dev);
1990
1984 return 0; 1991 return 0;
1985} 1992}
1986 1993
@@ -1990,6 +1997,10 @@ static int cpsw_resume(struct device *dev)
1990 struct net_device *ndev = platform_get_drvdata(pdev); 1997 struct net_device *ndev = platform_get_drvdata(pdev);
1991 1998
1992 pm_runtime_get_sync(&pdev->dev); 1999 pm_runtime_get_sync(&pdev->dev);
2000
2001 /* Select default pin state */
2002 pinctrl_pm_select_default_state(&pdev->dev);
2003
1993 if (netif_running(ndev)) 2004 if (netif_running(ndev))
1994 cpsw_ndo_open(ndev); 2005 cpsw_ndo_open(ndev);
1995 return 0; 2006 return 0;
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index c47f0dbcebb5..ce7c4991e41c 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
38#include <linux/davinci_emac.h> 38#include <linux/davinci_emac.h>
39#include <linux/of.h> 39#include <linux/of.h>
40#include <linux/of_device.h> 40#include <linux/of_device.h>
41#include <linux/pinctrl/consumer.h>
41 42
42/* 43/*
43 * This timeout definition is a worst-case ultra defensive measure against 44 * This timeout definition is a worst-case ultra defensive measure against
@@ -347,6 +348,9 @@ static int davinci_mdio_probe(struct platform_device *pdev)
347 data->bus->parent = dev; 348 data->bus->parent = dev;
348 data->bus->priv = data; 349 data->bus->priv = data;
349 350
351 /* Select default pin state */
352 pinctrl_pm_select_default_state(&pdev->dev);
353
350 pm_runtime_enable(&pdev->dev); 354 pm_runtime_enable(&pdev->dev);
351 pm_runtime_get_sync(&pdev->dev); 355 pm_runtime_get_sync(&pdev->dev);
352 data->clk = clk_get(&pdev->dev, "fck"); 356 data->clk = clk_get(&pdev->dev, "fck");
@@ -453,6 +457,9 @@ static int davinci_mdio_suspend(struct device *dev)
453 spin_unlock(&data->lock); 457 spin_unlock(&data->lock);
454 pm_runtime_put_sync(data->dev); 458 pm_runtime_put_sync(data->dev);
455 459
460 /* Select sleep pin state */
461 pinctrl_pm_select_sleep_state(dev);
462
456 return 0; 463 return 0;
457} 464}
458 465
@@ -460,6 +467,9 @@ static int davinci_mdio_resume(struct device *dev)
460{ 467{
461 struct davinci_mdio_data *data = dev_get_drvdata(dev); 468 struct davinci_mdio_data *data = dev_get_drvdata(dev);
462 469
470 /* Select default pin state */
471 pinctrl_pm_select_default_state(dev);
472
463 pm_runtime_get_sync(data->dev); 473 pm_runtime_get_sync(data->dev);
464 474
465 spin_lock(&data->lock); 475 spin_lock(&data->lock);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 19396c8ffe45..5a8ad5139312 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -58,6 +58,18 @@ config PINCTRL_AT91
58 help 58 help
59 Say Y here to enable the at91 pinctrl driver 59 Say Y here to enable the at91 pinctrl driver
60 60
61config PINCTRL_BAYTRAIL
62 bool "Intel Baytrail GPIO pin control"
63 depends on GPIOLIB && ACPI && X86
64 select IRQ_DOMAIN
65 help
66 driver for memory mapped GPIO functionality on Intel Baytrail
67 platforms. Supports 3 banks with 102, 28 and 44 gpios.
68 Most pins are usually muxed to some other functionality by firmware,
69 so only a small amount is available for gpio use.
70
71 Requires ACPI device enumeration code to set up a platform device.
72
61config PINCTRL_BCM2835 73config PINCTRL_BCM2835
62 bool 74 bool
63 select PINMUX 75 select PINMUX
@@ -108,6 +120,14 @@ config PINCTRL_IMX6SL
108 help 120 help
109 Say Y here to enable the imx6sl pinctrl driver 121 Say Y here to enable the imx6sl pinctrl driver
110 122
123config PINCTRL_VF610
124 bool "Freescale Vybrid VF610 pinctrl driver"
125 depends on OF
126 depends on SOC_VF610
127 select PINCTRL_IMX
128 help
129 Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
130
111config PINCTRL_LANTIQ 131config PINCTRL_LANTIQ
112 bool 132 bool
113 depends on LANTIQ 133 depends on LANTIQ
@@ -150,6 +170,12 @@ config PINCTRL_DB8540
150 bool "DB8540 pin controller driver" 170 bool "DB8540 pin controller driver"
151 depends on PINCTRL_NOMADIK && ARCH_U8500 171 depends on PINCTRL_NOMADIK && ARCH_U8500
152 172
173config PINCTRL_ROCKCHIP
174 bool
175 select PINMUX
176 select GENERIC_PINCONF
177 select GENERIC_IRQ_CHIP
178
153config PINCTRL_SINGLE 179config PINCTRL_SINGLE
154 tristate "One-register-per-pin type device tree based pinctrl driver" 180 tristate "One-register-per-pin type device tree based pinctrl driver"
155 depends on OF 181 depends on OF
@@ -192,6 +218,18 @@ config PINCTRL_TEGRA114
192 bool 218 bool
193 select PINCTRL_TEGRA 219 select PINCTRL_TEGRA
194 220
221config PINCTRL_TZ1090
222 bool "Toumaz Xenif TZ1090 pin control driver"
223 depends on SOC_TZ1090
224 select PINMUX
225 select GENERIC_PINCONF
226
227config PINCTRL_TZ1090_PDC
228 bool "Toumaz Xenif TZ1090 PDC pin control driver"
229 depends on SOC_TZ1090
230 select PINMUX
231 select PINCONF
232
195config PINCTRL_U300 233config PINCTRL_U300
196 bool "U300 pin controller driver" 234 bool "U300 pin controller driver"
197 depends on ARCH_U300 235 depends on ARCH_U300
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 76c937cbbb13..d64563bf6fb4 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,12 +16,14 @@ obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o 16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
17obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 17obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
18obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 18obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
19obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
19obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 20obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
20obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o 21obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
21obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o 22obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
22obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o 23obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
23obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 24obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
24obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o 25obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
26obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
25obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 27obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
26obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 28obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
27obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 29obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
@@ -30,13 +32,16 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
30obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o 32obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
31obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 33obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
32obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o 34obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
35obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
33obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 36obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
34obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 37obj-$(CONFIG_PINCTRL_SIRF) += sirf/
35obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o 38obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
36obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 39obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
37obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 40obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
38obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 41obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
39obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o 42obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
43obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
44obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
40obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 45obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
41obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 46obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
42obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o 47obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
@@ -47,6 +52,7 @@ obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
47obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 52obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
48obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 53obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
49obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 54obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
55obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
50 56
51obj-$(CONFIG_PLAT_ORION) += mvebu/ 57obj-$(CONFIG_PLAT_ORION) += mvebu/
52obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 58obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 5327f35d9b5c..5b272bfd261d 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -41,13 +41,13 @@
41static bool pinctrl_dummy_state; 41static bool pinctrl_dummy_state;
42 42
43/* Mutex taken to protect pinctrl_list */ 43/* Mutex taken to protect pinctrl_list */
44DEFINE_MUTEX(pinctrl_list_mutex); 44static DEFINE_MUTEX(pinctrl_list_mutex);
45 45
46/* Mutex taken to protect pinctrl_maps */ 46/* Mutex taken to protect pinctrl_maps */
47DEFINE_MUTEX(pinctrl_maps_mutex); 47DEFINE_MUTEX(pinctrl_maps_mutex);
48 48
49/* Mutex taken to protect pinctrldev_list */ 49/* Mutex taken to protect pinctrldev_list */
50DEFINE_MUTEX(pinctrldev_list_mutex); 50static DEFINE_MUTEX(pinctrldev_list_mutex);
51 51
52/* Global list of pin control devices (struct pinctrl_dev) */ 52/* Global list of pin control devices (struct pinctrl_dev) */
53static LIST_HEAD(pinctrldev_list); 53static LIST_HEAD(pinctrldev_list);
@@ -101,20 +101,23 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata);
101struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname) 101struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname)
102{ 102{
103 struct pinctrl_dev *pctldev = NULL; 103 struct pinctrl_dev *pctldev = NULL;
104 bool found = false;
105 104
106 if (!devname) 105 if (!devname)
107 return NULL; 106 return NULL;
108 107
108 mutex_lock(&pinctrldev_list_mutex);
109
109 list_for_each_entry(pctldev, &pinctrldev_list, node) { 110 list_for_each_entry(pctldev, &pinctrldev_list, node) {
110 if (!strcmp(dev_name(pctldev->dev), devname)) { 111 if (!strcmp(dev_name(pctldev->dev), devname)) {
111 /* Matched on device name */ 112 /* Matched on device name */
112 found = true; 113 mutex_unlock(&pinctrldev_list_mutex);
113 break; 114 return pctldev;
114 } 115 }
115 } 116 }
116 117
117 return found ? pctldev : NULL; 118 mutex_unlock(&pinctrldev_list_mutex);
119
120 return NULL;
118} 121}
119 122
120struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np) 123struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np)
@@ -280,6 +283,29 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
280} 283}
281 284
282/** 285/**
286 * gpio_to_pin() - GPIO range GPIO number to pin number translation
287 * @range: GPIO range used for the translation
288 * @gpio: gpio pin to translate to a pin number
289 *
290 * Finds the pin number for a given GPIO using the specified GPIO range
291 * as a base for translation. The distinction between linear GPIO ranges
292 * and pin list based GPIO ranges is managed correctly by this function.
293 *
294 * This function assumes the gpio is part of the specified GPIO range, use
295 * only after making sure this is the case (e.g. by calling it on the
296 * result of successful pinctrl_get_device_gpio_range calls)!
297 */
298static inline int gpio_to_pin(struct pinctrl_gpio_range *range,
299 unsigned int gpio)
300{
301 unsigned int offset = gpio - range->base;
302 if (range->pins)
303 return range->pins[offset];
304 else
305 return range->pin_base + offset;
306}
307
308/**
283 * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range 309 * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range
284 * @pctldev: pin controller device to check 310 * @pctldev: pin controller device to check
285 * @gpio: gpio pin to check taken from the global GPIO pin space 311 * @gpio: gpio pin to check taken from the global GPIO pin space
@@ -326,6 +352,8 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
326 struct pinctrl_gpio_range *range = NULL; 352 struct pinctrl_gpio_range *range = NULL;
327 struct gpio_chip *chip = gpio_to_chip(gpio); 353 struct gpio_chip *chip = gpio_to_chip(gpio);
328 354
355 mutex_lock(&pinctrldev_list_mutex);
356
329 /* Loop over the pin controllers */ 357 /* Loop over the pin controllers */
330 list_for_each_entry(pctldev, &pinctrldev_list, node) { 358 list_for_each_entry(pctldev, &pinctrldev_list, node) {
331 /* Loop over the ranges */ 359 /* Loop over the ranges */
@@ -334,9 +362,13 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
334 if (range->base + range->npins - 1 < chip->base || 362 if (range->base + range->npins - 1 < chip->base ||
335 range->base > chip->base + chip->ngpio - 1) 363 range->base > chip->base + chip->ngpio - 1)
336 continue; 364 continue;
365 mutex_unlock(&pinctrldev_list_mutex);
337 return true; 366 return true;
338 } 367 }
339 } 368 }
369
370 mutex_unlock(&pinctrldev_list_mutex);
371
340 return false; 372 return false;
341} 373}
342#else 374#else
@@ -408,8 +440,6 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
408{ 440{
409 struct pinctrl_dev *pctldev; 441 struct pinctrl_dev *pctldev;
410 442
411 mutex_lock(&pinctrldev_list_mutex);
412
413 pctldev = get_pinctrl_dev_from_devname(devname); 443 pctldev = get_pinctrl_dev_from_devname(devname);
414 444
415 /* 445 /*
@@ -418,13 +448,10 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
418 * range need to defer probing. 448 * range need to defer probing.
419 */ 449 */
420 if (!pctldev) { 450 if (!pctldev) {
421 mutex_unlock(&pinctrldev_list_mutex);
422 return ERR_PTR(-EPROBE_DEFER); 451 return ERR_PTR(-EPROBE_DEFER);
423 } 452 }
424 pinctrl_add_gpio_range(pctldev, range); 453 pinctrl_add_gpio_range(pctldev, range);
425 454
426 mutex_unlock(&pinctrldev_list_mutex);
427
428 return pctldev; 455 return pctldev;
429} 456}
430EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range); 457EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
@@ -438,21 +465,26 @@ struct pinctrl_gpio_range *
438pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev, 465pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
439 unsigned int pin) 466 unsigned int pin)
440{ 467{
441 struct pinctrl_gpio_range *range = NULL; 468 struct pinctrl_gpio_range *range;
442 469
443 mutex_lock(&pctldev->mutex); 470 mutex_lock(&pctldev->mutex);
444 /* Loop over the ranges */ 471 /* Loop over the ranges */
445 list_for_each_entry(range, &pctldev->gpio_ranges, node) { 472 list_for_each_entry(range, &pctldev->gpio_ranges, node) {
446 /* Check if we're in the valid range */ 473 /* Check if we're in the valid range */
447 if (pin >= range->pin_base && 474 if (range->pins) {
448 pin < range->pin_base + range->npins) { 475 int a;
449 mutex_unlock(&pctldev->mutex); 476 for (a = 0; a < range->npins; a++) {
450 return range; 477 if (range->pins[a] == pin)
451 } 478 goto out;
479 }
480 } else if (pin >= range->pin_base &&
481 pin < range->pin_base + range->npins)
482 goto out;
452 } 483 }
484 range = NULL;
485out:
453 mutex_unlock(&pctldev->mutex); 486 mutex_unlock(&pctldev->mutex);
454 487 return range;
455 return NULL;
456} 488}
457EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin); 489EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);
458 490
@@ -517,22 +549,18 @@ int pinctrl_request_gpio(unsigned gpio)
517 int ret; 549 int ret;
518 int pin; 550 int pin;
519 551
520 mutex_lock(&pinctrldev_list_mutex);
521
522 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 552 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
523 if (ret) { 553 if (ret) {
524 if (pinctrl_ready_for_gpio_range(gpio)) 554 if (pinctrl_ready_for_gpio_range(gpio))
525 ret = 0; 555 ret = 0;
526 mutex_unlock(&pinctrldev_list_mutex);
527 return ret; 556 return ret;
528 } 557 }
529 558
530 /* Convert to the pin controllers number space */ 559 /* Convert to the pin controllers number space */
531 pin = gpio - range->base + range->pin_base; 560 pin = gpio_to_pin(range, gpio);
532 561
533 ret = pinmux_request_gpio(pctldev, range, pin, gpio); 562 ret = pinmux_request_gpio(pctldev, range, pin, gpio);
534 563
535 mutex_unlock(&pinctrldev_list_mutex);
536 return ret; 564 return ret;
537} 565}
538EXPORT_SYMBOL_GPL(pinctrl_request_gpio); 566EXPORT_SYMBOL_GPL(pinctrl_request_gpio);
@@ -552,22 +580,18 @@ void pinctrl_free_gpio(unsigned gpio)
552 int ret; 580 int ret;
553 int pin; 581 int pin;
554 582
555 mutex_lock(&pinctrldev_list_mutex);
556
557 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 583 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
558 if (ret) { 584 if (ret) {
559 mutex_unlock(&pinctrldev_list_mutex);
560 return; 585 return;
561 } 586 }
562 mutex_lock(&pctldev->mutex); 587 mutex_lock(&pctldev->mutex);
563 588
564 /* Convert to the pin controllers number space */ 589 /* Convert to the pin controllers number space */
565 pin = gpio - range->base + range->pin_base; 590 pin = gpio_to_pin(range, gpio);
566 591
567 pinmux_free_gpio(pctldev, pin, range); 592 pinmux_free_gpio(pctldev, pin, range);
568 593
569 mutex_unlock(&pctldev->mutex); 594 mutex_unlock(&pctldev->mutex);
570 mutex_unlock(&pinctrldev_list_mutex);
571} 595}
572EXPORT_SYMBOL_GPL(pinctrl_free_gpio); 596EXPORT_SYMBOL_GPL(pinctrl_free_gpio);
573 597
@@ -578,22 +602,18 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input)
578 int ret; 602 int ret;
579 int pin; 603 int pin;
580 604
581 mutex_lock(&pinctrldev_list_mutex);
582
583 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 605 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
584 if (ret) { 606 if (ret) {
585 mutex_unlock(&pinctrldev_list_mutex);
586 return ret; 607 return ret;
587 } 608 }
588 609
589 mutex_lock(&pctldev->mutex); 610 mutex_lock(&pctldev->mutex);
590 611
591 /* Convert to the pin controllers number space */ 612 /* Convert to the pin controllers number space */
592 pin = gpio - range->base + range->pin_base; 613 pin = gpio_to_pin(range, gpio);
593 ret = pinmux_gpio_direction(pctldev, range, pin, input); 614 ret = pinmux_gpio_direction(pctldev, range, pin, input);
594 615
595 mutex_unlock(&pctldev->mutex); 616 mutex_unlock(&pctldev->mutex);
596 mutex_unlock(&pinctrldev_list_mutex);
597 617
598 return ret; 618 return ret;
599} 619}
@@ -1204,6 +1224,69 @@ int pinctrl_force_default(struct pinctrl_dev *pctldev)
1204} 1224}
1205EXPORT_SYMBOL_GPL(pinctrl_force_default); 1225EXPORT_SYMBOL_GPL(pinctrl_force_default);
1206 1226
1227#ifdef CONFIG_PM
1228
1229/**
1230 * pinctrl_pm_select_default_state() - select default pinctrl state for PM
1231 * @dev: device to select default state for
1232 */
1233int pinctrl_pm_select_default_state(struct device *dev)
1234{
1235 struct dev_pin_info *pins = dev->pins;
1236 int ret;
1237
1238 if (!pins)
1239 return 0;
1240 if (IS_ERR(pins->default_state))
1241 return 0; /* No default state */
1242 ret = pinctrl_select_state(pins->p, pins->default_state);
1243 if (ret)
1244 dev_err(dev, "failed to activate default pinctrl state\n");
1245 return ret;
1246}
1247EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state);
1248
1249/**
1250 * pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM
1251 * @dev: device to select sleep state for
1252 */
1253int pinctrl_pm_select_sleep_state(struct device *dev)
1254{
1255 struct dev_pin_info *pins = dev->pins;
1256 int ret;
1257
1258 if (!pins)
1259 return 0;
1260 if (IS_ERR(pins->sleep_state))
1261 return 0; /* No sleep state */
1262 ret = pinctrl_select_state(pins->p, pins->sleep_state);
1263 if (ret)
1264 dev_err(dev, "failed to activate pinctrl sleep state\n");
1265 return ret;
1266}
1267EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state);
1268
1269/**
1270 * pinctrl_pm_select_idle_state() - select idle pinctrl state for PM
1271 * @dev: device to select idle state for
1272 */
1273int pinctrl_pm_select_idle_state(struct device *dev)
1274{
1275 struct dev_pin_info *pins = dev->pins;
1276 int ret;
1277
1278 if (!pins)
1279 return 0;
1280 if (IS_ERR(pins->idle_state))
1281 return 0; /* No idle state */
1282 ret = pinctrl_select_state(pins->p, pins->idle_state);
1283 if (ret)
1284 dev_err(dev, "failed to activate pinctrl idle state\n");
1285 return ret;
1286}
1287EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state);
1288#endif
1289
1207#ifdef CONFIG_DEBUG_FS 1290#ifdef CONFIG_DEBUG_FS
1208 1291
1209static int pinctrl_pins_show(struct seq_file *s, void *what) 1292static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -1296,11 +1379,21 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
1296 1379
1297 /* Loop over the ranges */ 1380 /* Loop over the ranges */
1298 list_for_each_entry(range, &pctldev->gpio_ranges, node) { 1381 list_for_each_entry(range, &pctldev->gpio_ranges, node) {
1299 seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n", 1382 if (range->pins) {
1300 range->id, range->name, 1383 int a;
1301 range->base, (range->base + range->npins - 1), 1384 seq_printf(s, "%u: %s GPIOS [%u - %u] PINS {",
1302 range->pin_base, 1385 range->id, range->name,
1303 (range->pin_base + range->npins - 1)); 1386 range->base, (range->base + range->npins - 1));
1387 for (a = 0; a < range->npins - 1; a++)
1388 seq_printf(s, "%u, ", range->pins[a]);
1389 seq_printf(s, "%u}\n", range->pins[a]);
1390 }
1391 else
1392 seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n",
1393 range->id, range->name,
1394 range->base, (range->base + range->npins - 1),
1395 range->pin_base,
1396 (range->pin_base + range->npins - 1));
1304 } 1397 }
1305 1398
1306 mutex_unlock(&pctldev->mutex); 1399 mutex_unlock(&pctldev->mutex);
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 428ea96a94d3..048ae80adabd 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -26,6 +26,9 @@
26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
28#define DOVE_AU0_AC97_SEL BIT(16) 28#define DOVE_AU0_AC97_SEL BIT(16)
29#define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C)
30#define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030)
31#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
29#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 32#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
30#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 33#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
31#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 34#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
@@ -58,12 +61,16 @@ static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
58 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 61 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
59 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 62 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
60 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 63 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
61 unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); 64 unsigned long func;
62 65
63 if (pmu & (1 << ctrl->pid)) 66 if (pmu & (1 << ctrl->pid)) {
64 *config = CONFIG_PMU; 67 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
65 else 68 *config = (func >> shift) & MPP_MASK;
66 *config = (mpp >> shift) & MPP_MASK; 69 *config |= CONFIG_PMU;
70 } else {
71 func = readl(DOVE_MPP_VIRT_BASE + off);
72 *config = (func >> shift) & MPP_MASK;
73 }
67 return 0; 74 return 0;
68} 75}
69 76
@@ -73,15 +80,20 @@ static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
73 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 80 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
74 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 81 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
75 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 82 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
76 unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off); 83 unsigned long func;
77 84
78 if (config == CONFIG_PMU) 85 if (config & CONFIG_PMU) {
79 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 86 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
80 else { 87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
88 func &= ~(MPP_MASK << shift);
89 func |= (config & MPP_MASK) << shift;
90 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
91 } else {
81 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 92 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
82 mpp &= ~(MPP_MASK << shift); 93 func = readl(DOVE_MPP_VIRT_BASE + off);
83 mpp |= config << shift; 94 func &= ~(MPP_MASK << shift);
84 writel(mpp, DOVE_MPP_VIRT_BASE + off); 95 func |= (config & MPP_MASK) << shift;
96 writel(func, DOVE_MPP_VIRT_BASE + off);
85 } 97 }
86 return 0; 98 return 0;
87} 99}
@@ -378,20 +390,53 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
378 MPP_FUNCTION(0x02, "uart2", "rts"), 390 MPP_FUNCTION(0x02, "uart2", "rts"),
379 MPP_FUNCTION(0x03, "sdio0", "cd"), 391 MPP_FUNCTION(0x03, "sdio0", "cd"),
380 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 392 MPP_FUNCTION(0x0f, "lcd0", "pwm"),
381 MPP_FUNCTION(0x10, "pmu", NULL)), 393 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
394 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
395 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
396 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
397 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
398 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
399 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
400 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
401 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
402 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
403 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
404 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
382 MPP_MODE(1, 405 MPP_MODE(1,
383 MPP_FUNCTION(0x00, "gpio", NULL), 406 MPP_FUNCTION(0x00, "gpio", NULL),
384 MPP_FUNCTION(0x02, "uart2", "cts"), 407 MPP_FUNCTION(0x02, "uart2", "cts"),
385 MPP_FUNCTION(0x03, "sdio0", "wp"), 408 MPP_FUNCTION(0x03, "sdio0", "wp"),
386 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 409 MPP_FUNCTION(0x0f, "lcd1", "pwm"),
387 MPP_FUNCTION(0x10, "pmu", NULL)), 410 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
411 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
412 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
413 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
414 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
415 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
416 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
417 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
418 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
419 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
420 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
421 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
388 MPP_MODE(2, 422 MPP_MODE(2,
389 MPP_FUNCTION(0x00, "gpio", NULL), 423 MPP_FUNCTION(0x00, "gpio", NULL),
390 MPP_FUNCTION(0x01, "sata", "prsnt"), 424 MPP_FUNCTION(0x01, "sata", "prsnt"),
391 MPP_FUNCTION(0x02, "uart2", "txd"), 425 MPP_FUNCTION(0x02, "uart2", "txd"),
392 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 426 MPP_FUNCTION(0x03, "sdio0", "buspwr"),
393 MPP_FUNCTION(0x04, "uart1", "rts"), 427 MPP_FUNCTION(0x04, "uart1", "rts"),
394 MPP_FUNCTION(0x10, "pmu", NULL)), 428 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
429 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
430 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
431 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
432 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
433 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
434 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
435 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
436 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
437 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
438 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
439 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
395 MPP_MODE(3, 440 MPP_MODE(3,
396 MPP_FUNCTION(0x00, "gpio", NULL), 441 MPP_FUNCTION(0x00, "gpio", NULL),
397 MPP_FUNCTION(0x01, "sata", "act"), 442 MPP_FUNCTION(0x01, "sata", "act"),
@@ -399,43 +444,131 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
399 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 444 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
400 MPP_FUNCTION(0x04, "uart1", "cts"), 445 MPP_FUNCTION(0x04, "uart1", "cts"),
401 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 446 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
402 MPP_FUNCTION(0x10, "pmu", NULL)), 447 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
448 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
449 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
450 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
451 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
452 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
453 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
454 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
455 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
456 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
457 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
458 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
403 MPP_MODE(4, 459 MPP_MODE(4,
404 MPP_FUNCTION(0x00, "gpio", NULL), 460 MPP_FUNCTION(0x00, "gpio", NULL),
405 MPP_FUNCTION(0x02, "uart3", "rts"), 461 MPP_FUNCTION(0x02, "uart3", "rts"),
406 MPP_FUNCTION(0x03, "sdio1", "cd"), 462 MPP_FUNCTION(0x03, "sdio1", "cd"),
407 MPP_FUNCTION(0x04, "spi1", "miso"), 463 MPP_FUNCTION(0x04, "spi1", "miso"),
408 MPP_FUNCTION(0x10, "pmu", NULL)), 464 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
465 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
466 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
467 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
468 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
469 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
470 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
471 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
472 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
473 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
474 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
475 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
409 MPP_MODE(5, 476 MPP_MODE(5,
410 MPP_FUNCTION(0x00, "gpio", NULL), 477 MPP_FUNCTION(0x00, "gpio", NULL),
411 MPP_FUNCTION(0x02, "uart3", "cts"), 478 MPP_FUNCTION(0x02, "uart3", "cts"),
412 MPP_FUNCTION(0x03, "sdio1", "wp"), 479 MPP_FUNCTION(0x03, "sdio1", "wp"),
413 MPP_FUNCTION(0x04, "spi1", "cs"), 480 MPP_FUNCTION(0x04, "spi1", "cs"),
414 MPP_FUNCTION(0x10, "pmu", NULL)), 481 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
482 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
483 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
484 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
485 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
486 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
487 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
488 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
489 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
490 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
491 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
492 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
415 MPP_MODE(6, 493 MPP_MODE(6,
416 MPP_FUNCTION(0x00, "gpio", NULL), 494 MPP_FUNCTION(0x00, "gpio", NULL),
417 MPP_FUNCTION(0x02, "uart3", "txd"), 495 MPP_FUNCTION(0x02, "uart3", "txd"),
418 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 496 MPP_FUNCTION(0x03, "sdio1", "buspwr"),
419 MPP_FUNCTION(0x04, "spi1", "mosi"), 497 MPP_FUNCTION(0x04, "spi1", "mosi"),
420 MPP_FUNCTION(0x10, "pmu", NULL)), 498 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
499 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
500 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
501 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
502 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
503 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
504 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
505 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
506 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
507 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
508 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
509 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
421 MPP_MODE(7, 510 MPP_MODE(7,
422 MPP_FUNCTION(0x00, "gpio", NULL), 511 MPP_FUNCTION(0x00, "gpio", NULL),
423 MPP_FUNCTION(0x02, "uart3", "rxd"), 512 MPP_FUNCTION(0x02, "uart3", "rxd"),
424 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 513 MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
425 MPP_FUNCTION(0x04, "spi1", "sck"), 514 MPP_FUNCTION(0x04, "spi1", "sck"),
426 MPP_FUNCTION(0x10, "pmu", NULL)), 515 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
516 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
517 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
518 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
519 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
520 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
521 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
522 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
523 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
524 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
525 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
526 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
427 MPP_MODE(8, 527 MPP_MODE(8,
428 MPP_FUNCTION(0x00, "gpio", NULL), 528 MPP_FUNCTION(0x00, "gpio", NULL),
429 MPP_FUNCTION(0x01, "watchdog", "rstout"), 529 MPP_FUNCTION(0x01, "watchdog", "rstout"),
430 MPP_FUNCTION(0x10, "pmu", NULL)), 530 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
531 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
532 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
533 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
534 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
535 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
536 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
537 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
538 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
539 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
540 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
541 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
431 MPP_MODE(9, 542 MPP_MODE(9,
432 MPP_FUNCTION(0x00, "gpio", NULL), 543 MPP_FUNCTION(0x00, "gpio", NULL),
433 MPP_FUNCTION(0x05, "pex1", "clkreq"), 544 MPP_FUNCTION(0x05, "pex1", "clkreq"),
434 MPP_FUNCTION(0x10, "pmu", NULL)), 545 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
546 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
547 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
548 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
549 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
550 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
551 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
552 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
553 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
554 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
555 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
556 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
435 MPP_MODE(10, 557 MPP_MODE(10,
436 MPP_FUNCTION(0x00, "gpio", NULL), 558 MPP_FUNCTION(0x00, "gpio", NULL),
437 MPP_FUNCTION(0x05, "ssp", "sclk"), 559 MPP_FUNCTION(0x05, "ssp", "sclk"),
438 MPP_FUNCTION(0x10, "pmu", NULL)), 560 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
561 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
562 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
563 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
564 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
565 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
566 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
567 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
568 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
569 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
570 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
571 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
439 MPP_MODE(11, 572 MPP_MODE(11,
440 MPP_FUNCTION(0x00, "gpio", NULL), 573 MPP_FUNCTION(0x00, "gpio", NULL),
441 MPP_FUNCTION(0x01, "sata", "prsnt"), 574 MPP_FUNCTION(0x01, "sata", "prsnt"),
@@ -443,33 +576,88 @@ static struct mvebu_mpp_mode dove_mpp_modes[] = {
443 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 576 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
444 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 577 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
445 MPP_FUNCTION(0x05, "pex0", "clkreq"), 578 MPP_FUNCTION(0x05, "pex0", "clkreq"),
446 MPP_FUNCTION(0x10, "pmu", NULL)), 579 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
580 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
581 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
582 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
583 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
584 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
585 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
586 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
587 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
588 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
589 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
590 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
447 MPP_MODE(12, 591 MPP_MODE(12,
448 MPP_FUNCTION(0x00, "gpio", NULL), 592 MPP_FUNCTION(0x00, "gpio", NULL),
449 MPP_FUNCTION(0x01, "sata", "act"), 593 MPP_FUNCTION(0x01, "sata", "act"),
450 MPP_FUNCTION(0x02, "uart2", "rts"), 594 MPP_FUNCTION(0x02, "uart2", "rts"),
451 MPP_FUNCTION(0x03, "audio0", "extclk"), 595 MPP_FUNCTION(0x03, "audio0", "extclk"),
452 MPP_FUNCTION(0x04, "sdio1", "cd"), 596 MPP_FUNCTION(0x04, "sdio1", "cd"),
453 MPP_FUNCTION(0x10, "pmu", NULL)), 597 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
598 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
599 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
600 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
601 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
602 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
603 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
604 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
605 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
606 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
607 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
608 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
454 MPP_MODE(13, 609 MPP_MODE(13,
455 MPP_FUNCTION(0x00, "gpio", NULL), 610 MPP_FUNCTION(0x00, "gpio", NULL),
456 MPP_FUNCTION(0x02, "uart2", "cts"), 611 MPP_FUNCTION(0x02, "uart2", "cts"),
457 MPP_FUNCTION(0x03, "audio1", "extclk"), 612 MPP_FUNCTION(0x03, "audio1", "extclk"),
458 MPP_FUNCTION(0x04, "sdio1", "wp"), 613 MPP_FUNCTION(0x04, "sdio1", "wp"),
459 MPP_FUNCTION(0x05, "ssp", "extclk"), 614 MPP_FUNCTION(0x05, "ssp", "extclk"),
460 MPP_FUNCTION(0x10, "pmu", NULL)), 615 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
616 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
617 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
618 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
619 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
620 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
621 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
622 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
623 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
624 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
625 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
626 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
461 MPP_MODE(14, 627 MPP_MODE(14,
462 MPP_FUNCTION(0x00, "gpio", NULL), 628 MPP_FUNCTION(0x00, "gpio", NULL),
463 MPP_FUNCTION(0x02, "uart2", "txd"), 629 MPP_FUNCTION(0x02, "uart2", "txd"),
464 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 630 MPP_FUNCTION(0x04, "sdio1", "buspwr"),
465 MPP_FUNCTION(0x05, "ssp", "rxd"), 631 MPP_FUNCTION(0x05, "ssp", "rxd"),
466 MPP_FUNCTION(0x10, "pmu", NULL)), 632 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
633 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
634 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
635 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
636 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
637 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
638 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
639 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
640 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
641 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
642 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
643 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
467 MPP_MODE(15, 644 MPP_MODE(15,
468 MPP_FUNCTION(0x00, "gpio", NULL), 645 MPP_FUNCTION(0x00, "gpio", NULL),
469 MPP_FUNCTION(0x02, "uart2", "rxd"), 646 MPP_FUNCTION(0x02, "uart2", "rxd"),
470 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 647 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
471 MPP_FUNCTION(0x05, "ssp", "sfrm"), 648 MPP_FUNCTION(0x05, "ssp", "sfrm"),
472 MPP_FUNCTION(0x10, "pmu", NULL)), 649 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
650 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
651 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
652 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
653 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
654 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
655 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
656 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
657 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
658 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
659 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
660 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
473 MPP_MODE(16, 661 MPP_MODE(16,
474 MPP_FUNCTION(0x00, "gpio", NULL), 662 MPP_FUNCTION(0x00, "gpio", NULL),
475 MPP_FUNCTION(0x02, "uart3", "rts"), 663 MPP_FUNCTION(0x02, "uart3", "rts"),
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 2ad5a8d337b5..8594f033ac21 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -21,6 +21,7 @@
21#include <linux/pinctrl/pinctrl.h> 21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinconf.h> 22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinconf-generic.h>
24#include <linux/of.h>
24#include "core.h" 25#include "core.h"
25#include "pinconf.h" 26#include "pinconf.h"
26 27
@@ -37,14 +38,18 @@ struct pin_config_item {
37static struct pin_config_item conf_items[] = { 38static struct pin_config_item conf_items[] = {
38 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL), 39 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL),
39 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL), 40 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL),
41 PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL),
40 PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL), 42 PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL),
41 PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL), 43 PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL),
44 PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
45 "input bias pull to pin specific state", NULL),
42 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), 46 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
43 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), 47 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
44 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), 48 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
49 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"),
45 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL), 50 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL),
46 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), 51 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
47 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"), 52 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"),
48 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"), 53 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
49 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL), 54 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL),
50 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"), 55 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
@@ -135,3 +140,100 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
135} 140}
136EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); 141EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
137#endif 142#endif
143
144#ifdef CONFIG_OF
145struct pinconf_generic_dt_params {
146 const char * const property;
147 enum pin_config_param param;
148 u32 default_value;
149};
150
151static struct pinconf_generic_dt_params dt_params[] = {
152 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
153 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
154 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
155 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
156 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
157 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
158 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
159 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
160 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
161 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
162 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
163 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
164 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
165 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
166 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
167 { "output-low", PIN_CONFIG_OUTPUT, 0, },
168 { "output-high", PIN_CONFIG_OUTPUT, 1, },
169};
170
171/**
172 * pinconf_generic_parse_dt_config()
173 * parse the config properties into generic pinconfig values.
174 * @np: node containing the pinconfig properties
175 * @configs: array with nconfigs entries containing the generic pinconf values
176 * @nconfigs: umber of configurations
177 */
178int pinconf_generic_parse_dt_config(struct device_node *np,
179 unsigned long **configs,
180 unsigned int *nconfigs)
181{
182 unsigned long *cfg;
183 unsigned int ncfg = 0;
184 int ret;
185 int i;
186 u32 val;
187
188 if (!np)
189 return -EINVAL;
190
191 /* allocate a temporary array big enough to hold one of each option */
192 cfg = kzalloc(sizeof(*cfg) * ARRAY_SIZE(dt_params), GFP_KERNEL);
193 if (!cfg)
194 return -ENOMEM;
195
196 for (i = 0; i < ARRAY_SIZE(dt_params); i++) {
197 struct pinconf_generic_dt_params *par = &dt_params[i];
198 ret = of_property_read_u32(np, par->property, &val);
199
200 /* property not found */
201 if (ret == -EINVAL)
202 continue;
203
204 /* use default value, when no value is specified */
205 if (ret)
206 val = par->default_value;
207
208 pr_debug("found %s with value %u\n", par->property, val);
209 cfg[ncfg] = pinconf_to_config_packed(par->param, val);
210 ncfg++;
211 }
212
213 ret = 0;
214
215 /* no configs found at all */
216 if (ncfg == 0) {
217 *configs = NULL;
218 *nconfigs = 0;
219 goto out;
220 }
221
222 /*
223 * Now limit the number of configs to the real number of
224 * found properties.
225 */
226 *configs = kzalloc(ncfg * sizeof(unsigned long), GFP_KERNEL);
227 if (!*configs) {
228 ret = -ENOMEM;
229 goto out;
230 }
231
232 memcpy(*configs, cfg, ncfg * sizeof(unsigned long));
233 *nconfigs = ncfg;
234
235out:
236 kfree(cfg);
237 return ret;
238}
239#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 694c3ace4520..e875f21a5908 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -75,98 +75,6 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
75 return ops->pin_config_get(pctldev, pin, config); 75 return ops->pin_config_get(pctldev, pin, config);
76} 76}
77 77
78/**
79 * pin_config_get() - get the configuration of a single pin parameter
80 * @dev_name: name of the pin controller device for this pin
81 * @name: name of the pin to get the config for
82 * @config: the config pointed to by this argument will be filled in with the
83 * current pin state, it can be used directly by drivers as a numeral, or
84 * it can be dereferenced to any struct.
85 */
86int pin_config_get(const char *dev_name, const char *name,
87 unsigned long *config)
88{
89 struct pinctrl_dev *pctldev;
90 int pin;
91
92 pctldev = get_pinctrl_dev_from_devname(dev_name);
93 if (!pctldev) {
94 pin = -EINVAL;
95 return pin;
96 }
97
98 mutex_lock(&pctldev->mutex);
99
100 pin = pin_get_from_name(pctldev, name);
101 if (pin < 0)
102 goto unlock;
103
104 pin = pin_config_get_for_pin(pctldev, pin, config);
105
106unlock:
107 mutex_unlock(&pctldev->mutex);
108 return pin;
109}
110EXPORT_SYMBOL(pin_config_get);
111
112static int pin_config_set_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
113 unsigned long config)
114{
115 const struct pinconf_ops *ops = pctldev->desc->confops;
116 int ret;
117
118 if (!ops || !ops->pin_config_set) {
119 dev_err(pctldev->dev, "cannot configure pin, missing "
120 "config function in driver\n");
121 return -EINVAL;
122 }
123
124 ret = ops->pin_config_set(pctldev, pin, config);
125 if (ret) {
126 dev_err(pctldev->dev,
127 "unable to set pin configuration on pin %d\n", pin);
128 return ret;
129 }
130
131 return 0;
132}
133
134/**
135 * pin_config_set() - set the configuration of a single pin parameter
136 * @dev_name: name of pin controller device for this pin
137 * @name: name of the pin to set the config for
138 * @config: the config in this argument will contain the desired pin state, it
139 * can be used directly by drivers as a numeral, or it can be dereferenced
140 * to any struct.
141 */
142int pin_config_set(const char *dev_name, const char *name,
143 unsigned long config)
144{
145 struct pinctrl_dev *pctldev;
146 int pin, ret;
147
148 pctldev = get_pinctrl_dev_from_devname(dev_name);
149 if (!pctldev) {
150 ret = -EINVAL;
151 return ret;
152 }
153
154 mutex_lock(&pctldev->mutex);
155
156 pin = pin_get_from_name(pctldev, name);
157 if (pin < 0) {
158 ret = pin;
159 goto unlock;
160 }
161
162 ret = pin_config_set_for_pin(pctldev, pin, config);
163
164unlock:
165 mutex_unlock(&pctldev->mutex);
166 return ret;
167}
168EXPORT_SYMBOL(pin_config_set);
169
170int pin_config_group_get(const char *dev_name, const char *pin_group, 78int pin_config_group_get(const char *dev_name, const char *pin_group,
171 unsigned long *config) 79 unsigned long *config)
172{ 80{
@@ -204,88 +112,6 @@ unlock:
204 mutex_unlock(&pctldev->mutex); 112 mutex_unlock(&pctldev->mutex);
205 return ret; 113 return ret;
206} 114}
207EXPORT_SYMBOL(pin_config_group_get);
208
209int pin_config_group_set(const char *dev_name, const char *pin_group,
210 unsigned long config)
211{
212 struct pinctrl_dev *pctldev;
213 const struct pinconf_ops *ops;
214 const struct pinctrl_ops *pctlops;
215 int selector;
216 const unsigned *pins;
217 unsigned num_pins;
218 int ret;
219 int i;
220
221 pctldev = get_pinctrl_dev_from_devname(dev_name);
222 if (!pctldev) {
223 ret = -EINVAL;
224 return ret;
225 }
226
227 mutex_lock(&pctldev->mutex);
228
229 ops = pctldev->desc->confops;
230 pctlops = pctldev->desc->pctlops;
231
232 if (!ops || (!ops->pin_config_group_set && !ops->pin_config_set)) {
233 dev_err(pctldev->dev, "cannot configure pin group, missing "
234 "config function in driver\n");
235 ret = -EINVAL;
236 goto unlock;
237 }
238
239 selector = pinctrl_get_group_selector(pctldev, pin_group);
240 if (selector < 0) {
241 ret = selector;
242 goto unlock;
243 }
244
245 ret = pctlops->get_group_pins(pctldev, selector, &pins, &num_pins);
246 if (ret) {
247 dev_err(pctldev->dev, "cannot configure pin group, error "
248 "getting pins\n");
249 goto unlock;
250 }
251
252 /*
253 * If the pin controller supports handling entire groups we use that
254 * capability.
255 */
256 if (ops->pin_config_group_set) {
257 ret = ops->pin_config_group_set(pctldev, selector, config);
258 /*
259 * If the pin controller prefer that a certain group be handled
260 * pin-by-pin as well, it returns -EAGAIN.
261 */
262 if (ret != -EAGAIN)
263 goto unlock;
264 }
265
266 /*
267 * If the controller cannot handle entire groups, we configure each pin
268 * individually.
269 */
270 if (!ops->pin_config_set) {
271 ret = 0;
272 goto unlock;
273 }
274
275 for (i = 0; i < num_pins; i++) {
276 ret = ops->pin_config_set(pctldev, pins[i], config);
277 if (ret < 0)
278 goto unlock;
279 }
280
281 ret = 0;
282
283unlock:
284 mutex_unlock(&pctldev->mutex);
285
286 return ret;
287}
288EXPORT_SYMBOL(pin_config_group_set);
289 115
290int pinconf_map_to_setting(struct pinctrl_map const *map, 116int pinconf_map_to_setting(struct pinctrl_map const *map,
291 struct pinctrl_setting *setting) 117 struct pinctrl_setting *setting)
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 92c7267244d2..a4a5417e1413 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -123,3 +123,9 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
123 return; 123 return;
124} 124}
125#endif 125#endif
126
127#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF)
128int pinconf_generic_parse_dt_config(struct device_node *np,
129 unsigned long **configs,
130 unsigned int *nconfigs);
131#endif
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 6d4532702f80..1d3f988c2c8b 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -30,8 +30,11 @@
30#include <linux/pinctrl/pinmux.h> 30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf.h> 31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinconf-generic.h> 32#include <linux/pinctrl/pinconf-generic.h>
33#include <linux/pinctrl/machine.h>
33 34
34#include "pinctrl-abx500.h" 35#include "pinctrl-abx500.h"
36#include "core.h"
37#include "pinconf.h"
35 38
36/* 39/*
37 * The AB9540 and AB8540 GPIO support are extended versions 40 * The AB9540 and AB8540 GPIO support are extended versions
@@ -93,13 +96,15 @@
93#define AB8540_GPIOX_VBAT_START 51 96#define AB8540_GPIOX_VBAT_START 51
94#define AB8540_GPIOX_VBAT_END 54 97#define AB8540_GPIOX_VBAT_END 54
95 98
99#define ABX500_GPIO_INPUT 0
100#define ABX500_GPIO_OUTPUT 1
101
96struct abx500_pinctrl { 102struct abx500_pinctrl {
97 struct device *dev; 103 struct device *dev;
98 struct pinctrl_dev *pctldev; 104 struct pinctrl_dev *pctldev;
99 struct abx500_pinctrl_soc_data *soc; 105 struct abx500_pinctrl_soc_data *soc;
100 struct gpio_chip chip; 106 struct gpio_chip chip;
101 struct ab8500 *parent; 107 struct ab8500 *parent;
102 struct mutex lock;
103 struct abx500_gpio_irq_cluster *irq_cluster; 108 struct abx500_gpio_irq_cluster *irq_cluster;
104 int irq_cluster_size; 109 int irq_cluster_size;
105}; 110};
@@ -129,8 +134,8 @@ static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
129 134
130 if (ret < 0) 135 if (ret < 0)
131 dev_err(pct->dev, 136 dev_err(pct->dev,
132 "%s read reg =%x, offset=%x failed\n", 137 "%s read reg =%x, offset=%x failed (%d)\n",
133 __func__, reg, offset); 138 __func__, reg, offset, ret);
134 139
135 return ret; 140 return ret;
136} 141}
@@ -146,7 +151,8 @@ static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
146 ret = abx500_mask_and_set_register_interruptible(pct->dev, 151 ret = abx500_mask_and_set_register_interruptible(pct->dev,
147 AB8500_MISC, reg, BIT(pos), val << pos); 152 AB8500_MISC, reg, BIT(pos), val << pos);
148 if (ret < 0) 153 if (ret < 0)
149 dev_err(pct->dev, "%s write failed\n", __func__); 154 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
155 __func__, reg, offset, ret);
150 156
151 return ret; 157 return ret;
152} 158}
@@ -160,12 +166,24 @@ static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
160{ 166{
161 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); 167 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
162 bool bit; 168 bool bit;
169 bool is_out;
170 u8 gpio_offset = offset - 1;
163 int ret; 171 int ret;
164 172
165 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, 173 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
166 offset, &bit); 174 gpio_offset, &is_out);
175 if (ret < 0)
176 goto out;
177
178 if (is_out)
179 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
180 gpio_offset, &bit);
181 else
182 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
183 gpio_offset, &bit);
184out:
167 if (ret < 0) { 185 if (ret < 0) {
168 dev_err(pct->dev, "%s failed\n", __func__); 186 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
169 return ret; 187 return ret;
170 } 188 }
171 189
@@ -179,13 +197,14 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
179 197
180 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); 198 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
181 if (ret < 0) 199 if (ret < 0)
182 dev_err(pct->dev, "%s write failed\n", __func__); 200 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
183} 201}
184 202
185static int abx500_config_pull_updown(struct abx500_pinctrl *pct, 203static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
186 int offset, enum abx500_gpio_pull_updown val) 204 enum abx500_gpio_pull_updown *pull_updown)
187{ 205{
188 u8 pos; 206 u8 pos;
207 u8 val;
189 int ret; 208 int ret;
190 struct pullud *pullud; 209 struct pullud *pullud;
191 210
@@ -204,7 +223,41 @@ static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
204 goto out; 223 goto out;
205 } 224 }
206 225
207 pos = offset << 1; 226 ret = abx500_get_register_interruptible(pct->dev,
227 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
228
229 pos = (offset - pullud->first_pin) << 1;
230 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
231
232out:
233 if (ret < 0)
234 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
235
236 return ret;
237}
238
239static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
240 int offset, enum abx500_gpio_pull_updown val)
241{
242 u8 pos;
243 int ret;
244 struct pullud *pullud;
245
246 if (!pct->soc->pullud) {
247 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
248 __func__);
249 ret = -EPERM;
250 goto out;
251 }
252
253 pullud = pct->soc->pullud;
254
255 if ((offset < pullud->first_pin)
256 || (offset > pullud->last_pin)) {
257 ret = -EINVAL;
258 goto out;
259 }
260 pos = (offset - pullud->first_pin) << 1;
208 261
209 ret = abx500_mask_and_set_register_interruptible(pct->dev, 262 ret = abx500_mask_and_set_register_interruptible(pct->dev,
210 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, 263 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
@@ -217,33 +270,51 @@ out:
217 return ret; 270 return ret;
218} 271}
219 272
273static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
274{
275 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
276 struct pullud *pullud = pct->soc->pullud;
277
278 return (pullud &&
279 gpio >= pullud->first_pin &&
280 gpio <= pullud->last_pin);
281}
282
220static int abx500_gpio_direction_output(struct gpio_chip *chip, 283static int abx500_gpio_direction_output(struct gpio_chip *chip,
221 unsigned offset, 284 unsigned offset,
222 int val) 285 int val)
223{ 286{
224 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); 287 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
225 struct pullud *pullud = pct->soc->pullud;
226 unsigned gpio; 288 unsigned gpio;
227 int ret; 289 int ret;
228 290
229 /* set direction as output */ 291 /* set direction as output */
230 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); 292 ret = abx500_gpio_set_bits(chip,
293 AB8500_GPIO_DIR1_REG,
294 offset,
295 ABX500_GPIO_OUTPUT);
231 if (ret < 0) 296 if (ret < 0)
232 return ret; 297 goto out;
233 298
234 /* disable pull down */ 299 /* disable pull down */
235 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); 300 ret = abx500_gpio_set_bits(chip,
301 AB8500_GPIO_PUD1_REG,
302 offset,
303 ABX500_GPIO_PULL_NONE);
236 if (ret < 0) 304 if (ret < 0)
237 return ret; 305 goto out;
238 306
239 /* if supported, disable both pull down and pull up */ 307 /* if supported, disable both pull down and pull up */
240 gpio = offset + 1; 308 gpio = offset + 1;
241 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { 309 if (abx500_pullud_supported(chip, gpio)) {
242 ret = abx500_config_pull_updown(pct, 310 ret = abx500_set_pull_updown(pct,
243 gpio, 311 gpio,
244 ABX500_GPIO_PULL_NONE); 312 ABX500_GPIO_PULL_NONE);
245 if (ret < 0) 313 }
246 return ret; 314out:
315 if (ret < 0) {
316 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
317 return ret;
247 } 318 }
248 319
249 /* set the output as 1 or 0 */ 320 /* set the output as 1 or 0 */
@@ -253,7 +324,10 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip,
253static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 324static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
254{ 325{
255 /* set the register as input */ 326 /* set the register as input */
256 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); 327 return abx500_gpio_set_bits(chip,
328 AB8500_GPIO_DIR1_REG,
329 offset,
330 ABX500_GPIO_INPUT);
257} 331}
258 332
259static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 333static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
@@ -338,10 +412,16 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
338 if (af.alt_bit1 != UNUSED) { 412 if (af.alt_bit1 != UNUSED) {
339 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 413 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
340 offset, 0); 414 offset, 0);
415 if (ret < 0)
416 goto out;
417
341 ret = abx500_gpio_set_bits(chip, 418 ret = abx500_gpio_set_bits(chip,
342 AB8500_GPIO_ALTFUN_REG, 419 AB8500_GPIO_ALTFUN_REG,
343 af.alt_bit1, 420 af.alt_bit1,
344 !!(af.alta_val && BIT(0))); 421 !!(af.alta_val && BIT(0)));
422 if (ret < 0)
423 goto out;
424
345 if (af.alt_bit2 != UNUSED) 425 if (af.alt_bit2 != UNUSED)
346 ret = abx500_gpio_set_bits(chip, 426 ret = abx500_gpio_set_bits(chip,
347 AB8500_GPIO_ALTFUN_REG, 427 AB8500_GPIO_ALTFUN_REG,
@@ -355,8 +435,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
355 case ABX500_ALT_B: 435 case ABX500_ALT_B:
356 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 436 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
357 offset, 0); 437 offset, 0);
438 if (ret < 0)
439 goto out;
440
358 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 441 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
359 af.alt_bit1, !!(af.altb_val && BIT(0))); 442 af.alt_bit1, !!(af.altb_val && BIT(0)));
443 if (ret < 0)
444 goto out;
445
360 if (af.alt_bit2 != UNUSED) 446 if (af.alt_bit2 != UNUSED)
361 ret = abx500_gpio_set_bits(chip, 447 ret = abx500_gpio_set_bits(chip,
362 AB8500_GPIO_ALTFUN_REG, 448 AB8500_GPIO_ALTFUN_REG,
@@ -367,8 +453,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
367 case ABX500_ALT_C: 453 case ABX500_ALT_C:
368 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 454 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
369 offset, 0); 455 offset, 0);
456 if (ret < 0)
457 goto out;
458
370 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 459 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
371 af.alt_bit2, !!(af.altc_val && BIT(0))); 460 af.alt_bit2, !!(af.altc_val && BIT(0)));
461 if (ret < 0)
462 goto out;
463
372 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 464 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
373 af.alt_bit2, !!(af.altc_val && BIT(1))); 465 af.alt_bit2, !!(af.altc_val && BIT(1)));
374 break; 466 break;
@@ -378,11 +470,14 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
378 470
379 return -EINVAL; 471 return -EINVAL;
380 } 472 }
473out:
474 if (ret < 0)
475 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
381 476
382 return ret; 477 return ret;
383} 478}
384 479
385static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, 480static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
386 unsigned gpio) 481 unsigned gpio)
387{ 482{
388 u8 mode; 483 u8 mode;
@@ -393,6 +488,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
393 struct alternate_functions af = pct->soc->alternate_functions[gpio]; 488 struct alternate_functions af = pct->soc->alternate_functions[gpio];
394 /* on ABx5xx, there is no GPIO0, so adjust the offset */ 489 /* on ABx5xx, there is no GPIO0, so adjust the offset */
395 unsigned offset = gpio - 1; 490 unsigned offset = gpio - 1;
491 int ret;
396 492
397 /* 493 /*
398 * if gpiosel_bit is set to unused, 494 * if gpiosel_bit is set to unused,
@@ -402,8 +498,11 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
402 return ABX500_DEFAULT; 498 return ABX500_DEFAULT;
403 499
404 /* read GpioSelx register */ 500 /* read GpioSelx register */
405 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), 501 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
406 af.gpiosel_bit, &bit_mode); 502 af.gpiosel_bit, &bit_mode);
503 if (ret < 0)
504 goto out;
505
407 mode = bit_mode; 506 mode = bit_mode;
408 507
409 /* sanity check */ 508 /* sanity check */
@@ -435,14 +534,19 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
435 * pin use the AlternatFunction register 534 * pin use the AlternatFunction register
436 * read alt_bit1 value 535 * read alt_bit1 value
437 */ 536 */
438 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, 537 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
439 af.alt_bit1, &alt_bit1); 538 af.alt_bit1, &alt_bit1);
539 if (ret < 0)
540 goto out;
440 541
441 if (af.alt_bit2 != UNUSED) 542 if (af.alt_bit2 != UNUSED) {
442 /* read alt_bit2 value */ 543 /* read alt_bit2 value */
443 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, 544 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
545 af.alt_bit2,
444 &alt_bit2); 546 &alt_bit2);
445 else 547 if (ret < 0)
548 goto out;
549 } else
446 alt_bit2 = 0; 550 alt_bit2 = 0;
447 551
448 mode = (alt_bit2 << 1) + alt_bit1; 552 mode = (alt_bit2 << 1) + alt_bit1;
@@ -452,6 +556,10 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
452 return ABX500_ALT_B; 556 return ABX500_ALT_B;
453 else 557 else
454 return ABX500_ALT_C; 558 return ABX500_ALT_C;
559
560out:
561 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
562 return ret;
455} 563}
456 564
457#ifdef CONFIG_DEBUG_FS 565#ifdef CONFIG_DEBUG_FS
@@ -463,11 +571,14 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
463 struct gpio_chip *chip, 571 struct gpio_chip *chip,
464 unsigned offset, unsigned gpio) 572 unsigned offset, unsigned gpio)
465{ 573{
574 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
466 const char *label = gpiochip_is_requested(chip, offset - 1); 575 const char *label = gpiochip_is_requested(chip, offset - 1);
467 u8 gpio_offset = offset - 1; 576 u8 gpio_offset = offset - 1;
468 int mode = -1; 577 int mode = -1;
469 bool is_out; 578 bool is_out;
470 bool pull; 579 bool pd;
580 enum abx500_gpio_pull_updown pud = 0;
581 int ret;
471 582
472 const char *modes[] = { 583 const char *modes[] = {
473 [ABX500_DEFAULT] = "default", 584 [ABX500_DEFAULT] = "default",
@@ -476,21 +587,48 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
476 [ABX500_ALT_C] = "altC", 587 [ABX500_ALT_C] = "altC",
477 }; 588 };
478 589
479 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); 590 const char *pull_up_down[] = {
480 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); 591 [ABX500_GPIO_PULL_DOWN] = "pull down",
592 [ABX500_GPIO_PULL_NONE] = "pull none",
593 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
594 [ABX500_GPIO_PULL_UP] = "pull up",
595 };
596
597 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
598 gpio_offset, &is_out);
599 if (ret < 0)
600 goto out;
601
602 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
603 gpio, label ?: "(none)",
604 is_out ? "out" : "in ");
605
606 if (!is_out) {
607 if (abx500_pullud_supported(chip, offset)) {
608 ret = abx500_get_pull_updown(pct, offset, &pud);
609 if (ret < 0)
610 goto out;
611
612 seq_printf(s, " %-9s", pull_up_down[pud]);
613 } else {
614 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
615 gpio_offset, &pd);
616 if (ret < 0)
617 goto out;
618
619 seq_printf(s, " %-9s", pull_up_down[pd]);
620 }
621 } else
622 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
481 623
482 if (pctldev) 624 if (pctldev)
483 mode = abx500_get_mode(pctldev, chip, offset); 625 mode = abx500_get_mode(pctldev, chip, offset);
484 626
485 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", 627 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
486 gpio, label ?: "(none)", 628
487 is_out ? "out" : "in ", 629out:
488 is_out ? 630 if (ret < 0)
489 (chip->get 631 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
490 ? (chip->get(chip, offset) ? "hi" : "lo")
491 : "? ")
492 : (pull ? "pull up" : "pull down"),
493 (mode < 0) ? "unknown" : modes[mode]);
494} 632}
495 633
496static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 634static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -594,6 +732,9 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
594 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); 732 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
595 } 733 }
596 734
735 if (ret < 0)
736 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
737
597 return ret; 738 return ret;
598} 739}
599 740
@@ -642,10 +783,8 @@ static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
642 783
643 ret = abx500_set_mode(pct->pctldev, &pct->chip, 784 ret = abx500_set_mode(pct->pctldev, &pct->chip,
644 offset, p->altfunc); 785 offset, p->altfunc);
645 if (ret < 0) { 786 if (ret < 0)
646 dev_err(pct->dev, "%s setting altfunc failed\n", __func__); 787 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
647 return ret;
648 }
649 788
650 return ret; 789 return ret;
651} 790}
@@ -704,11 +843,193 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
704 chip->base + offset - 1); 843 chip->base + offset - 1);
705} 844}
706 845
846static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
847 struct pinctrl_map *map, unsigned num_maps)
848{
849 int i;
850
851 for (i = 0; i < num_maps; i++)
852 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
853 kfree(map[i].data.configs.configs);
854 kfree(map);
855}
856
857static int abx500_dt_reserve_map(struct pinctrl_map **map,
858 unsigned *reserved_maps,
859 unsigned *num_maps,
860 unsigned reserve)
861{
862 unsigned old_num = *reserved_maps;
863 unsigned new_num = *num_maps + reserve;
864 struct pinctrl_map *new_map;
865
866 if (old_num >= new_num)
867 return 0;
868
869 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
870 if (!new_map)
871 return -ENOMEM;
872
873 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
874
875 *map = new_map;
876 *reserved_maps = new_num;
877
878 return 0;
879}
880
881static int abx500_dt_add_map_mux(struct pinctrl_map **map,
882 unsigned *reserved_maps,
883 unsigned *num_maps, const char *group,
884 const char *function)
885{
886 if (*num_maps == *reserved_maps)
887 return -ENOSPC;
888
889 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
890 (*map)[*num_maps].data.mux.group = group;
891 (*map)[*num_maps].data.mux.function = function;
892 (*num_maps)++;
893
894 return 0;
895}
896
897static int abx500_dt_add_map_configs(struct pinctrl_map **map,
898 unsigned *reserved_maps,
899 unsigned *num_maps, const char *group,
900 unsigned long *configs, unsigned num_configs)
901{
902 unsigned long *dup_configs;
903
904 if (*num_maps == *reserved_maps)
905 return -ENOSPC;
906
907 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
908 GFP_KERNEL);
909 if (!dup_configs)
910 return -ENOMEM;
911
912 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
913
914 (*map)[*num_maps].data.configs.group_or_pin = group;
915 (*map)[*num_maps].data.configs.configs = dup_configs;
916 (*map)[*num_maps].data.configs.num_configs = num_configs;
917 (*num_maps)++;
918
919 return 0;
920}
921
922static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
923 const char *pin_name)
924{
925 int i, pin_number;
926 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
927
928 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
929 for (i = 0; i < npct->soc->npins; i++)
930 if (npct->soc->pins[i].number == pin_number)
931 return npct->soc->pins[i].name;
932 return NULL;
933}
934
935static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
936 struct device_node *np,
937 struct pinctrl_map **map,
938 unsigned *reserved_maps,
939 unsigned *num_maps)
940{
941 int ret;
942 const char *function = NULL;
943 unsigned long *configs;
944 unsigned int nconfigs = 0;
945 bool has_config = 0;
946 unsigned reserve = 0;
947 struct property *prop;
948 const char *group, *gpio_name;
949 struct device_node *np_config;
950
951 ret = of_property_read_string(np, "ste,function", &function);
952 if (ret >= 0)
953 reserve = 1;
954
955 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
956 if (nconfigs)
957 has_config = 1;
958
959 np_config = of_parse_phandle(np, "ste,config", 0);
960 if (np_config) {
961 ret = pinconf_generic_parse_dt_config(np_config, &configs,
962 &nconfigs);
963 if (ret)
964 goto exit;
965 has_config |= nconfigs;
966 }
967
968 ret = of_property_count_strings(np, "ste,pins");
969 if (ret < 0)
970 goto exit;
971
972 if (has_config)
973 reserve++;
974
975 reserve *= ret;
976
977 ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
978 if (ret < 0)
979 goto exit;
980
981 of_property_for_each_string(np, "ste,pins", prop, group) {
982 if (function) {
983 ret = abx500_dt_add_map_mux(map, reserved_maps,
984 num_maps, group, function);
985 if (ret < 0)
986 goto exit;
987 }
988 if (has_config) {
989 gpio_name = abx500_find_pin_name(pctldev, group);
990
991 ret = abx500_dt_add_map_configs(map, reserved_maps,
992 num_maps, gpio_name, configs, 1);
993 if (ret < 0)
994 goto exit;
995 }
996
997 }
998exit:
999 return ret;
1000}
1001
1002static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
1003 struct device_node *np_config,
1004 struct pinctrl_map **map, unsigned *num_maps)
1005{
1006 unsigned reserved_maps;
1007 struct device_node *np;
1008 int ret;
1009
1010 reserved_maps = 0;
1011 *map = NULL;
1012 *num_maps = 0;
1013
1014 for_each_child_of_node(np_config, np) {
1015 ret = abx500_dt_subnode_to_map(pctldev, np, map,
1016 &reserved_maps, num_maps);
1017 if (ret < 0) {
1018 abx500_dt_free_map(pctldev, *map, *num_maps);
1019 return ret;
1020 }
1021 }
1022
1023 return 0;
1024}
1025
707static const struct pinctrl_ops abx500_pinctrl_ops = { 1026static const struct pinctrl_ops abx500_pinctrl_ops = {
708 .get_groups_count = abx500_get_groups_cnt, 1027 .get_groups_count = abx500_get_groups_cnt,
709 .get_group_name = abx500_get_group_name, 1028 .get_group_name = abx500_get_group_name,
710 .get_group_pins = abx500_get_group_pins, 1029 .get_group_pins = abx500_get_group_pins,
711 .pin_dbg_show = abx500_pin_dbg_show, 1030 .pin_dbg_show = abx500_pin_dbg_show,
1031 .dt_node_to_map = abx500_dt_node_to_map,
1032 .dt_free_map = abx500_dt_free_map,
712}; 1033};
713 1034
714static int abx500_pin_config_get(struct pinctrl_dev *pctldev, 1035static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
@@ -723,10 +1044,9 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
723 unsigned long config) 1044 unsigned long config)
724{ 1045{
725 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 1046 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
726 struct pullud *pullud = pct->soc->pullud;
727 struct gpio_chip *chip = &pct->chip; 1047 struct gpio_chip *chip = &pct->chip;
728 unsigned offset; 1048 unsigned offset;
729 int ret; 1049 int ret = -EINVAL;
730 enum pin_config_param param = pinconf_to_config_param(config); 1050 enum pin_config_param param = pinconf_to_config_param(config);
731 enum pin_config_param argument = pinconf_to_config_argument(config); 1051 enum pin_config_param argument = pinconf_to_config_argument(config);
732 1052
@@ -739,41 +1059,83 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
739 offset = pin - 1; 1059 offset = pin - 1;
740 1060
741 switch (param) { 1061 switch (param) {
742 case PIN_CONFIG_BIAS_PULL_DOWN: 1062 case PIN_CONFIG_BIAS_DISABLE:
1063 ret = abx500_gpio_direction_input(chip, offset);
1064 if (ret < 0)
1065 goto out;
743 /* 1066 /*
744 * if argument = 1 set the pull down 1067 * Some chips only support pull down, while some actually
745 * else clear the pull down 1068 * support both pull up and pull down. Such chips have
1069 * a "pullud" range specified for the pins that support
1070 * both features. If the pin is not within that range, we
1071 * fall back to the old bit set that only support pull down.
746 */ 1072 */
1073 if (abx500_pullud_supported(chip, pin))
1074 ret = abx500_set_pull_updown(pct,
1075 pin,
1076 ABX500_GPIO_PULL_NONE);
1077 else
1078 /* Chip only supports pull down */
1079 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
1080 offset, ABX500_GPIO_PULL_NONE);
1081 break;
1082
1083 case PIN_CONFIG_BIAS_PULL_DOWN:
747 ret = abx500_gpio_direction_input(chip, offset); 1084 ret = abx500_gpio_direction_input(chip, offset);
1085 if (ret < 0)
1086 goto out;
748 /* 1087 /*
1088 * if argument = 1 set the pull down
1089 * else clear the pull down
749 * Some chips only support pull down, while some actually 1090 * Some chips only support pull down, while some actually
750 * support both pull up and pull down. Such chips have 1091 * support both pull up and pull down. Such chips have
751 * a "pullud" range specified for the pins that support 1092 * a "pullud" range specified for the pins that support
752 * both features. If the pin is not within that range, we 1093 * both features. If the pin is not within that range, we
753 * fall back to the old bit set that only support pull down. 1094 * fall back to the old bit set that only support pull down.
754 */ 1095 */
755 if (pullud && 1096 if (abx500_pullud_supported(chip, pin))
756 pin >= pullud->first_pin && 1097 ret = abx500_set_pull_updown(pct,
757 pin <= pullud->last_pin)
758 ret = abx500_config_pull_updown(pct,
759 pin, 1098 pin,
760 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); 1099 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
761 else 1100 else
762 /* Chip only supports pull down */ 1101 /* Chip only supports pull down */
763 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, 1102 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
764 offset, argument ? 0 : 1); 1103 offset,
1104 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
1105 break;
1106
1107 case PIN_CONFIG_BIAS_PULL_UP:
1108 ret = abx500_gpio_direction_input(chip, offset);
1109 if (ret < 0)
1110 goto out;
1111 /*
1112 * if argument = 1 set the pull up
1113 * else clear the pull up
1114 */
1115 ret = abx500_gpio_direction_input(chip, offset);
1116 /*
1117 * Some chips only support pull down, while some actually
1118 * support both pull up and pull down. Such chips have
1119 * a "pullud" range specified for the pins that support
1120 * both features. If the pin is not within that range, do
1121 * nothing
1122 */
1123 if (abx500_pullud_supported(chip, pin))
1124 ret = abx500_set_pull_updown(pct,
1125 pin,
1126 argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE);
765 break; 1127 break;
766 1128
767 case PIN_CONFIG_OUTPUT: 1129 case PIN_CONFIG_OUTPUT:
768 ret = abx500_gpio_direction_output(chip, offset, argument); 1130 ret = abx500_gpio_direction_output(chip, offset, argument);
769
770 break; 1131 break;
771 1132
772 default: 1133 default:
773 dev_err(chip->dev, "illegal configuration requested\n"); 1134 dev_err(chip->dev, "illegal configuration requested\n");
774
775 return -EINVAL;
776 } 1135 }
1136out:
1137 if (ret < 0)
1138 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
777 1139
778 return ret; 1140 return ret;
779} 1141}
@@ -881,9 +1243,6 @@ static int abx500_gpio_probe(struct platform_device *pdev)
881 id = (unsigned long)match->data; 1243 id = (unsigned long)match->data;
882 } 1244 }
883 1245
884 /* initialize the lock */
885 mutex_init(&pct->lock);
886
887 /* Poke in other ASIC variants here */ 1246 /* Poke in other ASIC variants here */
888 switch (id) { 1247 switch (id) {
889 case PINCTRL_AB8500: 1248 case PINCTRL_AB8500:
@@ -900,13 +1259,11 @@ static int abx500_gpio_probe(struct platform_device *pdev)
900 break; 1259 break;
901 default: 1260 default:
902 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); 1261 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
903 mutex_destroy(&pct->lock);
904 return -EINVAL; 1262 return -EINVAL;
905 } 1263 }
906 1264
907 if (!pct->soc) { 1265 if (!pct->soc) {
908 dev_err(&pdev->dev, "Invalid SOC data\n"); 1266 dev_err(&pdev->dev, "Invalid SOC data\n");
909 mutex_destroy(&pct->lock);
910 return -EINVAL; 1267 return -EINVAL;
911 } 1268 }
912 1269
@@ -917,7 +1274,6 @@ static int abx500_gpio_probe(struct platform_device *pdev)
917 ret = gpiochip_add(&pct->chip); 1274 ret = gpiochip_add(&pct->chip);
918 if (ret) { 1275 if (ret) {
919 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 1276 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
920 mutex_destroy(&pct->lock);
921 return ret; 1277 return ret;
922 } 1278 }
923 dev_info(&pdev->dev, "added gpiochip\n"); 1279 dev_info(&pdev->dev, "added gpiochip\n");
@@ -954,7 +1310,6 @@ out_rem_chip:
954 if (err) 1310 if (err)
955 dev_info(&pdev->dev, "failed to remove gpiochip\n"); 1311 dev_info(&pdev->dev, "failed to remove gpiochip\n");
956 1312
957 mutex_destroy(&pct->lock);
958 return ret; 1313 return ret;
959} 1314}
960 1315
@@ -974,8 +1329,6 @@ static int abx500_gpio_remove(struct platform_device *pdev)
974 return ret; 1329 return ret;
975 } 1330 }
976 1331
977 mutex_destroy(&pct->lock);
978
979 return 0; 1332 return 0;
980} 1333}
981 1334
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5d7529ed5392..b90a3a0ac534 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1543,12 +1543,6 @@ static int at91_gpio_probe(struct platform_device *pdev)
1543 goto err; 1543 goto err;
1544 } 1544 }
1545 1545
1546 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547 if (!res) {
1548 ret = -ENOENT;
1549 goto err;
1550 }
1551
1552 irq = platform_get_irq(pdev, 0); 1546 irq = platform_get_irq(pdev, 0);
1553 if (irq < 0) { 1547 if (irq < 0) {
1554 ret = irq; 1548 ret = irq;
@@ -1561,6 +1555,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
1561 goto err; 1555 goto err;
1562 } 1556 }
1563 1557
1558 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1559 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1565 if (IS_ERR(at91_chip->regbase)) { 1560 if (IS_ERR(at91_chip->regbase)) {
1566 ret = PTR_ERR(at91_chip->regbase); 1561 ret = PTR_ERR(at91_chip->regbase);
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
new file mode 100644
index 000000000000..e9d735dcebfb
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -0,0 +1,543 @@
1/*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/bitops.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/gpio.h>
30#include <linux/irqdomain.h>
31#include <linux/acpi.h>
32#include <linux/acpi_gpio.h>
33#include <linux/platform_device.h>
34#include <linux/seq_file.h>
35#include <linux/io.h>
36#include <linux/pm_runtime.h>
37#include <linux/pinctrl/pinctrl.h>
38
39/* memory mapped register offsets */
40#define BYT_CONF0_REG 0x000
41#define BYT_CONF1_REG 0x004
42#define BYT_VAL_REG 0x008
43#define BYT_DFT_REG 0x00c
44#define BYT_INT_STAT_REG 0x800
45
46/* BYT_CONF0_REG register bits */
47#define BYT_TRIG_NEG BIT(26)
48#define BYT_TRIG_POS BIT(25)
49#define BYT_TRIG_LVL BIT(24)
50#define BYT_PIN_MUX 0x07
51
52/* BYT_VAL_REG register bits */
53#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
54#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
55#define BYT_LEVEL BIT(0)
56
57#define BYT_DIR_MASK (BIT(1) | BIT(2))
58#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
59
60#define BYT_NGPIO_SCORE 102
61#define BYT_NGPIO_NCORE 28
62#define BYT_NGPIO_SUS 44
63
64/*
65 * Baytrail gpio controller consist of three separate sub-controllers called
66 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
67 *
68 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
69 * _not_ correspond to the first gpio register at controller's gpio base.
70 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
71 * each sub-controller needs to have its own mapping table
72 */
73
74/* score_pins[gpio_nr] = pad_nr */
75
76static unsigned const score_pins[BYT_NGPIO_SCORE] = {
77 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
78 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
79 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
80 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
81 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
82 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
83 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
84 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
85 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
86 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
87 97, 100,
88};
89
90static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
91 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
92 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
93 3, 6, 10, 13, 2, 5, 9, 7,
94};
95
96static unsigned const sus_pins[BYT_NGPIO_SUS] = {
97 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
98 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
99 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
100 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
101 52, 53, 59, 40,
102};
103
104static struct pinctrl_gpio_range byt_ranges[] = {
105 {
106 .name = "1", /* match with acpi _UID in probe */
107 .npins = BYT_NGPIO_SCORE,
108 .pins = score_pins,
109 },
110 {
111 .name = "2",
112 .npins = BYT_NGPIO_NCORE,
113 .pins = ncore_pins,
114 },
115 {
116 .name = "3",
117 .npins = BYT_NGPIO_SUS,
118 .pins = sus_pins,
119 },
120 {
121 },
122};
123
124struct byt_gpio {
125 struct gpio_chip chip;
126 struct irq_domain *domain;
127 struct platform_device *pdev;
128 spinlock_t lock;
129 void __iomem *reg_base;
130 struct pinctrl_gpio_range *range;
131};
132
133static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
134 int reg)
135{
136 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
137 u32 reg_offset;
138 void __iomem *ptr;
139
140 if (reg == BYT_INT_STAT_REG)
141 reg_offset = (offset / 32) * 4;
142 else
143 reg_offset = vg->range->pins[offset] * 16;
144
145 ptr = (void __iomem *) (vg->reg_base + reg_offset + reg);
146 return ptr;
147}
148
149static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
150{
151 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
152
153 pm_runtime_get(&vg->pdev->dev);
154
155 return 0;
156}
157
158static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
159{
160 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
161 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
162 u32 value;
163
164 /* clear interrupt triggering */
165 value = readl(reg);
166 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
167 writel(value, reg);
168
169 pm_runtime_put(&vg->pdev->dev);
170}
171
172static int byt_irq_type(struct irq_data *d, unsigned type)
173{
174 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
175 u32 offset = irqd_to_hwirq(d);
176 u32 value;
177 unsigned long flags;
178 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
179
180 if (offset >= vg->chip.ngpio)
181 return -EINVAL;
182
183 spin_lock_irqsave(&vg->lock, flags);
184 value = readl(reg);
185
186 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
187 * are used to indicate high and low level triggering
188 */
189 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
190
191 switch (type) {
192 case IRQ_TYPE_LEVEL_HIGH:
193 value |= BYT_TRIG_LVL;
194 case IRQ_TYPE_EDGE_RISING:
195 value |= BYT_TRIG_POS;
196 break;
197 case IRQ_TYPE_LEVEL_LOW:
198 value |= BYT_TRIG_LVL;
199 case IRQ_TYPE_EDGE_FALLING:
200 value |= BYT_TRIG_NEG;
201 break;
202 case IRQ_TYPE_EDGE_BOTH:
203 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
204 break;
205 }
206 writel(value, reg);
207
208 spin_unlock_irqrestore(&vg->lock, flags);
209
210 return 0;
211}
212
213static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
214{
215 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
216 return readl(reg) & BYT_LEVEL;
217}
218
219static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
220{
221 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
222 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
223 unsigned long flags;
224 u32 old_val;
225
226 spin_lock_irqsave(&vg->lock, flags);
227
228 old_val = readl(reg);
229
230 if (value)
231 writel(old_val | BYT_LEVEL, reg);
232 else
233 writel(old_val & ~BYT_LEVEL, reg);
234
235 spin_unlock_irqrestore(&vg->lock, flags);
236}
237
238static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
239{
240 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
241 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
242 unsigned long flags;
243 u32 value;
244
245 spin_lock_irqsave(&vg->lock, flags);
246
247 value = readl(reg) | BYT_DIR_MASK;
248 value = value & (~BYT_INPUT_EN); /* active low */
249 writel(value, reg);
250
251 spin_unlock_irqrestore(&vg->lock, flags);
252
253 return 0;
254}
255
256static int byt_gpio_direction_output(struct gpio_chip *chip,
257 unsigned gpio, int value)
258{
259 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
260 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
261 unsigned long flags;
262 u32 reg_val;
263
264 spin_lock_irqsave(&vg->lock, flags);
265
266 reg_val = readl(reg) | (BYT_DIR_MASK | !!value);
267 reg_val &= ~(BYT_OUTPUT_EN | !value);
268 writel(reg_val, reg);
269
270 spin_unlock_irqrestore(&vg->lock, flags);
271
272 return 0;
273}
274
275static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
276{
277 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
278 int i;
279 unsigned long flags;
280 u32 conf0, val, offs;
281
282 spin_lock_irqsave(&vg->lock, flags);
283
284 for (i = 0; i < vg->chip.ngpio; i++) {
285 offs = vg->range->pins[i] * 16;
286 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
287 val = readl(vg->reg_base + offs + BYT_VAL_REG);
288
289 seq_printf(s,
290 " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
291 i,
292 val & BYT_INPUT_EN ? " " : "in",
293 val & BYT_OUTPUT_EN ? " " : "out",
294 val & BYT_LEVEL ? "hi" : "lo",
295 vg->range->pins[i], offs,
296 conf0 & 0x7,
297 conf0 & BYT_TRIG_NEG ? "fall " : "",
298 conf0 & BYT_TRIG_POS ? "rise " : "",
299 conf0 & BYT_TRIG_LVL ? "lvl " : "");
300 }
301 spin_unlock_irqrestore(&vg->lock, flags);
302}
303
304static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
305{
306 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
307 return irq_create_mapping(vg->domain, offset);
308}
309
310static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
311{
312 struct irq_data *data = irq_desc_get_irq_data(desc);
313 struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
314 struct irq_chip *chip = irq_data_get_irq_chip(data);
315 u32 base, pin, mask;
316 void __iomem *reg;
317 u32 pending;
318 unsigned virq;
319 int looplimit = 0;
320
321 /* check from GPIO controller which pin triggered the interrupt */
322 for (base = 0; base < vg->chip.ngpio; base += 32) {
323
324 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
325
326 while ((pending = readl(reg))) {
327 pin = __ffs(pending);
328 mask = BIT(pin);
329 /* Clear before handling so we can't lose an edge */
330 writel(mask, reg);
331
332 virq = irq_find_mapping(vg->domain, base + pin);
333 generic_handle_irq(virq);
334
335 /* In case bios or user sets triggering incorretly a pin
336 * might remain in "interrupt triggered" state.
337 */
338 if (looplimit++ > 32) {
339 dev_err(&vg->pdev->dev,
340 "Gpio %d interrupt flood, disabling\n",
341 base + pin);
342
343 reg = byt_gpio_reg(&vg->chip, base + pin,
344 BYT_CONF0_REG);
345 mask = readl(reg);
346 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
347 BYT_TRIG_LVL);
348 writel(mask, reg);
349 mask = readl(reg); /* flush */
350 break;
351 }
352 }
353 }
354 chip->irq_eoi(data);
355}
356
357static void byt_irq_unmask(struct irq_data *d)
358{
359}
360
361static void byt_irq_mask(struct irq_data *d)
362{
363}
364
365static struct irq_chip byt_irqchip = {
366 .name = "BYT-GPIO",
367 .irq_mask = byt_irq_mask,
368 .irq_unmask = byt_irq_unmask,
369 .irq_set_type = byt_irq_type,
370};
371
372static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
373{
374 void __iomem *reg;
375 u32 base, value;
376
377 /* clear interrupt status trigger registers */
378 for (base = 0; base < vg->chip.ngpio; base += 32) {
379 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
380 writel(0xffffffff, reg);
381 /* make sure trigger bits are cleared, if not then a pin
382 might be misconfigured in bios */
383 value = readl(reg);
384 if (value)
385 dev_err(&vg->pdev->dev,
386 "GPIO interrupt error, pins misconfigured\n");
387 }
388}
389
390static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
391 irq_hw_number_t hw)
392{
393 struct byt_gpio *vg = d->host_data;
394
395 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
396 "demux");
397 irq_set_chip_data(virq, vg);
398 irq_set_irq_type(virq, IRQ_TYPE_NONE);
399
400 return 0;
401}
402
403static const struct irq_domain_ops byt_gpio_irq_ops = {
404 .map = byt_gpio_irq_map,
405};
406
407static int byt_gpio_probe(struct platform_device *pdev)
408{
409 struct byt_gpio *vg;
410 struct gpio_chip *gc;
411 struct resource *mem_rc, *irq_rc;
412 struct device *dev = &pdev->dev;
413 struct acpi_device *acpi_dev;
414 struct pinctrl_gpio_range *range;
415 acpi_handle handle = ACPI_HANDLE(dev);
416 unsigned hwirq;
417 int ret;
418
419 if (acpi_bus_get_device(handle, &acpi_dev))
420 return -ENODEV;
421
422 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
423 if (!vg) {
424 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
425 return -ENOMEM;
426 }
427
428 for (range = byt_ranges; range->name; range++) {
429 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
430 vg->chip.ngpio = range->npins;
431 vg->range = range;
432 break;
433 }
434 }
435
436 if (!vg->chip.ngpio || !vg->range)
437 return -ENODEV;
438
439 vg->pdev = pdev;
440 platform_set_drvdata(pdev, vg);
441
442 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
444 if (IS_ERR(vg->reg_base))
445 return PTR_ERR(vg->reg_base);
446
447 spin_lock_init(&vg->lock);
448
449 gc = &vg->chip;
450 gc->label = dev_name(&pdev->dev);
451 gc->owner = THIS_MODULE;
452 gc->request = byt_gpio_request;
453 gc->free = byt_gpio_free;
454 gc->direction_input = byt_gpio_direction_input;
455 gc->direction_output = byt_gpio_direction_output;
456 gc->get = byt_gpio_get;
457 gc->set = byt_gpio_set;
458 gc->dbg_show = byt_gpio_dbg_show;
459 gc->base = -1;
460 gc->can_sleep = 0;
461 gc->dev = dev;
462
463 ret = gpiochip_add(gc);
464 if (ret) {
465 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
466 return ret;
467 }
468
469 /* set up interrupts */
470 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
471 if (irq_rc && irq_rc->start) {
472 hwirq = irq_rc->start;
473 gc->to_irq = byt_gpio_to_irq;
474
475 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
476 &byt_gpio_irq_ops, vg);
477 if (!vg->domain)
478 return -ENXIO;
479
480 byt_gpio_irq_init_hw(vg);
481
482 irq_set_handler_data(hwirq, vg);
483 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
484
485 /* Register interrupt handlers for gpio signaled acpi events */
486 acpi_gpiochip_request_interrupts(gc);
487 }
488
489 pm_runtime_enable(dev);
490
491 return 0;
492}
493
494static int byt_gpio_runtime_suspend(struct device *dev)
495{
496 return 0;
497}
498
499static int byt_gpio_runtime_resume(struct device *dev)
500{
501 return 0;
502}
503
504static const struct dev_pm_ops byt_gpio_pm_ops = {
505 .runtime_suspend = byt_gpio_runtime_suspend,
506 .runtime_resume = byt_gpio_runtime_resume,
507};
508
509static const struct acpi_device_id byt_gpio_acpi_match[] = {
510 { "INT33B2", 0 },
511 { }
512};
513MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
514
515static int byt_gpio_remove(struct platform_device *pdev)
516{
517 struct byt_gpio *vg = platform_get_drvdata(pdev);
518 int err;
519 pm_runtime_disable(&pdev->dev);
520 err = gpiochip_remove(&vg->chip);
521 if (err)
522 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
523
524 return 0;
525}
526
527static struct platform_driver byt_gpio_driver = {
528 .probe = byt_gpio_probe,
529 .remove = byt_gpio_remove,
530 .driver = {
531 .name = "byt_gpio",
532 .owner = THIS_MODULE,
533 .pm = &byt_gpio_pm_ops,
534 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
535 },
536};
537
538static int __init byt_gpio_init(void)
539{
540 return platform_driver_register(&byt_gpio_driver);
541}
542
543subsys_initcall(byt_gpio_init);
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index c8f20a3d8f88..a1c88b30f71f 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -113,7 +113,7 @@ static struct lock_class_key gpio_lock_class;
113 113
114/* pins are just named GPIO0..GPIO53 */ 114/* pins are just named GPIO0..GPIO53 */
115#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 115#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
116struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 116static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
117 BCM2835_GPIO_PIN(0), 117 BCM2835_GPIO_PIN(0),
118 BCM2835_GPIO_PIN(1), 118 BCM2835_GPIO_PIN(1),
119 BCM2835_GPIO_PIN(2), 119 BCM2835_GPIO_PIN(2),
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index eeff7f7fc920..f22a2193d949 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -853,7 +853,6 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
853 } 853 }
854 u300_gpio_free_ports(gpio); 854 u300_gpio_free_ports(gpio);
855 clk_disable_unprepare(gpio->clk); 855 clk_disable_unprepare(gpio->clk);
856 platform_set_drvdata(pdev, NULL);
857 return 0; 856 return 0;
858} 857}
859 858
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 5f58cf0e96e2..a74b3cbd7451 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -50,37 +50,58 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
50 { } 50 { }
51}; 51};
52 52
53static void exynos_gpio_irq_unmask(struct irq_data *irqd) 53static void exynos_gpio_irq_mask(struct irq_data *irqd)
54{ 54{
55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
56 struct samsung_pinctrl_drv_data *d = bank->drvdata; 56 struct samsung_pinctrl_drv_data *d = bank->drvdata;
57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
58 unsigned long mask; 58 unsigned long mask;
59 unsigned long flags;
60
61 spin_lock_irqsave(&bank->slock, flags);
59 62
60 mask = readl(d->virt_base + reg_mask); 63 mask = readl(d->virt_base + reg_mask);
61 mask &= ~(1 << irqd->hwirq); 64 mask |= 1 << irqd->hwirq;
62 writel(mask, d->virt_base + reg_mask); 65 writel(mask, d->virt_base + reg_mask);
66
67 spin_unlock_irqrestore(&bank->slock, flags);
63} 68}
64 69
65static void exynos_gpio_irq_mask(struct irq_data *irqd) 70static void exynos_gpio_irq_ack(struct irq_data *irqd)
66{ 71{
67 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
68 struct samsung_pinctrl_drv_data *d = bank->drvdata; 73 struct samsung_pinctrl_drv_data *d = bank->drvdata;
69 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 74 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
70 unsigned long mask;
71 75
72 mask = readl(d->virt_base + reg_mask); 76 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
73 mask |= 1 << irqd->hwirq;
74 writel(mask, d->virt_base + reg_mask);
75} 77}
76 78
77static void exynos_gpio_irq_ack(struct irq_data *irqd) 79static void exynos_gpio_irq_unmask(struct irq_data *irqd)
78{ 80{
79 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 81 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
80 struct samsung_pinctrl_drv_data *d = bank->drvdata; 82 struct samsung_pinctrl_drv_data *d = bank->drvdata;
81 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; 83 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
84 unsigned long mask;
85 unsigned long flags;
82 86
83 writel(1 << irqd->hwirq, d->virt_base + reg_pend); 87 /*
88 * Ack level interrupts right before unmask
89 *
90 * If we don't do this we'll get a double-interrupt. Level triggered
91 * interrupts must not fire an interrupt if the level is not
92 * _currently_ active, even if it was active while the interrupt was
93 * masked.
94 */
95 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
96 exynos_gpio_irq_ack(irqd);
97
98 spin_lock_irqsave(&bank->slock, flags);
99
100 mask = readl(d->virt_base + reg_mask);
101 mask &= ~(1 << irqd->hwirq);
102 writel(mask, d->virt_base + reg_mask);
103
104 spin_unlock_irqrestore(&bank->slock, flags);
84} 105}
85 106
86static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 107static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -258,37 +279,58 @@ err_domains:
258 return ret; 279 return ret;
259} 280}
260 281
261static void exynos_wkup_irq_unmask(struct irq_data *irqd) 282static void exynos_wkup_irq_mask(struct irq_data *irqd)
262{ 283{
263 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); 284 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
264 struct samsung_pinctrl_drv_data *d = b->drvdata; 285 struct samsung_pinctrl_drv_data *d = b->drvdata;
265 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; 286 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
266 unsigned long mask; 287 unsigned long mask;
288 unsigned long flags;
289
290 spin_lock_irqsave(&b->slock, flags);
267 291
268 mask = readl(d->virt_base + reg_mask); 292 mask = readl(d->virt_base + reg_mask);
269 mask &= ~(1 << irqd->hwirq); 293 mask |= 1 << irqd->hwirq;
270 writel(mask, d->virt_base + reg_mask); 294 writel(mask, d->virt_base + reg_mask);
295
296 spin_unlock_irqrestore(&b->slock, flags);
271} 297}
272 298
273static void exynos_wkup_irq_mask(struct irq_data *irqd) 299static void exynos_wkup_irq_ack(struct irq_data *irqd)
274{ 300{
275 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); 301 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
276 struct samsung_pinctrl_drv_data *d = b->drvdata; 302 struct samsung_pinctrl_drv_data *d = b->drvdata;
277 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; 303 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
278 unsigned long mask;
279 304
280 mask = readl(d->virt_base + reg_mask); 305 writel(1 << irqd->hwirq, d->virt_base + pend);
281 mask |= 1 << irqd->hwirq;
282 writel(mask, d->virt_base + reg_mask);
283} 306}
284 307
285static void exynos_wkup_irq_ack(struct irq_data *irqd) 308static void exynos_wkup_irq_unmask(struct irq_data *irqd)
286{ 309{
287 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); 310 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
288 struct samsung_pinctrl_drv_data *d = b->drvdata; 311 struct samsung_pinctrl_drv_data *d = b->drvdata;
289 unsigned long pend = d->ctrl->weint_pend + b->eint_offset; 312 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
313 unsigned long mask;
314 unsigned long flags;
290 315
291 writel(1 << irqd->hwirq, d->virt_base + pend); 316 /*
317 * Ack level interrupts right before unmask
318 *
319 * If we don't do this we'll get a double-interrupt. Level triggered
320 * interrupts must not fire an interrupt if the level is not
321 * _currently_ active, even if it was active while the interrupt was
322 * masked.
323 */
324 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
325 exynos_wkup_irq_ack(irqd);
326
327 spin_lock_irqsave(&b->slock, flags);
328
329 mask = readl(d->virt_base + reg_mask);
330 mask &= ~(1 << irqd->hwirq);
331 writel(mask, d->virt_base + reg_mask);
332
333 spin_unlock_irqrestore(&b->slock, flags);
292} 334}
293 335
294static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) 336static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 32a48f44f574..3b283fd898ff 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -220,7 +220,7 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
220 dev_err(dev, "failed to alloc memory for group name\n"); 220 dev_err(dev, "failed to alloc memory for group name\n");
221 goto free_map; 221 goto free_map;
222 } 222 }
223 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX); 223 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX);
224 224
225 /* 225 /*
226 * don't have config options? then skip over to creating function 226 * don't have config options? then skip over to creating function
@@ -259,7 +259,8 @@ skip_cfgs:
259 dev_err(dev, "failed to alloc memory for func name\n"); 259 dev_err(dev, "failed to alloc memory for func name\n");
260 goto free_cfg; 260 goto free_cfg;
261 } 261 }
262 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX); 262 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name,
263 FUNCTION_SUFFIX);
263 264
264 map[*nmaps].data.mux.group = gname; 265 map[*nmaps].data.mux.group = gname;
265 map[*nmaps].data.mux.function = fname; 266 map[*nmaps].data.mux.function = fname;
@@ -713,7 +714,8 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
713 dev_err(dev, "failed to alloc memory for group name\n"); 714 dev_err(dev, "failed to alloc memory for group name\n");
714 return -ENOMEM; 715 return -ENOMEM;
715 } 716 }
716 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); 717 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
718 GROUP_SUFFIX);
717 719
718 grp->name = gname; 720 grp->name = gname;
719 grp->pins = pin_list; 721 grp->pins = pin_list;
@@ -733,7 +735,8 @@ skip_to_pin_function:
733 dev_err(dev, "failed to alloc memory for func name\n"); 735 dev_err(dev, "failed to alloc memory for func name\n");
734 return -ENOMEM; 736 return -ENOMEM;
735 } 737 }
736 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); 738 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
739 FUNCTION_SUFFIX);
737 740
738 func->name = fname; 741 func->name = fname;
739 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 742 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
@@ -806,7 +809,7 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev,
806 809
807 /* for each pin, set the name of the pin */ 810 /* for each pin, set the name of the pin */
808 for (pin = 0; pin < ctrldesc->npins; pin++) { 811 for (pin = 0; pin < ctrldesc->npins; pin++) {
809 sprintf(pin_names, "gpio%02d", pin); 812 snprintf(pin_names, 6, "gpio%02d", pin);
810 pdesc = pindesc + pin; 813 pdesc = pindesc + pin;
811 pdesc->name = pin_names; 814 pdesc->name = pin_names;
812 pin_names += PIN_NAME_LENGTH; 815 pin_names += PIN_NAME_LENGTH;
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4fcfff9243be..57a4eb0add2e 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -221,13 +221,21 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221 pin_id = pins[i]; 221 pin_id = pins[i];
222 pin_reg = &info->pin_regs[pin_id]; 222 pin_reg = &info->pin_regs[pin_id];
223 223
224 if (!pin_reg->mux_reg) { 224 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
225 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 225 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
226 info->pins[pin_id].name); 226 info->pins[pin_id].name);
227 return -EINVAL; 227 return -EINVAL;
228 } 228 }
229 229
230 writel(mux[i], ipctl->base + pin_reg->mux_reg); 230 if (info->flags & SHARE_MUX_CONF_REG) {
231 u32 reg;
232 reg = readl(ipctl->base + pin_reg->mux_reg);
233 reg &= ~(0x7 << 20);
234 reg |= (mux[i] << 20);
235 writel(reg, ipctl->base + pin_reg->mux_reg);
236 } else {
237 writel(mux[i], ipctl->base + pin_reg->mux_reg);
238 }
231 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 239 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
232 pin_reg->mux_reg, mux[i]); 240 pin_reg->mux_reg, mux[i]);
233 241
@@ -287,7 +295,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
287 const struct imx_pinctrl_soc_info *info = ipctl->info; 295 const struct imx_pinctrl_soc_info *info = ipctl->info;
288 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 296 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
289 297
290 if (!pin_reg->conf_reg) { 298 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
291 dev_err(info->dev, "Pin(%s) does not support config function\n", 299 dev_err(info->dev, "Pin(%s) does not support config function\n",
292 info->pins[pin_id].name); 300 info->pins[pin_id].name);
293 return -EINVAL; 301 return -EINVAL;
@@ -295,6 +303,9 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
295 303
296 *config = readl(ipctl->base + pin_reg->conf_reg); 304 *config = readl(ipctl->base + pin_reg->conf_reg);
297 305
306 if (info->flags & SHARE_MUX_CONF_REG)
307 *config &= 0xffff;
308
298 return 0; 309 return 0;
299} 310}
300 311
@@ -305,7 +316,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
305 const struct imx_pinctrl_soc_info *info = ipctl->info; 316 const struct imx_pinctrl_soc_info *info = ipctl->info;
306 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 317 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
307 318
308 if (!pin_reg->conf_reg) { 319 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
309 dev_err(info->dev, "Pin(%s) does not support config function\n", 320 dev_err(info->dev, "Pin(%s) does not support config function\n",
310 info->pins[pin_id].name); 321 info->pins[pin_id].name);
311 return -EINVAL; 322 return -EINVAL;
@@ -314,7 +325,15 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
314 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 325 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
315 info->pins[pin_id].name); 326 info->pins[pin_id].name);
316 327
317 writel(config, ipctl->base + pin_reg->conf_reg); 328 if (info->flags & SHARE_MUX_CONF_REG) {
329 u32 reg;
330 reg = readl(ipctl->base + pin_reg->conf_reg);
331 reg &= ~0xffff;
332 reg |= config;
333 writel(reg, ipctl->base + pin_reg->conf_reg);
334 } else {
335 writel(config, ipctl->base + pin_reg->conf_reg);
336 }
318 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 337 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
319 pin_reg->conf_reg, config); 338 pin_reg->conf_reg, config);
320 339
@@ -381,19 +400,24 @@ static struct pinctrl_desc imx_pinctrl_desc = {
381 * 1 u32 CONFIG, so 24 types in total for each pin. 400 * 1 u32 CONFIG, so 24 types in total for each pin.
382 */ 401 */
383#define FSL_PIN_SIZE 24 402#define FSL_PIN_SIZE 24
403#define SHARE_FSL_PIN_SIZE 20
384 404
385static int imx_pinctrl_parse_groups(struct device_node *np, 405static int imx_pinctrl_parse_groups(struct device_node *np,
386 struct imx_pin_group *grp, 406 struct imx_pin_group *grp,
387 struct imx_pinctrl_soc_info *info, 407 struct imx_pinctrl_soc_info *info,
388 u32 index) 408 u32 index)
389{ 409{
390 int size; 410 int size, pin_size;
391 const __be32 *list; 411 const __be32 *list;
392 int i; 412 int i;
393 u32 config; 413 u32 config;
394 414
395 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 415 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
396 416
417 if (info->flags & SHARE_MUX_CONF_REG)
418 pin_size = SHARE_FSL_PIN_SIZE;
419 else
420 pin_size = FSL_PIN_SIZE;
397 /* Initialise group */ 421 /* Initialise group */
398 grp->name = np->name; 422 grp->name = np->name;
399 423
@@ -403,12 +427,12 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
403 */ 427 */
404 list = of_get_property(np, "fsl,pins", &size); 428 list = of_get_property(np, "fsl,pins", &size);
405 /* we do not check return since it's safe node passed down */ 429 /* we do not check return since it's safe node passed down */
406 if (!size || size % FSL_PIN_SIZE) { 430 if (!size || size % pin_size) {
407 dev_err(info->dev, "Invalid fsl,pins property\n"); 431 dev_err(info->dev, "Invalid fsl,pins property\n");
408 return -EINVAL; 432 return -EINVAL;
409 } 433 }
410 434
411 grp->npins = size / FSL_PIN_SIZE; 435 grp->npins = size / pin_size;
412 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 436 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
413 GFP_KERNEL); 437 GFP_KERNEL);
414 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 438 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
@@ -421,10 +445,17 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
421 GFP_KERNEL); 445 GFP_KERNEL);
422 for (i = 0; i < grp->npins; i++) { 446 for (i = 0; i < grp->npins; i++) {
423 u32 mux_reg = be32_to_cpu(*list++); 447 u32 mux_reg = be32_to_cpu(*list++);
424 u32 conf_reg = be32_to_cpu(*list++); 448 u32 conf_reg;
425 unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; 449 unsigned int pin_id;
426 struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 450 struct imx_pin_reg *pin_reg;
427 451
452 if (info->flags & SHARE_MUX_CONF_REG)
453 conf_reg = mux_reg;
454 else
455 conf_reg = be32_to_cpu(*list++);
456
457 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
458 pin_reg = &info->pin_regs[pin_id];
428 grp->pins[i] = pin_id; 459 grp->pins[i] = pin_id;
429 pin_reg->mux_reg = mux_reg; 460 pin_reg->mux_reg = mux_reg;
430 pin_reg->conf_reg = conf_reg; 461 pin_reg->conf_reg = conf_reg;
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
index 607ef5497552..bcedd991c9f3 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -74,8 +74,12 @@ struct imx_pinctrl_soc_info {
74 unsigned int ngroups; 74 unsigned int ngroups;
75 struct imx_pmx_func *functions; 75 struct imx_pmx_func *functions;
76 unsigned int nfunctions; 76 unsigned int nfunctions;
77 unsigned int flags;
77}; 78};
78 79
80#define ZERO_OFFSET_VALID 0x1
81#define SHARE_MUX_CONF_REG 0x2
82
79#define NO_MUX 0x0 83#define NO_MUX 0x0
80#define NO_PAD 0x0 84#define NO_PAD 0x0
81 85
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
index b45c4eb35798..f5d56436ba7f 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -515,7 +515,6 @@ int mxs_pinctrl_probe(struct platform_device *pdev,
515 return 0; 515 return 0;
516 516
517err: 517err:
518 platform_set_drvdata(pdev, NULL);
519 iounmap(d->base); 518 iounmap(d->base);
520 return ret; 519 return ret;
521} 520}
@@ -525,7 +524,6 @@ int mxs_pinctrl_remove(struct platform_device *pdev)
525{ 524{
526 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); 525 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
527 526
528 platform_set_drvdata(pdev, NULL);
529 pinctrl_unregister(d->pctl); 527 pinctrl_unregister(d->pctl);
530 iounmap(d->base); 528 iounmap(d->base);
531 529
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 8a4f9c5c0b8e..4a1cfdce2232 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1309,7 +1309,7 @@ static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1309 return 0; 1309 return 0;
1310} 1310}
1311 1311
1312const struct irq_domain_ops nmk_gpio_irq_simple_ops = { 1312static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1313 .map = nmk_gpio_irq_map, 1313 .map = nmk_gpio_irq_map,
1314 .xlate = irq_domain_xlate_twocell, 1314 .xlate = irq_domain_xlate_twocell,
1315}; 1315};
@@ -1681,7 +1681,7 @@ static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1681 return has_config; 1681 return has_config;
1682} 1682}
1683 1683
1684int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1684static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1685 struct device_node *np, 1685 struct device_node *np,
1686 struct pinctrl_map **map, 1686 struct pinctrl_map **map,
1687 unsigned *reserved_maps, 1687 unsigned *reserved_maps,
@@ -1740,7 +1740,7 @@ exit:
1740 return ret; 1740 return ret;
1741} 1741}
1742 1742
1743int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1743static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1744 struct device_node *np_config, 1744 struct device_node *np_config,
1745 struct pinctrl_map **map, unsigned *num_maps) 1745 struct pinctrl_map **map, unsigned *num_maps)
1746{ 1746{
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
new file mode 100644
index 000000000000..1eb5a2e43b06
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -0,0 +1,1394 @@
1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
39#include <linux/clk-provider.h>
40#include <dt-bindings/pinctrl/rockchip.h>
41
42#include "core.h"
43#include "pinconf.h"
44
45/* GPIO control registers */
46#define GPIO_SWPORT_DR 0x00
47#define GPIO_SWPORT_DDR 0x04
48#define GPIO_INTEN 0x30
49#define GPIO_INTMASK 0x34
50#define GPIO_INTTYPE_LEVEL 0x38
51#define GPIO_INT_POLARITY 0x3c
52#define GPIO_INT_STATUS 0x40
53#define GPIO_INT_RAWSTATUS 0x44
54#define GPIO_DEBOUNCE 0x48
55#define GPIO_PORTS_EOI 0x4c
56#define GPIO_EXT_PORT 0x50
57#define GPIO_LS_SYNC 0x60
58
59/**
60 * @reg_base: register base of the gpio bank
61 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number
64 * @nr_pins: number of pins in this bank
65 * @name: name of the bank
66 * @bank_num: number of the bank, to account for holes
67 * @valid: are all necessary informations present
68 * @of_node: dt node of this bank
69 * @drvdata: common pinctrl basedata
70 * @domain: irqdomain of the gpio bank
71 * @gpio_chip: gpiolib chip
72 * @grange: gpio range
73 * @slock: spinlock for the gpio bank
74 */
75struct rockchip_pin_bank {
76 void __iomem *reg_base;
77 struct clk *clk;
78 int irq;
79 u32 pin_base;
80 u8 nr_pins;
81 char *name;
82 u8 bank_num;
83 bool valid;
84 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata;
86 struct irq_domain *domain;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange;
89 spinlock_t slock;
90
91};
92
93#define PIN_BANK(id, pins, label) \
94 { \
95 .bank_num = id, \
96 .nr_pins = pins, \
97 .name = label, \
98 }
99
100/**
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
103 */
104struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks;
106 u32 nr_banks;
107 u32 nr_pins;
108 char *label;
109 int mux_offset;
110 int pull_offset;
111 bool pull_auto;
112 int pull_bank_stride;
113};
114
115struct rockchip_pin_config {
116 unsigned int func;
117 unsigned long *configs;
118 unsigned int nconfigs;
119};
120
121/**
122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
123 * @name: name of the pin group, used to lookup the group.
124 * @pins: the pins included in this group.
125 * @npins: number of pins included in this group.
126 * @func: the mux function number to be programmed when selected.
127 * @configs: the config values to be set for each pin
128 * @nconfigs: number of configs for each pin
129 */
130struct rockchip_pin_group {
131 const char *name;
132 unsigned int npins;
133 unsigned int *pins;
134 struct rockchip_pin_config *data;
135};
136
137/**
138 * struct rockchip_pmx_func: represent a pin function.
139 * @name: name of the pin function, used to lookup the function.
140 * @groups: one or more names of pin groups that provide this function.
141 * @num_groups: number of groups included in @groups.
142 */
143struct rockchip_pmx_func {
144 const char *name;
145 const char **groups;
146 u8 ngroups;
147};
148
149struct rockchip_pinctrl {
150 void __iomem *reg_base;
151 struct device *dev;
152 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl;
154 struct pinctrl_dev *pctl_dev;
155 struct rockchip_pin_group *groups;
156 unsigned int ngroups;
157 struct rockchip_pmx_func *functions;
158 unsigned int nfunctions;
159};
160
161static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
162{
163 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
164}
165
166static const inline struct rockchip_pin_group *pinctrl_name_to_group(
167 const struct rockchip_pinctrl *info,
168 const char *name)
169{
170 const struct rockchip_pin_group *grp = NULL;
171 int i;
172
173 for (i = 0; i < info->ngroups; i++) {
174 if (strcmp(info->groups[i].name, name))
175 continue;
176
177 grp = &info->groups[i];
178 break;
179 }
180
181 return grp;
182}
183
184/*
185 * given a pin number that is local to a pin controller, find out the pin bank
186 * and the register base of the pin bank.
187 */
188static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
189 unsigned pin)
190{
191 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
192
193 while ((pin >= b->pin_base) &&
194 ((b->pin_base + b->nr_pins - 1) < pin))
195 b++;
196
197 return b;
198}
199
200static struct rockchip_pin_bank *bank_num_to_bank(
201 struct rockchip_pinctrl *info,
202 unsigned num)
203{
204 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
205 int i;
206
207 for (i = 0; i < info->ctrl->nr_banks; i++) {
208 if (b->bank_num == num)
209 break;
210
211 b++;
212 }
213
214 if (b->bank_num != num)
215 return ERR_PTR(-EINVAL);
216
217 return b;
218}
219
220/*
221 * Pinctrl_ops handling
222 */
223
224static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
225{
226 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
227
228 return info->ngroups;
229}
230
231static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
232 unsigned selector)
233{
234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
235
236 return info->groups[selector].name;
237}
238
239static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
240 unsigned selector, const unsigned **pins,
241 unsigned *npins)
242{
243 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
244
245 if (selector >= info->ngroups)
246 return -EINVAL;
247
248 *pins = info->groups[selector].pins;
249 *npins = info->groups[selector].npins;
250
251 return 0;
252}
253
254static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
255 struct device_node *np,
256 struct pinctrl_map **map, unsigned *num_maps)
257{
258 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
259 const struct rockchip_pin_group *grp;
260 struct pinctrl_map *new_map;
261 struct device_node *parent;
262 int map_num = 1;
263 int i;
264
265 /*
266 * first find the group of this node and check if we need to create
267 * config maps for pins
268 */
269 grp = pinctrl_name_to_group(info, np->name);
270 if (!grp) {
271 dev_err(info->dev, "unable to find group for node %s\n",
272 np->name);
273 return -EINVAL;
274 }
275
276 map_num += grp->npins;
277 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
278 GFP_KERNEL);
279 if (!new_map)
280 return -ENOMEM;
281
282 *map = new_map;
283 *num_maps = map_num;
284
285 /* create mux map */
286 parent = of_get_parent(np);
287 if (!parent) {
288 devm_kfree(pctldev->dev, new_map);
289 return -EINVAL;
290 }
291 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
292 new_map[0].data.mux.function = parent->name;
293 new_map[0].data.mux.group = np->name;
294 of_node_put(parent);
295
296 /* create config map */
297 new_map++;
298 for (i = 0; i < grp->npins; i++) {
299 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
300 new_map[i].data.configs.group_or_pin =
301 pin_get_name(pctldev, grp->pins[i]);
302 new_map[i].data.configs.configs = grp->data[i].configs;
303 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
304 }
305
306 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
307 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
308
309 return 0;
310}
311
312static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
313 struct pinctrl_map *map, unsigned num_maps)
314{
315}
316
317static const struct pinctrl_ops rockchip_pctrl_ops = {
318 .get_groups_count = rockchip_get_groups_count,
319 .get_group_name = rockchip_get_group_name,
320 .get_group_pins = rockchip_get_group_pins,
321 .dt_node_to_map = rockchip_dt_node_to_map,
322 .dt_free_map = rockchip_dt_free_map,
323};
324
325/*
326 * Hardware access
327 */
328
329/*
330 * Set a new mux function for a pin.
331 *
332 * The register is divided into the upper and lower 16 bit. When changing
333 * a value, the previous register value is not read and changed. Instead
334 * it seems the changed bits are marked in the upper 16 bit, while the
335 * changed value gets set in the same offset in the lower 16 bit.
336 * All pin settings seem to be 2 bit wide in both the upper and lower
337 * parts.
338 * @bank: pin bank to change
339 * @pin: pin to change
340 * @mux: new mux function to set
341 */
342static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
343{
344 struct rockchip_pinctrl *info = bank->drvdata;
345 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
346 unsigned long flags;
347 u8 bit;
348 u32 data;
349
350 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
351 bank->bank_num, pin, mux);
352
353 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg += bank->bank_num * 0x10;
355 reg += (pin / 8) * 4;
356 bit = (pin % 8) * 2;
357
358 spin_lock_irqsave(&bank->slock, flags);
359
360 data = (3 << (bit + 16));
361 data |= (mux & 3) << bit;
362 writel(data, reg);
363
364 spin_unlock_irqrestore(&bank->slock, flags);
365}
366
367static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
368{
369 struct rockchip_pinctrl *info = bank->drvdata;
370 struct rockchip_pin_ctrl *ctrl = info->ctrl;
371 void __iomem *reg;
372 u8 bit;
373
374 /* rk3066b does support any pulls */
375 if (!ctrl->pull_offset)
376 return PIN_CONFIG_BIAS_DISABLE;
377
378 reg = info->reg_base + ctrl->pull_offset;
379
380 if (ctrl->pull_auto) {
381 reg += bank->bank_num * ctrl->pull_bank_stride;
382 reg += (pin_num / 16) * 4;
383 bit = pin_num % 16;
384
385 return !(readl_relaxed(reg) & BIT(bit))
386 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
387 : PIN_CONFIG_BIAS_DISABLE;
388 } else {
389 dev_err(info->dev, "pull support for rk31xx not implemented\n");
390 return -EIO;
391 }
392}
393
394static int rockchip_set_pull(struct rockchip_pin_bank *bank,
395 int pin_num, int pull)
396{
397 struct rockchip_pinctrl *info = bank->drvdata;
398 struct rockchip_pin_ctrl *ctrl = info->ctrl;
399 void __iomem *reg;
400 unsigned long flags;
401 u8 bit;
402 u32 data;
403
404 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
405 bank->bank_num, pin_num, pull);
406
407 /* rk3066b does support any pulls */
408 if (!ctrl->pull_offset)
409 return pull ? -EINVAL : 0;
410
411 reg = info->reg_base + ctrl->pull_offset;
412
413 if (ctrl->pull_auto) {
414 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
415 pull != PIN_CONFIG_BIAS_DISABLE) {
416 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
417 return -EINVAL;
418 }
419
420 reg += bank->bank_num * ctrl->pull_bank_stride;
421 reg += (pin_num / 16) * 4;
422 bit = pin_num % 16;
423
424 spin_lock_irqsave(&bank->slock, flags);
425
426 data = BIT(bit + 16);
427 if (pull == PIN_CONFIG_BIAS_DISABLE)
428 data |= BIT(bit);
429 writel(data, reg);
430
431 spin_unlock_irqrestore(&bank->slock, flags);
432 } else {
433 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
434 dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
435 return -EINVAL;
436 }
437
438 dev_err(info->dev, "pull support for rk31xx not implemented\n");
439 return -EIO;
440 }
441
442 return 0;
443}
444
445/*
446 * Pinmux_ops handling
447 */
448
449static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
450{
451 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
452
453 return info->nfunctions;
454}
455
456static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
457 unsigned selector)
458{
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
460
461 return info->functions[selector].name;
462}
463
464static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
465 unsigned selector, const char * const **groups,
466 unsigned * const num_groups)
467{
468 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
469
470 *groups = info->functions[selector].groups;
471 *num_groups = info->functions[selector].ngroups;
472
473 return 0;
474}
475
476static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
477 unsigned group)
478{
479 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
480 const unsigned int *pins = info->groups[group].pins;
481 const struct rockchip_pin_config *data = info->groups[group].data;
482 struct rockchip_pin_bank *bank;
483 int cnt;
484
485 dev_dbg(info->dev, "enable function %s group %s\n",
486 info->functions[selector].name, info->groups[group].name);
487
488 /*
489 * for each pin in the pin group selected, program the correspoding pin
490 * pin function number in the config register.
491 */
492 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
493 bank = pin_to_bank(info, pins[cnt]);
494 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
495 data[cnt].func);
496 }
497
498 return 0;
499}
500
501static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
502 unsigned selector, unsigned group)
503{
504 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
505 const unsigned int *pins = info->groups[group].pins;
506 struct rockchip_pin_bank *bank;
507 int cnt;
508
509 dev_dbg(info->dev, "disable function %s group %s\n",
510 info->functions[selector].name, info->groups[group].name);
511
512 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
513 bank = pin_to_bank(info, pins[cnt]);
514 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
515 }
516}
517
518/*
519 * The calls to gpio_direction_output() and gpio_direction_input()
520 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
521 * function called from the gpiolib interface).
522 */
523static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
524 struct pinctrl_gpio_range *range,
525 unsigned offset, bool input)
526{
527 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
528 struct rockchip_pin_bank *bank;
529 struct gpio_chip *chip;
530 int pin;
531 u32 data;
532
533 chip = range->gc;
534 bank = gc_to_pin_bank(chip);
535 pin = offset - chip->base;
536
537 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
538 offset, range->name, pin, input ? "input" : "output");
539
540 rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
541
542 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
543 /* set bit to 1 for output, 0 for input */
544 if (!input)
545 data |= BIT(pin);
546 else
547 data &= ~BIT(pin);
548 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
549
550 return 0;
551}
552
553static const struct pinmux_ops rockchip_pmx_ops = {
554 .get_functions_count = rockchip_pmx_get_funcs_count,
555 .get_function_name = rockchip_pmx_get_func_name,
556 .get_function_groups = rockchip_pmx_get_groups,
557 .enable = rockchip_pmx_enable,
558 .disable = rockchip_pmx_disable,
559 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
560};
561
562/*
563 * Pinconf_ops handling
564 */
565
566static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
567 enum pin_config_param pull)
568{
569 /* rk3066b does support any pulls */
570 if (!ctrl->pull_offset)
571 return pull ? false : true;
572
573 if (ctrl->pull_auto) {
574 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
575 pull != PIN_CONFIG_BIAS_DISABLE)
576 return false;
577 } else {
578 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
579 return false;
580 }
581
582 return true;
583}
584
585/* set the pin config settings for a specified pin */
586static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
587 unsigned long config)
588{
589 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
590 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
591 enum pin_config_param param = pinconf_to_config_param(config);
592 u16 arg = pinconf_to_config_argument(config);
593
594 switch (param) {
595 case PIN_CONFIG_BIAS_DISABLE:
596 return rockchip_set_pull(bank, pin - bank->pin_base, param);
597 break;
598 case PIN_CONFIG_BIAS_PULL_UP:
599 case PIN_CONFIG_BIAS_PULL_DOWN:
600 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
601 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
602 return -ENOTSUPP;
603
604 if (!arg)
605 return -EINVAL;
606
607 return rockchip_set_pull(bank, pin - bank->pin_base, param);
608 break;
609 default:
610 return -ENOTSUPP;
611 break;
612 }
613
614 return 0;
615}
616
617/* get the pin config settings for a specified pin */
618static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
619 unsigned long *config)
620{
621 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
622 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
623 enum pin_config_param param = pinconf_to_config_param(*config);
624
625 switch (param) {
626 case PIN_CONFIG_BIAS_DISABLE:
627 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
628 return -EINVAL;
629
630 *config = 0;
631 break;
632 case PIN_CONFIG_BIAS_PULL_UP:
633 case PIN_CONFIG_BIAS_PULL_DOWN:
634 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
635 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
636 return -ENOTSUPP;
637
638 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
639 return -EINVAL;
640
641 *config = 1;
642 break;
643 default:
644 return -ENOTSUPP;
645 break;
646 }
647
648 return 0;
649}
650
651static const struct pinconf_ops rockchip_pinconf_ops = {
652 .pin_config_get = rockchip_pinconf_get,
653 .pin_config_set = rockchip_pinconf_set,
654};
655
656static const char *gpio_compat = "rockchip,gpio-bank";
657
658static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
659 struct device_node *np)
660{
661 struct device_node *child;
662
663 for_each_child_of_node(np, child) {
664 if (of_device_is_compatible(child, gpio_compat))
665 continue;
666
667 info->nfunctions++;
668 info->ngroups += of_get_child_count(child);
669 }
670}
671
672static int rockchip_pinctrl_parse_groups(struct device_node *np,
673 struct rockchip_pin_group *grp,
674 struct rockchip_pinctrl *info,
675 u32 index)
676{
677 struct rockchip_pin_bank *bank;
678 int size;
679 const __be32 *list;
680 int num;
681 int i, j;
682 int ret;
683
684 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
685
686 /* Initialise group */
687 grp->name = np->name;
688
689 /*
690 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
691 * do sanity check and calculate pins number
692 */
693 list = of_get_property(np, "rockchip,pins", &size);
694 /* we do not check return since it's safe node passed down */
695 size /= sizeof(*list);
696 if (!size || size % 4) {
697 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
698 return -EINVAL;
699 }
700
701 grp->npins = size / 4;
702
703 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
704 GFP_KERNEL);
705 grp->data = devm_kzalloc(info->dev, grp->npins *
706 sizeof(struct rockchip_pin_config),
707 GFP_KERNEL);
708 if (!grp->pins || !grp->data)
709 return -ENOMEM;
710
711 for (i = 0, j = 0; i < size; i += 4, j++) {
712 const __be32 *phandle;
713 struct device_node *np_config;
714
715 num = be32_to_cpu(*list++);
716 bank = bank_num_to_bank(info, num);
717 if (IS_ERR(bank))
718 return PTR_ERR(bank);
719
720 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
721 grp->data[j].func = be32_to_cpu(*list++);
722
723 phandle = list++;
724 if (!phandle)
725 return -EINVAL;
726
727 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
728 ret = pinconf_generic_parse_dt_config(np_config,
729 &grp->data[j].configs, &grp->data[j].nconfigs);
730 if (ret)
731 return ret;
732 }
733
734 return 0;
735}
736
737static int rockchip_pinctrl_parse_functions(struct device_node *np,
738 struct rockchip_pinctrl *info,
739 u32 index)
740{
741 struct device_node *child;
742 struct rockchip_pmx_func *func;
743 struct rockchip_pin_group *grp;
744 int ret;
745 static u32 grp_index;
746 u32 i = 0;
747
748 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
749
750 func = &info->functions[index];
751
752 /* Initialise function */
753 func->name = np->name;
754 func->ngroups = of_get_child_count(np);
755 if (func->ngroups <= 0)
756 return 0;
757
758 func->groups = devm_kzalloc(info->dev,
759 func->ngroups * sizeof(char *), GFP_KERNEL);
760 if (!func->groups)
761 return -ENOMEM;
762
763 for_each_child_of_node(np, child) {
764 func->groups[i] = child->name;
765 grp = &info->groups[grp_index++];
766 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
767 if (ret)
768 return ret;
769 }
770
771 return 0;
772}
773
774static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
775 struct rockchip_pinctrl *info)
776{
777 struct device *dev = &pdev->dev;
778 struct device_node *np = dev->of_node;
779 struct device_node *child;
780 int ret;
781 int i;
782
783 rockchip_pinctrl_child_count(info, np);
784
785 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
786 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
787
788 info->functions = devm_kzalloc(dev, info->nfunctions *
789 sizeof(struct rockchip_pmx_func),
790 GFP_KERNEL);
791 if (!info->functions) {
792 dev_err(dev, "failed to allocate memory for function list\n");
793 return -EINVAL;
794 }
795
796 info->groups = devm_kzalloc(dev, info->ngroups *
797 sizeof(struct rockchip_pin_group),
798 GFP_KERNEL);
799 if (!info->groups) {
800 dev_err(dev, "failed allocate memory for ping group list\n");
801 return -EINVAL;
802 }
803
804 i = 0;
805
806 for_each_child_of_node(np, child) {
807 if (of_device_is_compatible(child, gpio_compat))
808 continue;
809 ret = rockchip_pinctrl_parse_functions(child, info, i++);
810 if (ret) {
811 dev_err(&pdev->dev, "failed to parse function\n");
812 return ret;
813 }
814 }
815
816 return 0;
817}
818
819static int rockchip_pinctrl_register(struct platform_device *pdev,
820 struct rockchip_pinctrl *info)
821{
822 struct pinctrl_desc *ctrldesc = &info->pctl;
823 struct pinctrl_pin_desc *pindesc, *pdesc;
824 struct rockchip_pin_bank *pin_bank;
825 int pin, bank, ret;
826 int k;
827
828 ctrldesc->name = "rockchip-pinctrl";
829 ctrldesc->owner = THIS_MODULE;
830 ctrldesc->pctlops = &rockchip_pctrl_ops;
831 ctrldesc->pmxops = &rockchip_pmx_ops;
832 ctrldesc->confops = &rockchip_pinconf_ops;
833
834 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
835 info->ctrl->nr_pins, GFP_KERNEL);
836 if (!pindesc) {
837 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
838 return -ENOMEM;
839 }
840 ctrldesc->pins = pindesc;
841 ctrldesc->npins = info->ctrl->nr_pins;
842
843 pdesc = pindesc;
844 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
845 pin_bank = &info->ctrl->pin_banks[bank];
846 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
847 pdesc->number = k;
848 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
849 pin_bank->name, pin);
850 pdesc++;
851 }
852 }
853
854 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
855 if (!info->pctl_dev) {
856 dev_err(&pdev->dev, "could not register pinctrl driver\n");
857 return -EINVAL;
858 }
859
860 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
861 pin_bank = &info->ctrl->pin_banks[bank];
862 pin_bank->grange.name = pin_bank->name;
863 pin_bank->grange.id = bank;
864 pin_bank->grange.pin_base = pin_bank->pin_base;
865 pin_bank->grange.base = pin_bank->gpio_chip.base;
866 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
867 pin_bank->grange.gc = &pin_bank->gpio_chip;
868 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
869 }
870
871 ret = rockchip_pinctrl_parse_dt(pdev, info);
872 if (ret) {
873 pinctrl_unregister(info->pctl_dev);
874 return ret;
875 }
876
877 return 0;
878}
879
880/*
881 * GPIO handling
882 */
883
884static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
885{
886 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
887 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
888 unsigned long flags;
889 u32 data;
890
891 spin_lock_irqsave(&bank->slock, flags);
892
893 data = readl(reg);
894 data &= ~BIT(offset);
895 if (value)
896 data |= BIT(offset);
897 writel(data, reg);
898
899 spin_unlock_irqrestore(&bank->slock, flags);
900}
901
902/*
903 * Returns the level of the pin for input direction and setting of the DR
904 * register for output gpios.
905 */
906static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
907{
908 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
909 u32 data;
910
911 data = readl(bank->reg_base + GPIO_EXT_PORT);
912 data >>= offset;
913 data &= 1;
914 return data;
915}
916
917/*
918 * gpiolib gpio_direction_input callback function. The setting of the pin
919 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
920 * interface.
921 */
922static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
923{
924 return pinctrl_gpio_direction_input(gc->base + offset);
925}
926
927/*
928 * gpiolib gpio_direction_output callback function. The setting of the pin
929 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
930 * interface.
931 */
932static int rockchip_gpio_direction_output(struct gpio_chip *gc,
933 unsigned offset, int value)
934{
935 rockchip_gpio_set(gc, offset, value);
936 return pinctrl_gpio_direction_output(gc->base + offset);
937}
938
939/*
940 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
941 * and a virtual IRQ, if not already present.
942 */
943static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
944{
945 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
946 unsigned int virq;
947
948 if (!bank->domain)
949 return -ENXIO;
950
951 virq = irq_create_mapping(bank->domain, offset);
952
953 return (virq) ? : -ENXIO;
954}
955
956static const struct gpio_chip rockchip_gpiolib_chip = {
957 .set = rockchip_gpio_set,
958 .get = rockchip_gpio_get,
959 .direction_input = rockchip_gpio_direction_input,
960 .direction_output = rockchip_gpio_direction_output,
961 .to_irq = rockchip_gpio_to_irq,
962 .owner = THIS_MODULE,
963};
964
965/*
966 * Interrupt handling
967 */
968
969static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
970{
971 struct irq_chip *chip = irq_get_chip(irq);
972 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
973 u32 pend;
974
975 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
976
977 chained_irq_enter(chip, desc);
978
979 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
980
981 while (pend) {
982 unsigned int virq;
983
984 irq = __ffs(pend);
985 pend &= ~BIT(irq);
986 virq = irq_linear_revmap(bank->domain, irq);
987
988 if (!virq) {
989 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
990 continue;
991 }
992
993 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
994
995 generic_handle_irq(virq);
996 }
997
998 chained_irq_exit(chip, desc);
999}
1000
1001static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1002{
1003 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1004 struct rockchip_pin_bank *bank = gc->private;
1005 u32 mask = BIT(d->hwirq);
1006 u32 polarity;
1007 u32 level;
1008 u32 data;
1009
1010 if (type & IRQ_TYPE_EDGE_BOTH)
1011 __irq_set_handler_locked(d->irq, handle_edge_irq);
1012 else
1013 __irq_set_handler_locked(d->irq, handle_level_irq);
1014
1015 irq_gc_lock(gc);
1016
1017 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1018 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1019
1020 switch (type) {
1021 case IRQ_TYPE_EDGE_RISING:
1022 level |= mask;
1023 polarity |= mask;
1024 break;
1025 case IRQ_TYPE_EDGE_FALLING:
1026 level |= mask;
1027 polarity &= ~mask;
1028 break;
1029 case IRQ_TYPE_LEVEL_HIGH:
1030 level &= ~mask;
1031 polarity |= mask;
1032 break;
1033 case IRQ_TYPE_LEVEL_LOW:
1034 level &= ~mask;
1035 polarity &= ~mask;
1036 break;
1037 default:
1038 irq_gc_unlock(gc);
1039 return -EINVAL;
1040 }
1041
1042 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1043 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1044
1045 irq_gc_unlock(gc);
1046
1047 /* make sure the pin is configured as gpio input */
1048 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1049 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1050 data &= ~mask;
1051 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1052
1053 return 0;
1054}
1055
1056static int rockchip_interrupts_register(struct platform_device *pdev,
1057 struct rockchip_pinctrl *info)
1058{
1059 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1060 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1061 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1062 struct irq_chip_generic *gc;
1063 int ret;
1064 int i;
1065
1066 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1067 if (!bank->valid) {
1068 dev_warn(&pdev->dev, "bank %s is not valid\n",
1069 bank->name);
1070 continue;
1071 }
1072
1073 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1074 &irq_generic_chip_ops, NULL);
1075 if (!bank->domain) {
1076 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1077 bank->name);
1078 continue;
1079 }
1080
1081 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1082 "rockchip_gpio_irq", handle_level_irq,
1083 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1084 if (ret) {
1085 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1086 bank->name);
1087 irq_domain_remove(bank->domain);
1088 continue;
1089 }
1090
1091 gc = irq_get_domain_generic_chip(bank->domain, 0);
1092 gc->reg_base = bank->reg_base;
1093 gc->private = bank;
1094 gc->chip_types[0].regs.mask = GPIO_INTEN;
1095 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1096 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1097 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1098 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1099 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1100 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1101
1102 irq_set_handler_data(bank->irq, bank);
1103 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1104 }
1105
1106 return 0;
1107}
1108
1109static int rockchip_gpiolib_register(struct platform_device *pdev,
1110 struct rockchip_pinctrl *info)
1111{
1112 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1113 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1114 struct gpio_chip *gc;
1115 int ret;
1116 int i;
1117
1118 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1119 if (!bank->valid) {
1120 dev_warn(&pdev->dev, "bank %s is not valid\n",
1121 bank->name);
1122 continue;
1123 }
1124
1125 bank->gpio_chip = rockchip_gpiolib_chip;
1126
1127 gc = &bank->gpio_chip;
1128 gc->base = bank->pin_base;
1129 gc->ngpio = bank->nr_pins;
1130 gc->dev = &pdev->dev;
1131 gc->of_node = bank->of_node;
1132 gc->label = bank->name;
1133
1134 ret = gpiochip_add(gc);
1135 if (ret) {
1136 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1137 gc->label, ret);
1138 goto fail;
1139 }
1140 }
1141
1142 rockchip_interrupts_register(pdev, info);
1143
1144 return 0;
1145
1146fail:
1147 for (--i, --bank; i >= 0; --i, --bank) {
1148 if (!bank->valid)
1149 continue;
1150
1151 if (gpiochip_remove(&bank->gpio_chip))
1152 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1153 bank->gpio_chip.label);
1154 }
1155 return ret;
1156}
1157
1158static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1159 struct rockchip_pinctrl *info)
1160{
1161 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1162 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1163 int ret = 0;
1164 int i;
1165
1166 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1167 if (!bank->valid)
1168 continue;
1169
1170 ret = gpiochip_remove(&bank->gpio_chip);
1171 }
1172
1173 if (ret)
1174 dev_err(&pdev->dev, "gpio chip remove failed\n");
1175
1176 return ret;
1177}
1178
1179static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1180 struct device *dev)
1181{
1182 struct resource res;
1183
1184 if (of_address_to_resource(bank->of_node, 0, &res)) {
1185 dev_err(dev, "cannot find IO resource for bank\n");
1186 return -ENOENT;
1187 }
1188
1189 bank->reg_base = devm_ioremap_resource(dev, &res);
1190 if (IS_ERR(bank->reg_base))
1191 return PTR_ERR(bank->reg_base);
1192
1193 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1194
1195 bank->clk = of_clk_get(bank->of_node, 0);
1196 if (IS_ERR(bank->clk))
1197 return PTR_ERR(bank->clk);
1198
1199 return clk_prepare_enable(bank->clk);
1200}
1201
1202static const struct of_device_id rockchip_pinctrl_dt_match[];
1203
1204/* retrieve the soc specific data */
1205static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1206 struct rockchip_pinctrl *d,
1207 struct platform_device *pdev)
1208{
1209 const struct of_device_id *match;
1210 struct device_node *node = pdev->dev.of_node;
1211 struct device_node *np;
1212 struct rockchip_pin_ctrl *ctrl;
1213 struct rockchip_pin_bank *bank;
1214 int i;
1215
1216 match = of_match_node(rockchip_pinctrl_dt_match, node);
1217 ctrl = (struct rockchip_pin_ctrl *)match->data;
1218
1219 for_each_child_of_node(node, np) {
1220 if (!of_find_property(np, "gpio-controller", NULL))
1221 continue;
1222
1223 bank = ctrl->pin_banks;
1224 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1225 if (!strcmp(bank->name, np->name)) {
1226 bank->of_node = np;
1227
1228 if (!rockchip_get_bank_data(bank, &pdev->dev))
1229 bank->valid = true;
1230
1231 break;
1232 }
1233 }
1234 }
1235
1236 bank = ctrl->pin_banks;
1237 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1238 spin_lock_init(&bank->slock);
1239 bank->drvdata = d;
1240 bank->pin_base = ctrl->nr_pins;
1241 ctrl->nr_pins += bank->nr_pins;
1242 }
1243
1244 return ctrl;
1245}
1246
1247static int rockchip_pinctrl_probe(struct platform_device *pdev)
1248{
1249 struct rockchip_pinctrl *info;
1250 struct device *dev = &pdev->dev;
1251 struct rockchip_pin_ctrl *ctrl;
1252 struct resource *res;
1253 int ret;
1254
1255 if (!dev->of_node) {
1256 dev_err(dev, "device tree node not found\n");
1257 return -ENODEV;
1258 }
1259
1260 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1261 if (!info)
1262 return -ENOMEM;
1263
1264 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1265 if (!ctrl) {
1266 dev_err(dev, "driver data not available\n");
1267 return -EINVAL;
1268 }
1269 info->ctrl = ctrl;
1270 info->dev = dev;
1271
1272 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1273 if (!res) {
1274 dev_err(dev, "cannot find IO resource\n");
1275 return -ENOENT;
1276 }
1277
1278 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1279 if (IS_ERR(info->reg_base))
1280 return PTR_ERR(info->reg_base);
1281
1282 ret = rockchip_gpiolib_register(pdev, info);
1283 if (ret)
1284 return ret;
1285
1286 ret = rockchip_pinctrl_register(pdev, info);
1287 if (ret) {
1288 rockchip_gpiolib_unregister(pdev, info);
1289 return ret;
1290 }
1291
1292 platform_set_drvdata(pdev, info);
1293
1294 return 0;
1295}
1296
1297static struct rockchip_pin_bank rk2928_pin_banks[] = {
1298 PIN_BANK(0, 32, "gpio0"),
1299 PIN_BANK(1, 32, "gpio1"),
1300 PIN_BANK(2, 32, "gpio2"),
1301 PIN_BANK(3, 32, "gpio3"),
1302};
1303
1304static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1305 .pin_banks = rk2928_pin_banks,
1306 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1307 .label = "RK2928-GPIO",
1308 .mux_offset = 0xa8,
1309 .pull_offset = 0x118,
1310 .pull_auto = 1,
1311 .pull_bank_stride = 8,
1312};
1313
1314static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1315 PIN_BANK(0, 32, "gpio0"),
1316 PIN_BANK(1, 32, "gpio1"),
1317 PIN_BANK(2, 32, "gpio2"),
1318 PIN_BANK(3, 32, "gpio3"),
1319 PIN_BANK(4, 32, "gpio4"),
1320 PIN_BANK(6, 16, "gpio6"),
1321};
1322
1323static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1324 .pin_banks = rk3066a_pin_banks,
1325 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1326 .label = "RK3066a-GPIO",
1327 .mux_offset = 0xa8,
1328 .pull_offset = 0x118,
1329 .pull_auto = 1,
1330 .pull_bank_stride = 8,
1331};
1332
1333static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1334 PIN_BANK(0, 32, "gpio0"),
1335 PIN_BANK(1, 32, "gpio1"),
1336 PIN_BANK(2, 32, "gpio2"),
1337 PIN_BANK(3, 32, "gpio3"),
1338};
1339
1340static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1341 .pin_banks = rk3066b_pin_banks,
1342 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1343 .label = "RK3066b-GPIO",
1344 .mux_offset = 0x60,
1345 .pull_offset = -EINVAL,
1346};
1347
1348static struct rockchip_pin_bank rk3188_pin_banks[] = {
1349 PIN_BANK(0, 32, "gpio0"),
1350 PIN_BANK(1, 32, "gpio1"),
1351 PIN_BANK(2, 32, "gpio2"),
1352 PIN_BANK(3, 32, "gpio3"),
1353};
1354
1355static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1356 .pin_banks = rk3188_pin_banks,
1357 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1358 .label = "RK3188-GPIO",
1359 .mux_offset = 0x68,
1360 .pull_offset = 0x164,
1361 .pull_bank_stride = 16,
1362};
1363
1364static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1365 { .compatible = "rockchip,rk2928-pinctrl",
1366 .data = (void *)&rk2928_pin_ctrl },
1367 { .compatible = "rockchip,rk3066a-pinctrl",
1368 .data = (void *)&rk3066a_pin_ctrl },
1369 { .compatible = "rockchip,rk3066b-pinctrl",
1370 .data = (void *)&rk3066b_pin_ctrl },
1371 { .compatible = "rockchip,rk3188-pinctrl",
1372 .data = (void *)&rk3188_pin_ctrl },
1373 {},
1374};
1375MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1376
1377static struct platform_driver rockchip_pinctrl_driver = {
1378 .probe = rockchip_pinctrl_probe,
1379 .driver = {
1380 .name = "rockchip-pinctrl",
1381 .owner = THIS_MODULE,
1382 .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match),
1383 },
1384};
1385
1386static int __init rockchip_pinctrl_drv_register(void)
1387{
1388 return platform_driver_register(&rockchip_pinctrl_driver);
1389}
1390postcore_initcall(rockchip_pinctrl_drv_register);
1391
1392MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1393MODULE_DESCRIPTION("Rockchip pinctrl driver");
1394MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 0a6c720b6655..a7fa9e2d4751 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -50,7 +50,7 @@ static struct pin_config {
50}; 50};
51 51
52/* Global list of devices (struct samsung_pinctrl_drv_data) */ 52/* Global list of devices (struct samsung_pinctrl_drv_data) */
53LIST_HEAD(drvdata_list); 53static LIST_HEAD(drvdata_list);
54 54
55static unsigned int pin_base; 55static unsigned int pin_base;
56 56
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index b9fa04618601..6866548fab31 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -30,7 +30,7 @@
30#define DRIVER_NAME "pinctrl-single" 30#define DRIVER_NAME "pinctrl-single"
31#define PCS_MUX_PINS_NAME "pinctrl-single,pins" 31#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
32#define PCS_MUX_BITS_NAME "pinctrl-single,bits" 32#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
33#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) 33#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
34#define PCS_OFF_DISABLED ~0U 34#define PCS_OFF_DISABLED ~0U
35 35
36/** 36/**
@@ -163,6 +163,7 @@ struct pcs_name {
163 * @foff: value to turn mux off 163 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask 164 * @fmax: max number of functions in fmask
165 * @is_pinconf: whether supports pinconf 165 * @is_pinconf: whether supports pinconf
166 * @bits_per_pin:number of bits per pin
166 * @names: array of register names for pins 167 * @names: array of register names for pins
167 * @pins: physical pins on the SoC 168 * @pins: physical pins on the SoC
168 * @pgtree: pingroup index radix tree 169 * @pgtree: pingroup index radix tree
@@ -190,6 +191,7 @@ struct pcs_device {
190 unsigned fmax; 191 unsigned fmax;
191 bool bits_per_mux; 192 bool bits_per_mux;
192 bool is_pinconf; 193 bool is_pinconf;
194 unsigned bits_per_pin;
193 struct pcs_name *names; 195 struct pcs_name *names;
194 struct pcs_data pins; 196 struct pcs_data pins;
195 struct radix_tree_root pgtree; 197 struct radix_tree_root pgtree;
@@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
431 433
432 vals = &func->vals[i]; 434 vals = &func->vals[i];
433 val = pcs->read(vals->reg); 435 val = pcs->read(vals->reg);
434 if (!vals->mask) 436
435 mask = pcs->fmask; 437 if (pcs->bits_per_mux)
438 mask = vals->mask;
436 else 439 else
437 mask = pcs->fmask & vals->mask; 440 mask = pcs->fmask;
438 441
439 val &= ~mask; 442 val &= ~mask;
440 val |= (vals->val & mask); 443 val |= (vals->val & mask);
@@ -741,7 +744,8 @@ static const struct pinconf_ops pcs_pinconf_ops = {
741 * @pcs: pcs driver instance 744 * @pcs: pcs driver instance
742 * @offset: register offset from base 745 * @offset: register offset from base
743 */ 746 */
744static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) 747static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
748 unsigned pin_pos)
745{ 749{
746 struct pinctrl_pin_desc *pin; 750 struct pinctrl_pin_desc *pin;
747 struct pcs_name *pn; 751 struct pcs_name *pn;
@@ -756,8 +760,8 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset)
756 760
757 pin = &pcs->pins.pa[i]; 761 pin = &pcs->pins.pa[i];
758 pn = &pcs->names[i]; 762 pn = &pcs->names[i];
759 sprintf(pn->name, "%lx", 763 sprintf(pn->name, "%lx.%d",
760 (unsigned long)pcs->res->start + offset); 764 (unsigned long)pcs->res->start + offset, pin_pos);
761 pin->name = pn->name; 765 pin->name = pn->name;
762 pin->number = i; 766 pin->number = i;
763 pcs->pins.cur++; 767 pcs->pins.cur++;
@@ -777,9 +781,17 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset)
777static int pcs_allocate_pin_table(struct pcs_device *pcs) 781static int pcs_allocate_pin_table(struct pcs_device *pcs)
778{ 782{
779 int mux_bytes, nr_pins, i; 783 int mux_bytes, nr_pins, i;
784 int num_pins_in_register = 0;
780 785
781 mux_bytes = pcs->width / BITS_PER_BYTE; 786 mux_bytes = pcs->width / BITS_PER_BYTE;
782 nr_pins = pcs->size / mux_bytes; 787
788 if (pcs->bits_per_mux) {
789 pcs->bits_per_pin = fls(pcs->fmask);
790 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
791 num_pins_in_register = pcs->width / pcs->bits_per_pin;
792 } else {
793 nr_pins = pcs->size / mux_bytes;
794 }
783 795
784 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); 796 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
785 pcs->pins.pa = devm_kzalloc(pcs->dev, 797 pcs->pins.pa = devm_kzalloc(pcs->dev,
@@ -800,9 +812,17 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
800 for (i = 0; i < pcs->desc.npins; i++) { 812 for (i = 0; i < pcs->desc.npins; i++) {
801 unsigned offset; 813 unsigned offset;
802 int res; 814 int res;
803 815 int byte_num;
804 offset = i * mux_bytes; 816 int pin_pos = 0;
805 res = pcs_add_pin(pcs, offset); 817
818 if (pcs->bits_per_mux) {
819 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
820 offset = (byte_num / mux_bytes) * mux_bytes;
821 pin_pos = i % num_pins_in_register;
822 } else {
823 offset = i * mux_bytes;
824 }
825 res = pcs_add_pin(pcs, offset, pin_pos);
806 if (res < 0) { 826 if (res < 0) {
807 dev_err(pcs->dev, "error adding pins: %i\n", res); 827 dev_err(pcs->dev, "error adding pins: %i\n", res);
808 return res; 828 return res;
@@ -919,7 +939,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
919 return -EINVAL; 939 return -EINVAL;
920 } 940 }
921 941
922 index = offset / (pcs->width / BITS_PER_BYTE); 942 if (pcs->bits_per_mux)
943 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
944 else
945 index = offset / (pcs->width / BITS_PER_BYTE);
923 946
924 return index; 947 return index;
925} 948}
@@ -1097,29 +1120,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1097{ 1120{
1098 struct pcs_func_vals *vals; 1121 struct pcs_func_vals *vals;
1099 const __be32 *mux; 1122 const __be32 *mux;
1100 int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; 1123 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1101 struct pcs_function *function; 1124 struct pcs_function *function;
1102 1125
1103 if (pcs->bits_per_mux) { 1126 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1104 params = 3; 1127 if ((!mux) || (size < sizeof(*mux) * 2)) {
1105 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); 1128 dev_err(pcs->dev, "bad data for mux %s\n",
1106 } else { 1129 np->name);
1107 params = 2;
1108 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1109 }
1110
1111 if (!mux) {
1112 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1113 return -EINVAL;
1114 }
1115
1116 if (size < (sizeof(*mux) * params)) {
1117 dev_err(pcs->dev, "bad data for %s\n", np->name);
1118 return -EINVAL; 1130 return -EINVAL;
1119 } 1131 }
1120 1132
1121 size /= sizeof(*mux); /* Number of elements in array */ 1133 size /= sizeof(*mux); /* Number of elements in array */
1122 rows = size / params; 1134 rows = size / 2;
1123 1135
1124 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); 1136 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1125 if (!vals) 1137 if (!vals)
@@ -1137,10 +1149,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1137 val = be32_to_cpup(mux + index++); 1149 val = be32_to_cpup(mux + index++);
1138 vals[found].reg = pcs->base + offset; 1150 vals[found].reg = pcs->base + offset;
1139 vals[found].val = val; 1151 vals[found].val = val;
1140 if (params == 3) {
1141 val = be32_to_cpup(mux + index++);
1142 vals[found].mask = val;
1143 }
1144 1152
1145 pin = pcs_get_pin_by_offset(pcs, offset); 1153 pin = pcs_get_pin_by_offset(pcs, offset);
1146 if (pin < 0) { 1154 if (pin < 0) {
@@ -1189,6 +1197,125 @@ free_vals:
1189 1197
1190 return res; 1198 return res;
1191} 1199}
1200
1201#define PARAMS_FOR_BITS_PER_MUX 3
1202
1203static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1204 struct device_node *np,
1205 struct pinctrl_map **map,
1206 unsigned *num_maps,
1207 const char **pgnames)
1208{
1209 struct pcs_func_vals *vals;
1210 const __be32 *mux;
1211 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1212 int npins_in_row;
1213 struct pcs_function *function;
1214
1215 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1216
1217 if (!mux) {
1218 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1219 return -EINVAL;
1220 }
1221
1222 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1223 dev_err(pcs->dev, "bad data for %s\n", np->name);
1224 return -EINVAL;
1225 }
1226
1227 /* Number of elements in array */
1228 size /= sizeof(*mux);
1229
1230 rows = size / PARAMS_FOR_BITS_PER_MUX;
1231 npins_in_row = pcs->width / pcs->bits_per_pin;
1232
1233 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1234 GFP_KERNEL);
1235 if (!vals)
1236 return -ENOMEM;
1237
1238 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1239 GFP_KERNEL);
1240 if (!pins)
1241 goto free_vals;
1242
1243 while (index < size) {
1244 unsigned offset, val;
1245 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1246 unsigned pin_num_from_lsb;
1247 int pin;
1248
1249 offset = be32_to_cpup(mux + index++);
1250 val = be32_to_cpup(mux + index++);
1251 mask = be32_to_cpup(mux + index++);
1252
1253 /* Parse pins in each row from LSB */
1254 while (mask) {
1255 bit_pos = ffs(mask);
1256 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1257 mask_pos = ((pcs->fmask) << (bit_pos - 1));
1258 val_pos = val & mask_pos;
1259 submask = mask & mask_pos;
1260 mask &= ~mask_pos;
1261
1262 if (submask != mask_pos) {
1263 dev_warn(pcs->dev,
1264 "Invalid submask 0x%x for %s at 0x%x\n",
1265 submask, np->name, offset);
1266 continue;
1267 }
1268
1269 vals[found].mask = submask;
1270 vals[found].reg = pcs->base + offset;
1271 vals[found].val = val_pos;
1272
1273 pin = pcs_get_pin_by_offset(pcs, offset);
1274 if (pin < 0) {
1275 dev_err(pcs->dev,
1276 "could not add functions for %s %ux\n",
1277 np->name, offset);
1278 break;
1279 }
1280 pins[found++] = pin + pin_num_from_lsb;
1281 }
1282 }
1283
1284 pgnames[0] = np->name;
1285 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1286 if (!function)
1287 goto free_pins;
1288
1289 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1290 if (res < 0)
1291 goto free_function;
1292
1293 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1294 (*map)->data.mux.group = np->name;
1295 (*map)->data.mux.function = np->name;
1296
1297 if (pcs->is_pinconf) {
1298 dev_err(pcs->dev, "pinconf not supported\n");
1299 goto free_pingroups;
1300 }
1301
1302 *num_maps = 1;
1303 return 0;
1304
1305free_pingroups:
1306 pcs_free_pingroups(pcs);
1307 *num_maps = 1;
1308free_function:
1309 pcs_remove_function(pcs, function);
1310
1311free_pins:
1312 devm_kfree(pcs->dev, pins);
1313
1314free_vals:
1315 devm_kfree(pcs->dev, vals);
1316
1317 return res;
1318}
1192/** 1319/**
1193 * pcs_dt_node_to_map() - allocates and parses pinctrl maps 1320 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1194 * @pctldev: pinctrl instance 1321 * @pctldev: pinctrl instance
@@ -1219,12 +1346,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1219 goto free_map; 1346 goto free_map;
1220 } 1347 }
1221 1348
1222 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, 1349 if (pcs->bits_per_mux) {
1223 pgnames); 1350 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1224 if (ret < 0) { 1351 num_maps, pgnames);
1225 dev_err(pcs->dev, "no pins entries for %s\n", 1352 if (ret < 0) {
1226 np_config->name); 1353 dev_err(pcs->dev, "no pins entries for %s\n",
1227 goto free_pgnames; 1354 np_config->name);
1355 goto free_pgnames;
1356 }
1357 } else {
1358 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1359 num_maps, pgnames);
1360 if (ret < 0) {
1361 dev_err(pcs->dev, "no pins entries for %s\n",
1362 np_config->name);
1363 goto free_pgnames;
1364 }
1228 } 1365 }
1229 1366
1230 return 0; 1367 return 0;
@@ -1346,6 +1483,29 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1346 return ret; 1483 return ret;
1347} 1484}
1348 1485
1486static int pinctrl_single_suspend(struct platform_device *pdev,
1487 pm_message_t state)
1488{
1489 struct pcs_device *pcs;
1490
1491 pcs = platform_get_drvdata(pdev);
1492 if (!pcs)
1493 return -EINVAL;
1494
1495 return pinctrl_force_sleep(pcs->pctl);
1496}
1497
1498static int pinctrl_single_resume(struct platform_device *pdev)
1499{
1500 struct pcs_device *pcs;
1501
1502 pcs = platform_get_drvdata(pdev);
1503 if (!pcs)
1504 return -EINVAL;
1505
1506 return pinctrl_force_default(pcs->pctl);
1507}
1508
1349static int pcs_probe(struct platform_device *pdev) 1509static int pcs_probe(struct platform_device *pdev)
1350{ 1510{
1351 struct device_node *np = pdev->dev.of_node; 1511 struct device_node *np = pdev->dev.of_node;
@@ -1494,6 +1654,10 @@ static struct platform_driver pcs_driver = {
1494 .name = DRIVER_NAME, 1654 .name = DRIVER_NAME,
1495 .of_match_table = pcs_of_match, 1655 .of_match_table = pcs_of_match,
1496 }, 1656 },
1657#ifdef CONFIG_PM
1658 .suspend = pinctrl_single_suspend,
1659 .resume = pinctrl_single_resume,
1660#endif
1497}; 1661};
1498 1662
1499module_platform_driver(pcs_driver); 1663module_platform_driver(pcs_driver);
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
new file mode 100644
index 000000000000..2eeae0c066c4
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -0,0 +1,2023 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_PINS_H
14#define __PINCTRL_SUNXI_PINS_H
15
16#include "pinctrl-sunxi.h"
17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005};
1006
1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1642 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
1643 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1644 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
1645};
1646
1647static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1648 /* Hole */
1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1660 SUNXI_FUNCTION(0x2, "pwm"),
1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1672 /* Hole */
1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1678 /* Hole */
1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1695 /* Hole */
1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1774 /* Hole */
1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1780 /* Hole */
1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1805 /* Hole */
1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1830 /* Hole */
1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1871 /* Hole */
1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1931 /* Hole */
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1981 /* Hole */
1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2001 SUNXI_FUNCTION(0x0, "gpio_in"),
2002 SUNXI_FUNCTION(0x1, "gpio_out"),
2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2004 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
2006};
2007
2008static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
2009 .pins = sun4i_a10_pins,
2010 .npins = ARRAY_SIZE(sun4i_a10_pins),
2011};
2012
2013static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
2014 .pins = sun5i_a10s_pins,
2015 .npins = ARRAY_SIZE(sun5i_a10s_pins),
2016};
2017
2018static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
2019 .pins = sun5i_a13_pins,
2020 .npins = ARRAY_SIZE(sun5i_a13_pins),
2021};
2022
2023#endif /* __PINCTRL_SUNXI_PINS_H */
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index b7d8c890514c..c47fd1e5450b 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -13,10 +13,12 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/irqdomain.h>
16#include <linux/module.h> 17#include <linux/module.h>
17#include <linux/of.h> 18#include <linux/of.h>
18#include <linux/of_address.h> 19#include <linux/of_address.h>
19#include <linux/of_device.h> 20#include <linux/of_device.h>
21#include <linux/of_irq.h>
20#include <linux/pinctrl/consumer.h> 22#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/machine.h> 23#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinctrl.h>
@@ -27,1319 +29,7 @@
27 29
28#include "core.h" 30#include "core.h"
29#include "pinctrl-sunxi.h" 31#include "pinctrl-sunxi.h"
30 32#include "pinctrl-sunxi-pins.h"
31static const struct sunxi_desc_pin sun4i_a10_pins[] = {
32 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
36 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
37 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
42 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
43 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
48 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
49 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
54 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
55 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
56 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
60 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
65 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
66 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
67 SUNXI_FUNCTION(0x0, "gpio_in"),
68 SUNXI_FUNCTION(0x1, "gpio_out"),
69 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
70 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
75 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
80 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
85 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
90 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
95 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
100 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
101 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
102 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
103 SUNXI_FUNCTION(0x0, "gpio_in"),
104 SUNXI_FUNCTION(0x1, "gpio_out"),
105 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
106 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
107 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
108 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
109 SUNXI_FUNCTION(0x0, "gpio_in"),
110 SUNXI_FUNCTION(0x1, "gpio_out"),
111 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
112 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
113 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
115 SUNXI_FUNCTION(0x0, "gpio_in"),
116 SUNXI_FUNCTION(0x1, "gpio_out"),
117 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
118 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
119 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
124 SUNXI_FUNCTION(0x3, "can"), /* TX */
125 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
127 SUNXI_FUNCTION(0x0, "gpio_in"),
128 SUNXI_FUNCTION(0x1, "gpio_out"),
129 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
130 SUNXI_FUNCTION(0x3, "can"), /* RX */
131 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
132 /* Hole */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
157 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
162 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
167 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
172 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
189 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
198 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
203 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
208 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
213 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out"),
217 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
218 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
219 SUNXI_FUNCTION(0x0, "gpio_in"),
220 SUNXI_FUNCTION(0x1, "gpio_out"),
221 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
227 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out"),
229 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
234 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
239 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
240 /* Hole */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
245 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
250 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
255 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
257 SUNXI_FUNCTION(0x0, "gpio_in"),
258 SUNXI_FUNCTION(0x1, "gpio_out"),
259 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
292 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
297 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out"),
305 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
330 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
335 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
340 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
345 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
346 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
354 /* Hole */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
359 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
364 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
366 SUNXI_FUNCTION(0x0, "gpio_in"),
367 SUNXI_FUNCTION(0x1, "gpio_out"),
368 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
369 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
374 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
399 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
404 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
409 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
414 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
419 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
424 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
449 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
454 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
459 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
464 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
469 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
474 SUNXI_FUNCTION(0x3, "sim")), /* DET */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
479 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
484 SUNXI_FUNCTION(0x3, "sim")), /* RST */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
489 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
494 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
495 /* Hole */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
500 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
502 SUNXI_FUNCTION(0x0, "gpio_in"),
503 SUNXI_FUNCTION(0x1, "gpio_out"),
504 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
505 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
507 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out"),
509 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
510 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
515 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
520 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
525 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
526 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
531 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
536 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
538 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out"),
540 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
541 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
542 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
543 SUNXI_FUNCTION(0x0, "gpio_in"),
544 SUNXI_FUNCTION(0x1, "gpio_out"),
545 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
546 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
547 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
548 SUNXI_FUNCTION(0x0, "gpio_in"),
549 SUNXI_FUNCTION(0x1, "gpio_out"),
550 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
551 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
553 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out"),
555 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
556 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
557 /* Hole */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
562 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
572 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
577 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
578 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
579 SUNXI_FUNCTION(0x0, "gpio_in"),
580 SUNXI_FUNCTION(0x1, "gpio_out"),
581 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
582 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out"),
586 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
587 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
588 /* Hole */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
590 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
593 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
594 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
596 SUNXI_FUNCTION(0x0, "gpio_in"),
597 SUNXI_FUNCTION(0x1, "gpio_out"),
598 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
599 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
600 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
602 SUNXI_FUNCTION(0x0, "gpio_in"),
603 SUNXI_FUNCTION(0x1, "gpio_out"),
604 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
605 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
606 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
611 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
612 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
613 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
614 SUNXI_FUNCTION(0x0, "gpio_in"),
615 SUNXI_FUNCTION(0x1, "gpio_out"),
616 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
617 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
618 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
619 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
621 SUNXI_FUNCTION(0x0, "gpio_in"),
622 SUNXI_FUNCTION(0x1, "gpio_out"),
623 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
624 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
625 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
626 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
628 SUNXI_FUNCTION(0x0, "gpio_in"),
629 SUNXI_FUNCTION(0x1, "gpio_out"),
630 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
631 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
632 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
633 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out"),
637 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
638 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
639 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
640 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
642 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
645 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
646 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
647 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
649 SUNXI_FUNCTION(0x0, "gpio_in"),
650 SUNXI_FUNCTION(0x1, "gpio_out"),
651 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
652 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
653 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
654 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
655 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
656 SUNXI_FUNCTION(0x0, "gpio_in"),
657 SUNXI_FUNCTION(0x1, "gpio_out"),
658 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
659 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
660 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
661 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
663 SUNXI_FUNCTION(0x0, "gpio_in"),
664 SUNXI_FUNCTION(0x1, "gpio_out"),
665 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
666 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
667 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
668 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
669 /* Hole */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
671 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
674 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
675 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
676 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
678 SUNXI_FUNCTION(0x0, "gpio_in"),
679 SUNXI_FUNCTION(0x1, "gpio_out"),
680 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
681 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
682 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
683 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
684 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
685 SUNXI_FUNCTION(0x0, "gpio_in"),
686 SUNXI_FUNCTION(0x1, "gpio_out"),
687 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
688 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
689 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
690 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
692 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out"),
694 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
695 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
696 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
697 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
698 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
699 SUNXI_FUNCTION(0x0, "gpio_in"),
700 SUNXI_FUNCTION(0x1, "gpio_out"),
701 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
702 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
703 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
710 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
711 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
713 SUNXI_FUNCTION(0x0, "gpio_in"),
714 SUNXI_FUNCTION(0x1, "gpio_out"),
715 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
716 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
717 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
718 SUNXI_FUNCTION(0x5, "ms"), /* BS */
719 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
721 SUNXI_FUNCTION(0x0, "gpio_in"),
722 SUNXI_FUNCTION(0x1, "gpio_out"),
723 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
724 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
725 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
726 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
727 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
729 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out"),
731 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
732 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
733 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
734 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
735 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
736 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
737 SUNXI_FUNCTION(0x0, "gpio_in"),
738 SUNXI_FUNCTION(0x1, "gpio_out"),
739 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
740 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
741 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
742 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
743 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
745 SUNXI_FUNCTION(0x0, "gpio_in"),
746 SUNXI_FUNCTION(0x1, "gpio_out"),
747 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
748 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
749 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
750 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
751 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
752 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
753 SUNXI_FUNCTION(0x0, "gpio_in"),
754 SUNXI_FUNCTION(0x1, "gpio_out"),
755 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
756 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
757 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
758 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
759 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
761 SUNXI_FUNCTION(0x0, "gpio_in"),
762 SUNXI_FUNCTION(0x1, "gpio_out"),
763 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
764 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
765 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
776 SUNXI_FUNCTION(0x0, "gpio_in"),
777 SUNXI_FUNCTION(0x1, "gpio_out"),
778 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
779 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
780 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
781 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
782 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
783 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
784 SUNXI_FUNCTION(0x0, "gpio_in"),
785 SUNXI_FUNCTION(0x1, "gpio_out"),
786 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
787 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
788 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
789 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
790 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
791 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
792 SUNXI_FUNCTION(0x0, "gpio_in"),
793 SUNXI_FUNCTION(0x1, "gpio_out"),
794 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
795 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
796 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
797 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
799 SUNXI_FUNCTION(0x0, "gpio_in"),
800 SUNXI_FUNCTION(0x1, "gpio_out"),
801 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
802 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
803 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
804 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
805 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
807 SUNXI_FUNCTION(0x0, "gpio_in"),
808 SUNXI_FUNCTION(0x1, "gpio_out"),
809 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
810 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
811 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
812 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
813 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out"),
817 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
818 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
819 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
820 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
821 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
823 SUNXI_FUNCTION(0x0, "gpio_in"),
824 SUNXI_FUNCTION(0x1, "gpio_out"),
825 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
826 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
827 SUNXI_FUNCTION(0x4, "can"), /* TX */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
834 SUNXI_FUNCTION(0x4, "can"), /* RX */
835 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
836 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
837 SUNXI_FUNCTION(0x0, "gpio_in"),
838 SUNXI_FUNCTION(0x1, "gpio_out"),
839 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
840 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
841 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
842 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
843 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
844 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
845 SUNXI_FUNCTION(0x0, "gpio_in"),
846 SUNXI_FUNCTION(0x1, "gpio_out"),
847 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
848 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
849 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
850 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
851 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
852 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
853 SUNXI_FUNCTION(0x0, "gpio_in"),
854 SUNXI_FUNCTION(0x1, "gpio_out"),
855 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
856 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
857 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
858 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
859 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
860 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
861 SUNXI_FUNCTION(0x0, "gpio_in"),
862 SUNXI_FUNCTION(0x1, "gpio_out"),
863 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
864 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
865 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
866 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
867 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
868 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
869 SUNXI_FUNCTION(0x0, "gpio_in"),
870 SUNXI_FUNCTION(0x1, "gpio_out"),
871 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
872 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
873 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
874 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
875 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
877 SUNXI_FUNCTION(0x0, "gpio_in"),
878 SUNXI_FUNCTION(0x1, "gpio_out"),
879 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
880 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
881 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
882 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
883 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
884 /* Hole */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out")),
888 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
889 SUNXI_FUNCTION(0x0, "gpio_in"),
890 SUNXI_FUNCTION(0x1, "gpio_out")),
891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
892 SUNXI_FUNCTION(0x0, "gpio_in"),
893 SUNXI_FUNCTION(0x1, "gpio_out")),
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out"),
897 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
898 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
899 SUNXI_FUNCTION(0x0, "gpio_in"),
900 SUNXI_FUNCTION(0x1, "gpio_out"),
901 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
902 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
903 SUNXI_FUNCTION(0x0, "gpio_in"),
904 SUNXI_FUNCTION(0x1, "gpio_out"),
905 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
907 SUNXI_FUNCTION(0x0, "gpio_in"),
908 SUNXI_FUNCTION(0x1, "gpio_out"),
909 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
910 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
911 SUNXI_FUNCTION(0x0, "gpio_in"),
912 SUNXI_FUNCTION(0x1, "gpio_out"),
913 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
914 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
915 SUNXI_FUNCTION(0x0, "gpio_in"),
916 SUNXI_FUNCTION(0x1, "gpio_out"),
917 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
918 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
919 SUNXI_FUNCTION(0x0, "gpio_in"),
920 SUNXI_FUNCTION(0x1, "gpio_out"),
921 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
922 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
923 SUNXI_FUNCTION(0x0, "gpio_in"),
924 SUNXI_FUNCTION(0x1, "gpio_out"),
925 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
926 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
931 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
933 SUNXI_FUNCTION(0x0, "gpio_in"),
934 SUNXI_FUNCTION(0x1, "gpio_out"),
935 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
936 SUNXI_FUNCTION(0x3, "uart6")), /* TX */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
941 SUNXI_FUNCTION(0x3, "uart6")), /* RX */
942 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
943 SUNXI_FUNCTION(0x0, "gpio_in"),
944 SUNXI_FUNCTION(0x1, "gpio_out"),
945 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
946 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
947 SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */
948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
949 SUNXI_FUNCTION(0x0, "gpio_in"),
950 SUNXI_FUNCTION(0x1, "gpio_out"),
951 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
952 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
953 SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */
954 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
955 SUNXI_FUNCTION(0x0, "gpio_in"),
956 SUNXI_FUNCTION(0x1, "gpio_out"),
957 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
958 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
959 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
960 SUNXI_FUNCTION(0x0, "gpio_in"),
961 SUNXI_FUNCTION(0x1, "gpio_out"),
962 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
963 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
964 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
965 SUNXI_FUNCTION(0x0, "gpio_in"),
966 SUNXI_FUNCTION(0x1, "gpio_out"),
967 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
968 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
973 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
974 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
975 SUNXI_FUNCTION(0x0, "gpio_in"),
976 SUNXI_FUNCTION(0x1, "gpio_out"),
977 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
978 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
979 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
980 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
981 SUNXI_FUNCTION(0x0, "gpio_in"),
982 SUNXI_FUNCTION(0x1, "gpio_out"),
983 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
984 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
985 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
986};
987
988static const struct sunxi_desc_pin sun5i_a13_pins[] = {
989 /* Hole */
990 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
991 SUNXI_FUNCTION(0x0, "gpio_in"),
992 SUNXI_FUNCTION(0x1, "gpio_out"),
993 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
995 SUNXI_FUNCTION(0x0, "gpio_in"),
996 SUNXI_FUNCTION(0x1, "gpio_out"),
997 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
998 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
999 SUNXI_FUNCTION(0x0, "gpio_in"),
1000 SUNXI_FUNCTION(0x1, "gpio_out"),
1001 SUNXI_FUNCTION(0x2, "pwm")),
1002 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1003 SUNXI_FUNCTION(0x0, "gpio_in"),
1004 SUNXI_FUNCTION(0x1, "gpio_out"),
1005 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
1006 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1007 SUNXI_FUNCTION(0x0, "gpio_in"),
1008 SUNXI_FUNCTION(0x1, "gpio_out"),
1009 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
1010 /* Hole */
1011 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1012 SUNXI_FUNCTION(0x0, "gpio_in"),
1013 SUNXI_FUNCTION(0x1, "gpio_out"),
1014 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
1015 /* Hole */
1016 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1017 SUNXI_FUNCTION(0x0, "gpio_in"),
1018 SUNXI_FUNCTION(0x1, "gpio_out"),
1019 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1024 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1025 SUNXI_FUNCTION(0x0, "gpio_in"),
1026 SUNXI_FUNCTION(0x1, "gpio_out"),
1027 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1028 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1029 SUNXI_FUNCTION(0x0, "gpio_in"),
1030 SUNXI_FUNCTION(0x1, "gpio_out"),
1031 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1032 /* Hole */
1033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1034 SUNXI_FUNCTION(0x0, "gpio_in"),
1035 SUNXI_FUNCTION(0x1, "gpio_out"),
1036 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1037 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1042 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1043 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1044 SUNXI_FUNCTION(0x0, "gpio_in"),
1045 SUNXI_FUNCTION(0x1, "gpio_out"),
1046 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1047 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1048 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1049 SUNXI_FUNCTION(0x0, "gpio_in"),
1050 SUNXI_FUNCTION(0x1, "gpio_out"),
1051 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1052 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1053 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1054 SUNXI_FUNCTION(0x0, "gpio_in"),
1055 SUNXI_FUNCTION(0x1, "gpio_out"),
1056 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1058 SUNXI_FUNCTION(0x0, "gpio_in"),
1059 SUNXI_FUNCTION(0x1, "gpio_out"),
1060 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1062 SUNXI_FUNCTION(0x0, "gpio_in"),
1063 SUNXI_FUNCTION(0x1, "gpio_out"),
1064 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1065 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1066 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1067 SUNXI_FUNCTION(0x0, "gpio_in"),
1068 SUNXI_FUNCTION(0x1, "gpio_out"),
1069 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1070 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1071 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1072 SUNXI_FUNCTION(0x0, "gpio_in"),
1073 SUNXI_FUNCTION(0x1, "gpio_out"),
1074 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1075 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1077 SUNXI_FUNCTION(0x0, "gpio_in"),
1078 SUNXI_FUNCTION(0x1, "gpio_out"),
1079 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1080 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1081 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1082 SUNXI_FUNCTION(0x0, "gpio_in"),
1083 SUNXI_FUNCTION(0x1, "gpio_out"),
1084 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1085 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1086 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1087 SUNXI_FUNCTION(0x0, "gpio_in"),
1088 SUNXI_FUNCTION(0x1, "gpio_out"),
1089 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1090 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1091 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1092 SUNXI_FUNCTION(0x0, "gpio_in"),
1093 SUNXI_FUNCTION(0x1, "gpio_out"),
1094 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1095 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1100 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1102 SUNXI_FUNCTION(0x0, "gpio_in"),
1103 SUNXI_FUNCTION(0x1, "gpio_out"),
1104 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1105 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1107 SUNXI_FUNCTION(0x0, "gpio_in"),
1108 SUNXI_FUNCTION(0x1, "gpio_out"),
1109 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1110 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1111 /* Hole */
1112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1113 SUNXI_FUNCTION(0x0, "gpio_in"),
1114 SUNXI_FUNCTION(0x1, "gpio_out"),
1115 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1116 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1117 /* Hole */
1118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1119 SUNXI_FUNCTION(0x0, "gpio_in"),
1120 SUNXI_FUNCTION(0x1, "gpio_out"),
1121 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1134 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1135 SUNXI_FUNCTION(0x0, "gpio_in"),
1136 SUNXI_FUNCTION(0x1, "gpio_out"),
1137 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1138 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1139 SUNXI_FUNCTION(0x0, "gpio_in"),
1140 SUNXI_FUNCTION(0x1, "gpio_out"),
1141 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1142 /* Hole */
1143 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1144 SUNXI_FUNCTION(0x0, "gpio_in"),
1145 SUNXI_FUNCTION(0x1, "gpio_out"),
1146 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1147 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1148 SUNXI_FUNCTION(0x0, "gpio_in"),
1149 SUNXI_FUNCTION(0x1, "gpio_out"),
1150 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1152 SUNXI_FUNCTION(0x0, "gpio_in"),
1153 SUNXI_FUNCTION(0x1, "gpio_out"),
1154 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1159 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1160 SUNXI_FUNCTION(0x0, "gpio_in"),
1161 SUNXI_FUNCTION(0x1, "gpio_out"),
1162 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1163 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1164 SUNXI_FUNCTION(0x0, "gpio_in"),
1165 SUNXI_FUNCTION(0x1, "gpio_out"),
1166 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1167 /* Hole */
1168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1169 SUNXI_FUNCTION(0x0, "gpio_in"),
1170 SUNXI_FUNCTION(0x1, "gpio_out"),
1171 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1173 SUNXI_FUNCTION(0x0, "gpio_in"),
1174 SUNXI_FUNCTION(0x1, "gpio_out"),
1175 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1176 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1177 SUNXI_FUNCTION(0x0, "gpio_in"),
1178 SUNXI_FUNCTION(0x1, "gpio_out"),
1179 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1180 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1181 SUNXI_FUNCTION(0x0, "gpio_in"),
1182 SUNXI_FUNCTION(0x1, "gpio_out"),
1183 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1185 SUNXI_FUNCTION(0x0, "gpio_in"),
1186 SUNXI_FUNCTION(0x1, "gpio_out"),
1187 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1188 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1189 SUNXI_FUNCTION(0x0, "gpio_in"),
1190 SUNXI_FUNCTION(0x1, "gpio_out"),
1191 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1193 SUNXI_FUNCTION(0x0, "gpio_in"),
1194 SUNXI_FUNCTION(0x1, "gpio_out"),
1195 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1197 SUNXI_FUNCTION(0x0, "gpio_in"),
1198 SUNXI_FUNCTION(0x1, "gpio_out"),
1199 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1201 SUNXI_FUNCTION(0x0, "gpio_in"),
1202 SUNXI_FUNCTION(0x1, "gpio_out"),
1203 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1205 SUNXI_FUNCTION(0x0, "gpio_in"),
1206 SUNXI_FUNCTION(0x1, "gpio_out"),
1207 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1208 /* Hole */
1209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1210 SUNXI_FUNCTION(0x0, "gpio_in"),
1211 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1212 SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */
1213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1214 SUNXI_FUNCTION(0x0, "gpio_in"),
1215 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1216 SUNXI_FUNCTION(0x4, "spi2")), /* CLK */
1217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1218 SUNXI_FUNCTION(0x0, "gpio_in"),
1219 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1220 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1221 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1222 SUNXI_FUNCTION(0x0, "gpio_in"),
1223 SUNXI_FUNCTION(0x1, "gpio_out"),
1224 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1225 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1230 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1235 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1240 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1245 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1250 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1252 SUNXI_FUNCTION(0x0, "gpio_in"),
1253 SUNXI_FUNCTION(0x1, "gpio_out"),
1254 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1255 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1257 SUNXI_FUNCTION(0x0, "gpio_in"),
1258 SUNXI_FUNCTION(0x1, "gpio_out"),
1259 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1260 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1261 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1262 SUNXI_FUNCTION(0x0, "gpio_in"),
1263 SUNXI_FUNCTION(0x1, "gpio_out"),
1264 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1265 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1266 /* Hole */
1267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1268 SUNXI_FUNCTION(0x0, "gpio_in"),
1269 SUNXI_FUNCTION(0x1, "gpio_out"),
1270 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
1271 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1272 SUNXI_FUNCTION(0x0, "gpio_in"),
1273 SUNXI_FUNCTION(0x1, "gpio_out"),
1274 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
1275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1276 SUNXI_FUNCTION(0x0, "gpio_in"),
1277 SUNXI_FUNCTION(0x1, "gpio_out"),
1278 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
1283 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1284 SUNXI_FUNCTION(0x0, "gpio_in"),
1285 SUNXI_FUNCTION(0x1, "gpio_out"),
1286 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
1287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1288 SUNXI_FUNCTION(0x0, "gpio_in"),
1289 SUNXI_FUNCTION(0x1, "gpio_out"),
1290 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
1291 /* Hole */
1292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1293 SUNXI_FUNCTION(0x0, "gpio_in"),
1294 SUNXI_FUNCTION(0x1, "gpio_out")),
1295 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1296 SUNXI_FUNCTION(0x0, "gpio_in"),
1297 SUNXI_FUNCTION(0x1, "gpio_out")),
1298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1299 SUNXI_FUNCTION(0x0, "gpio_in"),
1300 SUNXI_FUNCTION(0x1, "gpio_out")),
1301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1302 SUNXI_FUNCTION(0x0, "gpio_in"),
1303 SUNXI_FUNCTION(0x1, "gpio_out"),
1304 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1305 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1306 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1307 SUNXI_FUNCTION(0x0, "gpio_in"),
1308 SUNXI_FUNCTION(0x1, "gpio_out"),
1309 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1310 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1311/* Hole */
1312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1313 SUNXI_FUNCTION(0x0, "gpio_in"),
1314 SUNXI_FUNCTION(0x1, "gpio_out"),
1315 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1316 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
1317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1318 SUNXI_FUNCTION(0x0, "gpio_in"),
1319 SUNXI_FUNCTION(0x1, "gpio_out"),
1320 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1321 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
1322 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1323 SUNXI_FUNCTION(0x0, "gpio_in"),
1324 SUNXI_FUNCTION(0x1, "gpio_out"),
1325 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1326 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1331 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
1332};
1333
1334static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1335 .pins = sun4i_a10_pins,
1336 .npins = ARRAY_SIZE(sun4i_a10_pins),
1337};
1338
1339static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
1340 .pins = sun5i_a13_pins,
1341 .npins = ARRAY_SIZE(sun5i_a13_pins),
1342};
1343 33
1344static struct sunxi_pinctrl_group * 34static struct sunxi_pinctrl_group *
1345sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
@@ -1399,6 +89,31 @@ sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
1399 return NULL; 89 return NULL;
1400} 90}
1401 91
92static struct sunxi_desc_function *
93sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
94 const u16 pin_num,
95 const char *func_name)
96{
97 int i;
98
99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
101
102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions;
104
105 while (func->name) {
106 if (!strcmp(func->name, func_name))
107 return func;
108
109 func++;
110 }
111 }
112 }
113
114 return NULL;
115}
116
1402static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 117static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
1403{ 118{
1404 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@@ -1680,37 +395,20 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1680{ 395{
1681 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 396 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1682 struct sunxi_desc_function *desc; 397 struct sunxi_desc_function *desc;
1683 char pin_name[SUNXI_PIN_NAME_MAX_LEN];
1684 const char *func; 398 const char *func;
1685 u8 bank, pin;
1686 int ret;
1687
1688 bank = (offset) / PINS_PER_BANK;
1689 pin = (offset) % PINS_PER_BANK;
1690
1691 ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin);
1692 if (!ret)
1693 goto error;
1694 399
1695 if (input) 400 if (input)
1696 func = "gpio_in"; 401 func = "gpio_in";
1697 else 402 else
1698 func = "gpio_out"; 403 func = "gpio_out";
1699 404
1700 desc = sunxi_pinctrl_desc_find_function_by_name(pctl, 405 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
1701 pin_name, 406 if (!desc)
1702 func); 407 return -EINVAL;
1703 if (!desc) {
1704 ret = -EINVAL;
1705 goto error;
1706 }
1707 408
1708 sunxi_pmx_set(pctldev, offset, desc->muxval); 409 sunxi_pmx_set(pctldev, offset, desc->muxval);
1709 410
1710 ret = 0; 411 return 0;
1711
1712error:
1713 return ret;
1714} 412}
1715 413
1716static const struct pinmux_ops sunxi_pmx_ops = { 414static const struct pinmux_ops sunxi_pmx_ops = {
@@ -1788,6 +486,26 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
1788 return pin; 486 return pin;
1789} 487}
1790 488
489static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
490{
491 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
492 struct sunxi_desc_function *desc;
493
494 if (offset > chip->ngpio)
495 return -ENXIO;
496
497 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
498 if (!desc)
499 return -EINVAL;
500
501 pctl->irq_array[desc->irqnum] = offset;
502
503 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
504 chip->label, offset + chip->base, desc->irqnum);
505
506 return irq_find_mapping(pctl->domain, desc->irqnum);
507}
508
1791static struct gpio_chip sunxi_pinctrl_gpio_chip = { 509static struct gpio_chip sunxi_pinctrl_gpio_chip = {
1792 .owner = THIS_MODULE, 510 .owner = THIS_MODULE,
1793 .request = sunxi_pinctrl_gpio_request, 511 .request = sunxi_pinctrl_gpio_request,
@@ -1797,12 +515,121 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip = {
1797 .get = sunxi_pinctrl_gpio_get, 515 .get = sunxi_pinctrl_gpio_get,
1798 .set = sunxi_pinctrl_gpio_set, 516 .set = sunxi_pinctrl_gpio_set,
1799 .of_xlate = sunxi_pinctrl_gpio_of_xlate, 517 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
518 .to_irq = sunxi_pinctrl_gpio_to_irq,
1800 .of_gpio_n_cells = 3, 519 .of_gpio_n_cells = 3,
1801 .can_sleep = 0, 520 .can_sleep = 0,
1802}; 521};
1803 522
523static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
524 unsigned int type)
525{
526 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
527 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
528 u8 index = sunxi_irq_cfg_offset(d->hwirq);
529 u8 mode;
530
531 switch (type) {
532 case IRQ_TYPE_EDGE_RISING:
533 mode = IRQ_EDGE_RISING;
534 break;
535 case IRQ_TYPE_EDGE_FALLING:
536 mode = IRQ_EDGE_FALLING;
537 break;
538 case IRQ_TYPE_EDGE_BOTH:
539 mode = IRQ_EDGE_BOTH;
540 break;
541 case IRQ_TYPE_LEVEL_HIGH:
542 mode = IRQ_LEVEL_HIGH;
543 break;
544 case IRQ_TYPE_LEVEL_LOW:
545 mode = IRQ_LEVEL_LOW;
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
552
553 return 0;
554}
555
556static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
557{
558 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
559 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
560 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
561 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
562 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
563 u32 val;
564
565 /* Mask the IRQ */
566 val = readl(pctl->membase + ctrl_reg);
567 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
568
569 /* Clear the IRQ */
570 writel(1 << status_idx, pctl->membase + status_reg);
571}
572
573static void sunxi_pinctrl_irq_mask(struct irq_data *d)
574{
575 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
576 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
577 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
578 u32 val;
579
580 /* Mask the IRQ */
581 val = readl(pctl->membase + reg);
582 writel(val & ~(1 << idx), pctl->membase + reg);
583}
584
585static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
586{
587 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
588 struct sunxi_desc_function *func;
589 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
590 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
591 u32 val;
592
593 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
594 pctl->irq_array[d->hwirq],
595 "irq");
596
597 /* Change muxing to INT mode */
598 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
599
600 /* Unmask the IRQ */
601 val = readl(pctl->membase + reg);
602 writel(val | (1 << idx), pctl->membase + reg);
603}
604
605static struct irq_chip sunxi_pinctrl_irq_chip = {
606 .irq_mask = sunxi_pinctrl_irq_mask,
607 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
608 .irq_unmask = sunxi_pinctrl_irq_unmask,
609 .irq_set_type = sunxi_pinctrl_irq_set_type,
610};
611
612static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
613{
614 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
615 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
616
617 /* Clear all interrupts */
618 writel(reg, pctl->membase + IRQ_STATUS_REG);
619
620 if (reg) {
621 int irqoffset;
622
623 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
624 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
625 generic_handle_irq(pin_irq);
626 }
627 }
628}
629
1804static struct of_device_id sunxi_pinctrl_match[] = { 630static struct of_device_id sunxi_pinctrl_match[] = {
1805 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, 631 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
632 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
1806 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, 633 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
1807 {} 634 {}
1808}; 635};
@@ -1997,6 +824,31 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
1997 824
1998 clk_prepare_enable(clk); 825 clk_prepare_enable(clk);
1999 826
827 pctl->irq = irq_of_parse_and_map(node, 0);
828 if (!pctl->irq) {
829 ret = -EINVAL;
830 goto gpiochip_error;
831 }
832
833 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
834 &irq_domain_simple_ops, NULL);
835 if (!pctl->domain) {
836 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
837 ret = -ENOMEM;
838 goto gpiochip_error;
839 }
840
841 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
842 int irqno = irq_create_mapping(pctl->domain, i);
843
844 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
845 handle_simple_irq);
846 irq_set_chip_data(irqno, pctl);
847 };
848
849 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
850 irq_set_handler_data(pctl->irq, pctl);
851
2000 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 852 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
2001 853
2002 return 0; 854 return 0;
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index e921621059ce..d68047d8f699 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -344,9 +344,31 @@
344#define PULL_PINS_BITS 2 344#define PULL_PINS_BITS 2
345#define PULL_PINS_MASK 0x03 345#define PULL_PINS_MASK 0x03
346 346
347#define SUNXI_IRQ_NUMBER 32
348
349#define IRQ_CFG_REG 0x200
350#define IRQ_CFG_IRQ_PER_REG 8
351#define IRQ_CFG_IRQ_BITS 4
352#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
353#define IRQ_CTRL_REG 0x210
354#define IRQ_CTRL_IRQ_PER_REG 32
355#define IRQ_CTRL_IRQ_BITS 1
356#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
357#define IRQ_STATUS_REG 0x214
358#define IRQ_STATUS_IRQ_PER_REG 32
359#define IRQ_STATUS_IRQ_BITS 1
360#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
361
362#define IRQ_EDGE_RISING 0x00
363#define IRQ_EDGE_FALLING 0x01
364#define IRQ_LEVEL_HIGH 0x02
365#define IRQ_LEVEL_LOW 0x03
366#define IRQ_EDGE_BOTH 0x04
367
347struct sunxi_desc_function { 368struct sunxi_desc_function {
348 const char *name; 369 const char *name;
349 u8 muxval; 370 u8 muxval;
371 u8 irqnum;
350}; 372};
351 373
352struct sunxi_desc_pin { 374struct sunxi_desc_pin {
@@ -378,10 +400,13 @@ struct sunxi_pinctrl {
378 struct gpio_chip *chip; 400 struct gpio_chip *chip;
379 struct sunxi_pinctrl_desc *desc; 401 struct sunxi_pinctrl_desc *desc;
380 struct device *dev; 402 struct device *dev;
403 struct irq_domain *domain;
381 struct sunxi_pinctrl_function *functions; 404 struct sunxi_pinctrl_function *functions;
382 unsigned nfunctions; 405 unsigned nfunctions;
383 struct sunxi_pinctrl_group *groups; 406 struct sunxi_pinctrl_group *groups;
384 unsigned ngroups; 407 unsigned ngroups;
408 int irq;
409 int irq_array[SUNXI_IRQ_NUMBER];
385 struct pinctrl_dev *pctl_dev; 410 struct pinctrl_dev *pctl_dev;
386}; 411};
387 412
@@ -398,6 +423,13 @@ struct sunxi_pinctrl {
398 .muxval = _val, \ 423 .muxval = _val, \
399 } 424 }
400 425
426#define SUNXI_FUNCTION_IRQ(_val, _irq) \
427 { \
428 .name = "irq", \
429 .muxval = _val, \
430 .irqnum = _irq, \
431 }
432
401/* 433/*
402 * The sunXi PIO registers are organized as is: 434 * The sunXi PIO registers are organized as is:
403 * 0x00 - 0x0c Muxing values. 435 * 0x00 - 0x0c Muxing values.
@@ -475,4 +507,40 @@ static inline u32 sunxi_pull_offset(u16 pin)
475 return pin_num * PULL_PINS_BITS; 507 return pin_num * PULL_PINS_BITS;
476} 508}
477 509
510static inline u32 sunxi_irq_cfg_reg(u16 irq)
511{
512 u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
513 return reg + IRQ_CFG_REG;
514}
515
516static inline u32 sunxi_irq_cfg_offset(u16 irq)
517{
518 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
519 return irq_num * IRQ_CFG_IRQ_BITS;
520}
521
522static inline u32 sunxi_irq_ctrl_reg(u16 irq)
523{
524 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
525 return reg + IRQ_CTRL_REG;
526}
527
528static inline u32 sunxi_irq_ctrl_offset(u16 irq)
529{
530 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
531 return irq_num * IRQ_CTRL_IRQ_BITS;
532}
533
534static inline u32 sunxi_irq_status_reg(u16 irq)
535{
536 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
537 return reg + IRQ_STATUS_REG;
538}
539
540static inline u32 sunxi_irq_status_offset(u16 irq)
541{
542 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
543 return irq_num * IRQ_STATUS_IRQ_BITS;
544}
545
478#endif /* __PINCTRL_SUNXI_H */ 546#endif /* __PINCTRL_SUNXI_H */
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
new file mode 100644
index 000000000000..d4f12cc556b4
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -0,0 +1,1024 @@
1/*
2 * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
3 *
4 * Copyright (c) 2013, Imagination Technologies Ltd.
5 *
6 * Derived from Tegra code:
7 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Derived from code:
10 * Copyright (C) 2010 Google, Inc.
11 * Copyright (C) 2010 NVIDIA Corporation
12 * Copyright (C) 2009-2011 ST-Ericsson AB
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms and conditions of the GNU General Public License,
16 * version 2, as published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/bitops.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pinctrl/machine.h>
30#include <linux/pinctrl/pinconf-generic.h>
31#include <linux/pinctrl/pinctrl.h>
32#include <linux/pinctrl/pinmux.h>
33#include <linux/slab.h>
34
35/*
36 * The registers may be shared with other threads/cores, so we need to use the
37 * metag global lock2 for atomicity.
38 */
39#include <asm/global_lock.h>
40
41#include "core.h"
42#include "pinconf.h"
43
44/* Register offsets from bank base address */
45#define REG_GPIO_CONTROL0 0x00
46#define REG_GPIO_CONTROL2 0x08
47
48/* Register field information */
49#define REG_GPIO_CONTROL2_PU_PD_S 16
50#define REG_GPIO_CONTROL2_PDC_POS_S 4
51#define REG_GPIO_CONTROL2_PDC_DR_S 2
52#define REG_GPIO_CONTROL2_PDC_SR_S 1
53#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
54
55/* PU_PD field values */
56#define REG_PU_PD_TRISTATE 0
57#define REG_PU_PD_UP 1
58#define REG_PU_PD_DOWN 2
59#define REG_PU_PD_REPEATER 3
60
61/* DR field values */
62#define REG_DR_2mA 0
63#define REG_DR_4mA 1
64#define REG_DR_8mA 2
65#define REG_DR_12mA 3
66
67/**
68 * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
69 * @name: The name of the function, exported to pinctrl core.
70 * @groups: An array of pin groups that may select this function.
71 * @ngroups: The number of entries in @groups.
72 */
73struct tz1090_pdc_function {
74 const char *name;
75 const char * const *groups;
76 unsigned int ngroups;
77};
78
79/**
80 * struct tz1090_pdc_pingroup - TZ1090 PDC pin group
81 * @name: Name of pin group.
82 * @pins: Array of pin numbers in this pin group.
83 * @npins: Number of pins in this pin group.
84 * @func: Function enabled by the mux.
85 * @reg: Mux register offset.
86 * @bit: Mux register bit.
87 * @drv: Drive control supported, otherwise it's a mux.
88 * This means Schmitt, Slew, and Drive strength.
89 *
90 * A representation of a group of pins (possibly just one pin) in the TZ1090
91 * PDC pin controller. Each group allows some parameter or parameters to be
92 * configured. The most common is mux function selection.
93 */
94struct tz1090_pdc_pingroup {
95 const char *name;
96 const unsigned int *pins;
97 unsigned int npins;
98 int func;
99 u16 reg;
100 u8 bit;
101 bool drv;
102};
103
104/*
105 * All PDC pins can be GPIOs. Define these first to match how the GPIO driver
106 * names/numbers its pins.
107 */
108
109enum tz1090_pdc_pin {
110 TZ1090_PDC_PIN_GPIO0,
111 TZ1090_PDC_PIN_GPIO1,
112 TZ1090_PDC_PIN_SYS_WAKE0,
113 TZ1090_PDC_PIN_SYS_WAKE1,
114 TZ1090_PDC_PIN_SYS_WAKE2,
115 TZ1090_PDC_PIN_IR_DATA,
116 TZ1090_PDC_PIN_EXT_POWER,
117};
118
119/* Pin names */
120
121static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
122 /* PDC GPIOs */
123 PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
124 PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
125 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
126 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
127 PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
128 PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
129 PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
130};
131
132/* Pin group pins */
133
134static const unsigned int gpio0_pins[] = {
135 TZ1090_PDC_PIN_GPIO0,
136};
137
138static const unsigned int gpio1_pins[] = {
139 TZ1090_PDC_PIN_GPIO1,
140};
141
142static const unsigned int pdc_pins[] = {
143 TZ1090_PDC_PIN_GPIO0,
144 TZ1090_PDC_PIN_GPIO1,
145 TZ1090_PDC_PIN_SYS_WAKE0,
146 TZ1090_PDC_PIN_SYS_WAKE1,
147 TZ1090_PDC_PIN_SYS_WAKE2,
148 TZ1090_PDC_PIN_IR_DATA,
149 TZ1090_PDC_PIN_EXT_POWER,
150};
151
152/* Mux functions */
153
154enum tz1090_pdc_mux {
155 /* PDC_GPIO0 mux */
156 TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
157 /* PDC_GPIO1 mux */
158 TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
159};
160
161/* Pin groups a function can be muxed to */
162
163static const char * const gpio0_groups[] = {
164 "gpio0",
165};
166
167static const char * const gpio1_groups[] = {
168 "gpio1",
169};
170
171#define FUNCTION(mux, fname, group) \
172 [(TZ1090_PDC_MUX_ ## mux)] = { \
173 .name = #fname, \
174 .groups = group##_groups, \
175 .ngroups = ARRAY_SIZE(group##_groups), \
176 }
177
178/* Must correlate with enum tz1090_pdc_mux */
179static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
180 /* MUX fn pingroups */
181 FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
182 FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
183};
184
185/**
186 * MUX_PG() - Initialise a pin group with mux control
187 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
188 * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
189 * @mux_r: Mux register (REG_PINCTRL_ is prepended)
190 * @mux_b: Bit number in register of mux field
191 */
192#define MUX_PG(pg_name, f0, mux_r, mux_b) \
193 { \
194 .name = #pg_name, \
195 .pins = pg_name##_pins, \
196 .npins = ARRAY_SIZE(pg_name##_pins), \
197 .func = TZ1090_PDC_MUX_ ## f0, \
198 .reg = (REG_ ## mux_r), \
199 .bit = (mux_b), \
200 }
201
202/**
203 * DRV_PG() - Initialise a pin group with drive control
204 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
205 */
206#define DRV_PG(pg_name) \
207 { \
208 .name = #pg_name, \
209 .pins = pg_name##_pins, \
210 .npins = ARRAY_SIZE(pg_name##_pins), \
211 .drv = true, \
212 }
213
214static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
215 /* Muxing pin groups */
216 /* pg_name, f0, mux register, mux bit */
217 MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
218 MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
219
220 /* Drive pin groups */
221 /* pg_name */
222 DRV_PG(pdc),
223};
224
225/**
226 * struct tz1090_pdc_pmx - Private pinctrl data
227 * @dev: Platform device
228 * @pctl: Pin control device
229 * @regs: Register region
230 * @lock: Lock protecting coherency of mux_en and gpio_en
231 * @mux_en: Muxes that have been enabled
232 * @gpio_en: Muxable GPIOs that have been enabled
233 */
234struct tz1090_pdc_pmx {
235 struct device *dev;
236 struct pinctrl_dev *pctl;
237 void __iomem *regs;
238 spinlock_t lock;
239 u32 mux_en;
240 u32 gpio_en;
241};
242
243static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
244{
245 return ioread32(pmx->regs + reg);
246}
247
248static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
249{
250 iowrite32(val, pmx->regs + reg);
251}
252
253/*
254 * Pin control operations
255 */
256
257static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
258{
259 return ARRAY_SIZE(tz1090_pdc_groups);
260}
261
262static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl,
263 unsigned int group)
264{
265 return tz1090_pdc_groups[group].name;
266}
267
268static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
269 unsigned int group,
270 const unsigned int **pins,
271 unsigned int *num_pins)
272{
273 *pins = tz1090_pdc_groups[group].pins;
274 *num_pins = tz1090_pdc_groups[group].npins;
275
276 return 0;
277}
278
279#ifdef CONFIG_DEBUG_FS
280static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
281 struct seq_file *s,
282 unsigned int offset)
283{
284 seq_printf(s, " %s", dev_name(pctldev->dev));
285}
286#endif
287
288static int reserve_map(struct device *dev, struct pinctrl_map **map,
289 unsigned int *reserved_maps, unsigned int *num_maps,
290 unsigned int reserve)
291{
292 unsigned int old_num = *reserved_maps;
293 unsigned int new_num = *num_maps + reserve;
294 struct pinctrl_map *new_map;
295
296 if (old_num >= new_num)
297 return 0;
298
299 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
300 if (!new_map) {
301 dev_err(dev, "krealloc(map) failed\n");
302 return -ENOMEM;
303 }
304
305 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
306
307 *map = new_map;
308 *reserved_maps = new_num;
309
310 return 0;
311}
312
313static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
314 unsigned int *num_maps, const char *group,
315 const char *function)
316{
317 if (WARN_ON(*num_maps == *reserved_maps))
318 return -ENOSPC;
319
320 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
321 (*map)[*num_maps].data.mux.group = group;
322 (*map)[*num_maps].data.mux.function = function;
323 (*num_maps)++;
324
325 return 0;
326}
327
328/**
329 * get_group_selector() - returns the group selector for a group
330 * @pin_group: the pin group to look up
331 *
332 * This is the same as pinctrl_get_group_selector except it doesn't produce an
333 * error message if the group isn't found or debug messages.
334 */
335static int get_group_selector(const char *pin_group)
336{
337 unsigned int group;
338
339 for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group)
340 if (!strcmp(tz1090_pdc_groups[group].name, pin_group))
341 return group;
342
343 return -EINVAL;
344}
345
346static int add_map_configs(struct device *dev,
347 struct pinctrl_map **map,
348 unsigned int *reserved_maps, unsigned int *num_maps,
349 const char *group, unsigned long *configs,
350 unsigned int num_configs)
351{
352 unsigned long *dup_configs;
353 enum pinctrl_map_type type;
354
355 if (WARN_ON(*num_maps == *reserved_maps))
356 return -ENOSPC;
357
358 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
359 GFP_KERNEL);
360 if (!dup_configs) {
361 dev_err(dev, "kmemdup(configs) failed\n");
362 return -ENOMEM;
363 }
364
365 /*
366 * We support both pins and pin groups, but we need to figure out which
367 * one we have.
368 */
369 if (get_group_selector(group) >= 0)
370 type = PIN_MAP_TYPE_CONFIGS_GROUP;
371 else
372 type = PIN_MAP_TYPE_CONFIGS_PIN;
373 (*map)[*num_maps].type = type;
374 (*map)[*num_maps].data.configs.group_or_pin = group;
375 (*map)[*num_maps].data.configs.configs = dup_configs;
376 (*map)[*num_maps].data.configs.num_configs = num_configs;
377 (*num_maps)++;
378
379 return 0;
380}
381
382static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
383 struct pinctrl_map *map,
384 unsigned int num_maps)
385{
386 int i;
387
388 for (i = 0; i < num_maps; i++)
389 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
390 kfree(map[i].data.configs.configs);
391
392 kfree(map);
393}
394
395static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
396 struct device_node *np,
397 struct pinctrl_map **map,
398 unsigned int *reserved_maps,
399 unsigned int *num_maps)
400{
401 int ret;
402 const char *function;
403 unsigned long *configs = NULL;
404 unsigned int num_configs = 0;
405 unsigned int reserve;
406 struct property *prop;
407 const char *group;
408
409 ret = of_property_read_string(np, "tz1090,function", &function);
410 if (ret < 0) {
411 /* EINVAL=missing, which is fine since it's optional */
412 if (ret != -EINVAL)
413 dev_err(dev,
414 "could not parse property function\n");
415 function = NULL;
416 }
417
418 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
419 if (ret)
420 return ret;
421
422 reserve = 0;
423 if (function != NULL)
424 reserve++;
425 if (num_configs)
426 reserve++;
427 ret = of_property_count_strings(np, "tz1090,pins");
428 if (ret < 0) {
429 dev_err(dev, "could not parse property pins\n");
430 goto exit;
431 }
432 reserve *= ret;
433
434 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
435 if (ret < 0)
436 goto exit;
437
438 of_property_for_each_string(np, "tz1090,pins", prop, group) {
439 if (function) {
440 ret = add_map_mux(map, reserved_maps, num_maps,
441 group, function);
442 if (ret < 0)
443 goto exit;
444 }
445
446 if (num_configs) {
447 ret = add_map_configs(dev, map, reserved_maps,
448 num_maps, group, configs,
449 num_configs);
450 if (ret < 0)
451 goto exit;
452 }
453 }
454
455 ret = 0;
456
457exit:
458 kfree(configs);
459 return ret;
460}
461
462static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
463 struct device_node *np_config,
464 struct pinctrl_map **map,
465 unsigned int *num_maps)
466{
467 unsigned int reserved_maps;
468 struct device_node *np;
469 int ret;
470
471 reserved_maps = 0;
472 *map = NULL;
473 *num_maps = 0;
474
475 for_each_child_of_node(np_config, np) {
476 ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np,
477 map, &reserved_maps,
478 num_maps);
479 if (ret < 0) {
480 tz1090_pdc_pinctrl_dt_free_map(pctldev, *map,
481 *num_maps);
482 return ret;
483 }
484 }
485
486 return 0;
487}
488
489static struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
490 .get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
491 .get_group_name = tz1090_pdc_pinctrl_get_group_name,
492 .get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
493#ifdef CONFIG_DEBUG_FS
494 .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show,
495#endif
496 .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map,
497 .dt_free_map = tz1090_pdc_pinctrl_dt_free_map,
498};
499
500/*
501 * Pin mux operations
502 */
503
504static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
505{
506 return ARRAY_SIZE(tz1090_pdc_functions);
507}
508
509static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
510 unsigned int function)
511{
512 return tz1090_pdc_functions[function].name;
513}
514
515static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
516 unsigned int function,
517 const char * const **groups,
518 unsigned int * const num_groups)
519{
520 *groups = tz1090_pdc_functions[function].groups;
521 *num_groups = tz1090_pdc_functions[function].ngroups;
522
523 return 0;
524}
525
526/**
527 * tz1090_pdc_pinctrl_mux() - update mux bit
528 * @pmx: Pinmux data
529 * @grp: Pin mux group
530 */
531static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
532 const struct tz1090_pdc_pingroup *grp)
533{
534 u32 reg, select;
535 unsigned int pin_shift = grp->pins[0];
536 unsigned long flags;
537
538 /* select = mux && !gpio */
539 select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1;
540
541 /* set up the mux */
542 __global_lock2(flags);
543 reg = pmx_read(pmx, grp->reg);
544 reg &= ~BIT(grp->bit);
545 reg |= select << grp->bit;
546 pmx_write(pmx, reg, grp->reg);
547 __global_unlock2(flags);
548}
549
550static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
551 unsigned int function, unsigned int group)
552{
553 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
554 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
555
556 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
557 __func__,
558 function, tz1090_pdc_functions[function].name,
559 group, tz1090_pdc_groups[group].name);
560
561 /* is it even a mux? */
562 if (grp->drv)
563 return -EINVAL;
564
565 /* does this group even control the function? */
566 if (function != grp->func)
567 return -EINVAL;
568
569 /* record the pin being muxed and update mux bit */
570 spin_lock(&pmx->lock);
571 pmx->mux_en |= BIT(grp->pins[0]);
572 tz1090_pdc_pinctrl_mux(pmx, grp);
573 spin_unlock(&pmx->lock);
574 return 0;
575}
576
577static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
578 unsigned int function,
579 unsigned int group)
580{
581 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
582 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
583
584 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
585 __func__,
586 function, tz1090_pdc_functions[function].name,
587 group, tz1090_pdc_groups[group].name);
588
589 /* is it even a mux? */
590 if (grp->drv)
591 return;
592
593 /* does this group even control the function? */
594 if (function != grp->func)
595 return;
596
597 /* record the pin being unmuxed and update mux bit */
598 spin_lock(&pmx->lock);
599 pmx->mux_en &= ~BIT(grp->pins[0]);
600 tz1090_pdc_pinctrl_mux(pmx, grp);
601 spin_unlock(&pmx->lock);
602}
603
604static const struct tz1090_pdc_pingroup *find_mux_group(
605 struct tz1090_pdc_pmx *pmx,
606 unsigned int pin)
607{
608 const struct tz1090_pdc_pingroup *grp;
609 unsigned int group;
610
611 grp = tz1090_pdc_groups;
612 for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) {
613 /* only match muxes */
614 if (grp->drv)
615 continue;
616
617 /* with a matching pin */
618 if (grp->pins[0] == pin)
619 return grp;
620 }
621
622 return NULL;
623}
624
625static int tz1090_pdc_pinctrl_gpio_request_enable(
626 struct pinctrl_dev *pctldev,
627 struct pinctrl_gpio_range *range,
628 unsigned int pin)
629{
630 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
631 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
632
633 if (grp) {
634 /* record the pin in GPIO use and update mux bit */
635 spin_lock(&pmx->lock);
636 pmx->gpio_en |= BIT(pin);
637 tz1090_pdc_pinctrl_mux(pmx, grp);
638 spin_unlock(&pmx->lock);
639 }
640 return 0;
641}
642
643static void tz1090_pdc_pinctrl_gpio_disable_free(
644 struct pinctrl_dev *pctldev,
645 struct pinctrl_gpio_range *range,
646 unsigned int pin)
647{
648 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
649 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
650
651 if (grp) {
652 /* record the pin not in GPIO use and update mux bit */
653 spin_lock(&pmx->lock);
654 pmx->gpio_en &= ~BIT(pin);
655 tz1090_pdc_pinctrl_mux(pmx, grp);
656 spin_unlock(&pmx->lock);
657 }
658}
659
660static struct pinmux_ops tz1090_pdc_pinmux_ops = {
661 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
662 .get_function_name = tz1090_pdc_pinctrl_get_func_name,
663 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
664 .enable = tz1090_pdc_pinctrl_enable,
665 .disable = tz1090_pdc_pinctrl_disable,
666 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
667 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
668};
669
670/*
671 * Pin config operations
672 */
673
674static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
675 unsigned int pin,
676 enum pin_config_param param,
677 bool report_err,
678 u32 *reg, u32 *width, u32 *mask, u32 *shift,
679 u32 *val)
680{
681 /* Find information about parameter's register */
682 switch (param) {
683 case PIN_CONFIG_BIAS_DISABLE:
684 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
685 *val = REG_PU_PD_TRISTATE;
686 break;
687 case PIN_CONFIG_BIAS_PULL_UP:
688 *val = REG_PU_PD_UP;
689 break;
690 case PIN_CONFIG_BIAS_PULL_DOWN:
691 *val = REG_PU_PD_DOWN;
692 break;
693 case PIN_CONFIG_BIAS_BUS_HOLD:
694 *val = REG_PU_PD_REPEATER;
695 break;
696 default:
697 return -ENOTSUPP;
698 };
699
700 /* Only input bias parameters supported */
701 *reg = REG_GPIO_CONTROL2;
702 *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2;
703 *width = 2;
704
705 /* Calculate field information */
706 *mask = (BIT(*width) - 1) << *shift;
707
708 return 0;
709}
710
711static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
712 unsigned int pin, unsigned long *config)
713{
714 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
715 enum pin_config_param param = pinconf_to_config_param(*config);
716 int ret;
717 u32 reg, width, mask, shift, val, tmp, arg;
718
719 /* Get register information */
720 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
721 &reg, &width, &mask, &shift, &val);
722 if (ret < 0)
723 return ret;
724
725 /* Extract field from register */
726 tmp = pmx_read(pmx, reg);
727 arg = ((tmp & mask) >> shift) == val;
728
729 /* Config not active */
730 if (!arg)
731 return -EINVAL;
732
733 /* And pack config */
734 *config = pinconf_to_config_packed(param, arg);
735
736 return 0;
737}
738
739static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
740 unsigned int pin, unsigned long config)
741{
742 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
743 enum pin_config_param param = pinconf_to_config_param(config);
744 unsigned int arg = pinconf_to_config_argument(config);
745 int ret;
746 u32 reg, width, mask, shift, val, tmp;
747 unsigned long flags;
748
749 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
750 __func__, tz1090_pdc_pins[pin].name, config);
751
752 /* Get register information */
753 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
754 &reg, &width, &mask, &shift, &val);
755 if (ret < 0)
756 return ret;
757
758 /* Unpack argument and range check it */
759 if (arg > 1) {
760 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
761 __func__, arg);
762 return -EINVAL;
763 }
764
765 /* Write register field */
766 __global_lock2(flags);
767 tmp = pmx_read(pmx, reg);
768 tmp &= ~mask;
769 if (arg)
770 tmp |= val << shift;
771 pmx_write(pmx, tmp, reg);
772 __global_unlock2(flags);
773
774 return 0;
775}
776
777static const int tz1090_pdc_boolean_map[] = {
778 [0] = -EINVAL,
779 [1] = 1,
780};
781
782static const int tz1090_pdc_dr_map[] = {
783 [REG_DR_2mA] = 2,
784 [REG_DR_4mA] = 4,
785 [REG_DR_8mA] = 8,
786 [REG_DR_12mA] = 12,
787};
788
789static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
790 const struct tz1090_pdc_pingroup *g,
791 enum pin_config_param param,
792 bool report_err, u32 *reg, u32 *width,
793 u32 *mask, u32 *shift, const int **map)
794{
795 /* Drive configuration applies in groups, but not to all groups. */
796 if (!g->drv) {
797 if (report_err)
798 dev_dbg(pctldev->dev,
799 "%s: group %s has no drive control\n",
800 __func__, g->name);
801 return -ENOTSUPP;
802 }
803
804 /* Find information about drive parameter's register */
805 *reg = REG_GPIO_CONTROL2;
806 switch (param) {
807 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
808 *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S;
809 *width = 1;
810 *map = tz1090_pdc_boolean_map;
811 break;
812 case PIN_CONFIG_DRIVE_STRENGTH:
813 *shift = REG_GPIO_CONTROL2_PDC_DR_S;
814 *width = 2;
815 *map = tz1090_pdc_dr_map;
816 break;
817 case PIN_CONFIG_LOW_POWER_MODE:
818 *shift = REG_GPIO_CONTROL2_PDC_POS_S;
819 *width = 1;
820 *map = tz1090_pdc_boolean_map;
821 break;
822 default:
823 return -ENOTSUPP;
824 };
825
826 /* Calculate field information */
827 *mask = (BIT(*width) - 1) << *shift;
828
829 return 0;
830}
831
832static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
833 unsigned int group,
834 unsigned long *config)
835{
836 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
837 const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
838 enum pin_config_param param = pinconf_to_config_param(*config);
839 int ret, arg;
840 u32 reg, width, mask, shift, val;
841 const int *map;
842
843 /* Get register information */
844 ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
845 &reg, &width, &mask, &shift, &map);
846 if (ret < 0)
847 return ret;
848
849 /* Extract field from register */
850 val = pmx_read(pmx, reg);
851 arg = map[(val & mask) >> shift];
852 if (arg < 0)
853 return arg;
854
855 /* And pack config */
856 *config = pinconf_to_config_packed(param, arg);
857
858 return 0;
859}
860
861static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
862 unsigned int group,
863 unsigned long config)
864{
865 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
866 const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
867 enum pin_config_param param = pinconf_to_config_param(config);
868 const unsigned int *pit;
869 unsigned int i;
870 int ret, arg;
871 u32 reg, width, mask, shift, val;
872 unsigned long flags;
873 const int *map;
874
875 dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
876 __func__, g->name, config);
877
878 /* Get register information */
879 ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
880 &reg, &width, &mask, &shift, &map);
881 if (ret < 0) {
882 /*
883 * Maybe we're trying to set a per-pin configuration of a group,
884 * so do the pins one by one. This is mainly as a convenience.
885 */
886 for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
887 ret = tz1090_pdc_pinconf_set(pctldev, *pit, config);
888 if (ret)
889 return ret;
890 }
891 return 0;
892 }
893
894 /* Unpack argument and map it to register value */
895 arg = pinconf_to_config_argument(config);
896 for (i = 0; i < BIT(width); ++i) {
897 if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
898 /* Write register field */
899 __global_lock2(flags);
900 val = pmx_read(pmx, reg);
901 val &= ~mask;
902 val |= i << shift;
903 pmx_write(pmx, val, reg);
904 __global_unlock2(flags);
905 return 0;
906 }
907 }
908
909 dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
910 __func__, arg);
911 return 0;
912}
913
914static struct pinconf_ops tz1090_pdc_pinconf_ops = {
915 .is_generic = true,
916 .pin_config_get = tz1090_pdc_pinconf_get,
917 .pin_config_set = tz1090_pdc_pinconf_set,
918 .pin_config_group_get = tz1090_pdc_pinconf_group_get,
919 .pin_config_group_set = tz1090_pdc_pinconf_group_set,
920 .pin_config_config_dbg_show = pinconf_generic_dump_config,
921};
922
923/*
924 * Pin control driver setup
925 */
926
927static struct pinctrl_desc tz1090_pdc_pinctrl_desc = {
928 .pctlops = &tz1090_pdc_pinctrl_ops,
929 .pmxops = &tz1090_pdc_pinmux_ops,
930 .confops = &tz1090_pdc_pinconf_ops,
931 .owner = THIS_MODULE,
932};
933
934static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
935{
936 struct tz1090_pdc_pmx *pmx;
937 struct resource *res;
938
939 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
940 if (!pmx) {
941 dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n");
942 return -ENOMEM;
943 }
944 pmx->dev = &pdev->dev;
945 spin_lock_init(&pmx->lock);
946
947 tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev);
948 tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins;
949 tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
950
951 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
952 if (!res) {
953 dev_err(&pdev->dev, "Missing MEM resource\n");
954 return -ENODEV;
955 }
956
957 if (!devm_request_mem_region(&pdev->dev, res->start,
958 resource_size(res),
959 dev_name(&pdev->dev))) {
960 dev_err(&pdev->dev,
961 "Couldn't request MEM resource\n");
962 return -ENODEV;
963 }
964
965 pmx->regs = devm_ioremap(&pdev->dev, res->start,
966 resource_size(res));
967 if (!pmx->regs) {
968 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
969 return -ENODEV;
970 }
971
972 pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx);
973 if (!pmx->pctl) {
974 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
975 return -ENODEV;
976 }
977
978 platform_set_drvdata(pdev, pmx);
979
980 dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n");
981
982 return 0;
983}
984
985static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev)
986{
987 struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev);
988
989 pinctrl_unregister(pmx->pctl);
990
991 return 0;
992}
993
994static struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
995 { .compatible = "img,tz1090-pdc-pinctrl", },
996 { },
997};
998
999static struct platform_driver tz1090_pdc_pinctrl_driver = {
1000 .driver = {
1001 .name = "tz1090-pdc-pinctrl",
1002 .owner = THIS_MODULE,
1003 .of_match_table = tz1090_pdc_pinctrl_of_match,
1004 },
1005 .probe = tz1090_pdc_pinctrl_probe,
1006 .remove = tz1090_pdc_pinctrl_remove,
1007};
1008
1009static int __init tz1090_pdc_pinctrl_init(void)
1010{
1011 return platform_driver_register(&tz1090_pdc_pinctrl_driver);
1012}
1013arch_initcall(tz1090_pdc_pinctrl_init);
1014
1015static void __exit tz1090_pdc_pinctrl_exit(void)
1016{
1017 platform_driver_unregister(&tz1090_pdc_pinctrl_driver);
1018}
1019module_exit(tz1090_pdc_pinctrl_exit);
1020
1021MODULE_AUTHOR("Imagination Technologies Ltd.");
1022MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver");
1023MODULE_LICENSE("GPL v2");
1024MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
new file mode 100644
index 000000000000..4edae08a0a61
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -0,0 +1,2072 @@
1/*
2 * Pinctrl driver for the Toumaz Xenif TZ1090 SoC
3 *
4 * Copyright (c) 2013, Imagination Technologies Ltd.
5 *
6 * Derived from Tegra code:
7 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Derived from code:
10 * Copyright (C) 2010 Google, Inc.
11 * Copyright (C) 2010 NVIDIA Corporation
12 * Copyright (C) 2009-2011 ST-Ericsson AB
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms and conditions of the GNU General Public License,
16 * version 2, as published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/bitops.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pinctrl/machine.h>
30#include <linux/pinctrl/pinconf-generic.h>
31#include <linux/pinctrl/pinctrl.h>
32#include <linux/pinctrl/pinmux.h>
33#include <linux/slab.h>
34#include <linux/spinlock.h>
35
36/*
37 * The registers may be shared with other threads/cores, so we need to use the
38 * metag global lock2 for atomicity.
39 */
40#include <asm/global_lock.h>
41
42#include "core.h"
43#include "pinconf.h"
44
45/* Register offsets from bank base address */
46#define REG_PINCTRL_SELECT 0x10
47#define REG_PINCTRL_SCHMITT 0x90
48#define REG_PINCTRL_PU_PD 0xa0
49#define REG_PINCTRL_SR 0xc0
50#define REG_PINCTRL_DR 0xd0
51#define REG_PINCTRL_IF_CTL 0xe0
52
53/* REG_PINCTRL_PU_PD field values */
54#define REG_PU_PD_TRISTATE 0
55#define REG_PU_PD_UP 1
56#define REG_PU_PD_DOWN 2
57#define REG_PU_PD_REPEATER 3
58
59/* REG_PINCTRL_DR field values */
60#define REG_DR_2mA 0
61#define REG_DR_4mA 1
62#define REG_DR_8mA 2
63#define REG_DR_12mA 3
64
65/**
66 * struct tz1090_function - TZ1090 pinctrl mux function
67 * @name: The name of the function, exported to pinctrl core.
68 * @groups: An array of pin groups that may select this function.
69 * @ngroups: The number of entries in @groups.
70 */
71struct tz1090_function {
72 const char *name;
73 const char * const *groups;
74 unsigned int ngroups;
75};
76
77/**
78 * struct tz1090_muxdesc - TZ1090 individual mux description
79 * @funcs: Function for each mux value.
80 * @reg: Mux register offset. 0 if unsupported.
81 * @bit: Mux register bit. 0 if unsupported.
82 * @width: Mux field width. 0 if unsupported.
83 *
84 * A representation of a group of signals (possibly just one signal) in the
85 * TZ1090 which can be muxed to a set of functions or sub muxes.
86 */
87struct tz1090_muxdesc {
88 int funcs[5];
89 u16 reg;
90 u8 bit;
91 u8 width;
92};
93
94/**
95 * struct tz1090_pingroup - TZ1090 pin group
96 * @name: Name of pin group.
97 * @pins: Array of pin numbers in this pin group.
98 * @npins: Number of pins in this pin group.
99 * @mux: Top level mux.
100 * @drv: Drive control supported, 0 if unsupported.
101 * This means Schmitt, Slew, and Drive strength.
102 * @slw_bit: Slew register bit. 0 if unsupported.
103 * The same bit is used for Schmitt, and Drive (*2).
104 * @func: Currently muxed function.
105 * @func_count: Number of pins using current mux function.
106 *
107 * A representation of a group of pins (possibly just one pin) in the TZ1090
108 * pin controller. Each group allows some parameter or parameters to be
109 * configured. The most common is mux function selection.
110 */
111struct tz1090_pingroup {
112 const char *name;
113 const unsigned int *pins;
114 unsigned int npins;
115 struct tz1090_muxdesc mux;
116
117 bool drv;
118 u8 slw_bit;
119
120 int func;
121 unsigned int func_count;
122};
123
124/*
125 * Most pins affected by the pinmux can also be GPIOs. Define these first.
126 * These must match how the GPIO driver names/numbers its pins.
127 */
128
129enum tz1090_pin {
130 /* GPIO pins */
131 TZ1090_PIN_SDIO_CLK,
132 TZ1090_PIN_SDIO_CMD,
133 TZ1090_PIN_SDIO_D0,
134 TZ1090_PIN_SDIO_D1,
135 TZ1090_PIN_SDIO_D2,
136 TZ1090_PIN_SDIO_D3,
137 TZ1090_PIN_SDH_CD,
138 TZ1090_PIN_SDH_WP,
139 TZ1090_PIN_SPI0_MCLK,
140 TZ1090_PIN_SPI0_CS0,
141 TZ1090_PIN_SPI0_CS1,
142 TZ1090_PIN_SPI0_CS2,
143 TZ1090_PIN_SPI0_DOUT,
144 TZ1090_PIN_SPI0_DIN,
145 TZ1090_PIN_SPI1_MCLK,
146 TZ1090_PIN_SPI1_CS0,
147 TZ1090_PIN_SPI1_CS1,
148 TZ1090_PIN_SPI1_CS2,
149 TZ1090_PIN_SPI1_DOUT,
150 TZ1090_PIN_SPI1_DIN,
151 TZ1090_PIN_UART0_RXD,
152 TZ1090_PIN_UART0_TXD,
153 TZ1090_PIN_UART0_CTS,
154 TZ1090_PIN_UART0_RTS,
155 TZ1090_PIN_UART1_RXD,
156 TZ1090_PIN_UART1_TXD,
157 TZ1090_PIN_SCB0_SDAT,
158 TZ1090_PIN_SCB0_SCLK,
159 TZ1090_PIN_SCB1_SDAT,
160 TZ1090_PIN_SCB1_SCLK,
161 TZ1090_PIN_SCB2_SDAT,
162 TZ1090_PIN_SCB2_SCLK,
163 TZ1090_PIN_I2S_MCLK,
164 TZ1090_PIN_I2S_BCLK_OUT,
165 TZ1090_PIN_I2S_LRCLK_OUT,
166 TZ1090_PIN_I2S_DOUT0,
167 TZ1090_PIN_I2S_DOUT1,
168 TZ1090_PIN_I2S_DOUT2,
169 TZ1090_PIN_I2S_DIN,
170 TZ1090_PIN_PDM_A,
171 TZ1090_PIN_PDM_B,
172 TZ1090_PIN_PDM_C,
173 TZ1090_PIN_PDM_D,
174 TZ1090_PIN_TFT_RED0,
175 TZ1090_PIN_TFT_RED1,
176 TZ1090_PIN_TFT_RED2,
177 TZ1090_PIN_TFT_RED3,
178 TZ1090_PIN_TFT_RED4,
179 TZ1090_PIN_TFT_RED5,
180 TZ1090_PIN_TFT_RED6,
181 TZ1090_PIN_TFT_RED7,
182 TZ1090_PIN_TFT_GREEN0,
183 TZ1090_PIN_TFT_GREEN1,
184 TZ1090_PIN_TFT_GREEN2,
185 TZ1090_PIN_TFT_GREEN3,
186 TZ1090_PIN_TFT_GREEN4,
187 TZ1090_PIN_TFT_GREEN5,
188 TZ1090_PIN_TFT_GREEN6,
189 TZ1090_PIN_TFT_GREEN7,
190 TZ1090_PIN_TFT_BLUE0,
191 TZ1090_PIN_TFT_BLUE1,
192 TZ1090_PIN_TFT_BLUE2,
193 TZ1090_PIN_TFT_BLUE3,
194 TZ1090_PIN_TFT_BLUE4,
195 TZ1090_PIN_TFT_BLUE5,
196 TZ1090_PIN_TFT_BLUE6,
197 TZ1090_PIN_TFT_BLUE7,
198 TZ1090_PIN_TFT_VDDEN_GD,
199 TZ1090_PIN_TFT_PANELCLK,
200 TZ1090_PIN_TFT_BLANK_LS,
201 TZ1090_PIN_TFT_VSYNC_NS,
202 TZ1090_PIN_TFT_HSYNC_NR,
203 TZ1090_PIN_TFT_VD12ACB,
204 TZ1090_PIN_TFT_PWRSAVE,
205 TZ1090_PIN_TX_ON,
206 TZ1090_PIN_RX_ON,
207 TZ1090_PIN_PLL_ON,
208 TZ1090_PIN_PA_ON,
209 TZ1090_PIN_RX_HP,
210 TZ1090_PIN_GAIN0,
211 TZ1090_PIN_GAIN1,
212 TZ1090_PIN_GAIN2,
213 TZ1090_PIN_GAIN3,
214 TZ1090_PIN_GAIN4,
215 TZ1090_PIN_GAIN5,
216 TZ1090_PIN_GAIN6,
217 TZ1090_PIN_GAIN7,
218 TZ1090_PIN_ANT_SEL0,
219 TZ1090_PIN_ANT_SEL1,
220 TZ1090_PIN_SDH_CLK_IN,
221
222 /* Non-GPIO pins */
223 TZ1090_PIN_TCK,
224 TZ1090_PIN_TRST,
225 TZ1090_PIN_TDI,
226 TZ1090_PIN_TDO,
227 TZ1090_PIN_TMS,
228 TZ1090_PIN_CLK_OUT0,
229 TZ1090_PIN_CLK_OUT1,
230
231 NUM_GPIOS = TZ1090_PIN_TCK,
232};
233
234/* Pin names */
235
236static const struct pinctrl_pin_desc tz1090_pins[] = {
237 /* GPIO pins */
238 PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"),
239 PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"),
240 PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"),
241 PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"),
242 PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"),
243 PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"),
244 PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"),
245 PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"),
246 PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"),
247 PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"),
248 PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"),
249 PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"),
250 PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"),
251 PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"),
252 PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"),
253 PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"),
254 PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"),
255 PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"),
256 PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"),
257 PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"),
258 PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"),
259 PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"),
260 PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"),
261 PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"),
262 PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"),
263 PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"),
264 PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"),
265 PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"),
266 PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"),
267 PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"),
268 PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"),
269 PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"),
270 PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"),
271 PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"),
272 PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"),
273 PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"),
274 PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"),
275 PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"),
276 PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"),
277 PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"),
278 PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"),
279 PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"),
280 PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"),
281 PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"),
282 PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"),
283 PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"),
284 PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"),
285 PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"),
286 PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"),
287 PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"),
288 PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"),
289 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"),
290 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"),
291 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"),
292 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"),
293 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"),
294 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"),
295 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"),
296 PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"),
297 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"),
298 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"),
299 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"),
300 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"),
301 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"),
302 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"),
303 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"),
304 PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"),
305 PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"),
306 PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"),
307 PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"),
308 PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"),
309 PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"),
310 PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"),
311 PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"),
312 PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"),
313 PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"),
314 PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"),
315 PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"),
316 PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"),
317 PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"),
318 PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"),
319 PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"),
320 PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"),
321 PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"),
322 PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"),
323 PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"),
324 PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"),
325 PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"),
326 PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"),
327 PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"),
328
329 /* Non-GPIO pins */
330 PINCTRL_PIN(TZ1090_PIN_TCK, "tck"),
331 PINCTRL_PIN(TZ1090_PIN_TRST, "trst"),
332 PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"),
333 PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"),
334 PINCTRL_PIN(TZ1090_PIN_TMS, "tms"),
335 PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"),
336 PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"),
337};
338
339/* Pins in each pin group */
340
341static const unsigned int spi1_cs2_pins[] = {
342 TZ1090_PIN_SPI1_CS2,
343};
344
345static const unsigned int pdm_d_pins[] = {
346 TZ1090_PIN_PDM_D,
347};
348
349static const unsigned int tft_pins[] = {
350 TZ1090_PIN_TFT_RED0,
351 TZ1090_PIN_TFT_RED1,
352 TZ1090_PIN_TFT_RED2,
353 TZ1090_PIN_TFT_RED3,
354 TZ1090_PIN_TFT_RED4,
355 TZ1090_PIN_TFT_RED5,
356 TZ1090_PIN_TFT_RED6,
357 TZ1090_PIN_TFT_RED7,
358 TZ1090_PIN_TFT_GREEN0,
359 TZ1090_PIN_TFT_GREEN1,
360 TZ1090_PIN_TFT_GREEN2,
361 TZ1090_PIN_TFT_GREEN3,
362 TZ1090_PIN_TFT_GREEN4,
363 TZ1090_PIN_TFT_GREEN5,
364 TZ1090_PIN_TFT_GREEN6,
365 TZ1090_PIN_TFT_GREEN7,
366 TZ1090_PIN_TFT_BLUE0,
367 TZ1090_PIN_TFT_BLUE1,
368 TZ1090_PIN_TFT_BLUE2,
369 TZ1090_PIN_TFT_BLUE3,
370 TZ1090_PIN_TFT_BLUE4,
371 TZ1090_PIN_TFT_BLUE5,
372 TZ1090_PIN_TFT_BLUE6,
373 TZ1090_PIN_TFT_BLUE7,
374 TZ1090_PIN_TFT_VDDEN_GD,
375 TZ1090_PIN_TFT_PANELCLK,
376 TZ1090_PIN_TFT_BLANK_LS,
377 TZ1090_PIN_TFT_VSYNC_NS,
378 TZ1090_PIN_TFT_HSYNC_NR,
379 TZ1090_PIN_TFT_VD12ACB,
380 TZ1090_PIN_TFT_PWRSAVE,
381};
382
383static const unsigned int afe_pins[] = {
384 TZ1090_PIN_TX_ON,
385 TZ1090_PIN_RX_ON,
386 TZ1090_PIN_PLL_ON,
387 TZ1090_PIN_PA_ON,
388 TZ1090_PIN_RX_HP,
389 TZ1090_PIN_ANT_SEL0,
390 TZ1090_PIN_ANT_SEL1,
391 TZ1090_PIN_GAIN0,
392 TZ1090_PIN_GAIN1,
393 TZ1090_PIN_GAIN2,
394 TZ1090_PIN_GAIN3,
395 TZ1090_PIN_GAIN4,
396 TZ1090_PIN_GAIN5,
397 TZ1090_PIN_GAIN6,
398 TZ1090_PIN_GAIN7,
399};
400
401static const unsigned int sdio_pins[] = {
402 TZ1090_PIN_SDIO_CLK,
403 TZ1090_PIN_SDIO_CMD,
404 TZ1090_PIN_SDIO_D0,
405 TZ1090_PIN_SDIO_D1,
406 TZ1090_PIN_SDIO_D2,
407 TZ1090_PIN_SDIO_D3,
408};
409
410static const unsigned int sdh_pins[] = {
411 TZ1090_PIN_SDH_CD,
412 TZ1090_PIN_SDH_WP,
413 TZ1090_PIN_SDH_CLK_IN,
414};
415
416static const unsigned int spi0_pins[] = {
417 TZ1090_PIN_SPI0_MCLK,
418 TZ1090_PIN_SPI0_CS0,
419 TZ1090_PIN_SPI0_CS1,
420 TZ1090_PIN_SPI0_CS2,
421 TZ1090_PIN_SPI0_DOUT,
422 TZ1090_PIN_SPI0_DIN,
423};
424
425static const unsigned int spi1_pins[] = {
426 TZ1090_PIN_SPI1_MCLK,
427 TZ1090_PIN_SPI1_CS0,
428 TZ1090_PIN_SPI1_CS1,
429 TZ1090_PIN_SPI1_CS2,
430 TZ1090_PIN_SPI1_DOUT,
431 TZ1090_PIN_SPI1_DIN,
432};
433
434static const unsigned int uart0_pins[] = {
435 TZ1090_PIN_UART0_RTS,
436 TZ1090_PIN_UART0_CTS,
437 TZ1090_PIN_UART0_TXD,
438 TZ1090_PIN_UART0_RXD,
439};
440
441static const unsigned int uart1_pins[] = {
442 TZ1090_PIN_UART1_TXD,
443 TZ1090_PIN_UART1_RXD,
444};
445
446static const unsigned int uart_pins[] = {
447 TZ1090_PIN_UART1_TXD,
448 TZ1090_PIN_UART1_RXD,
449 TZ1090_PIN_UART0_RTS,
450 TZ1090_PIN_UART0_CTS,
451 TZ1090_PIN_UART0_TXD,
452 TZ1090_PIN_UART0_RXD,
453};
454
455static const unsigned int scb0_pins[] = {
456 TZ1090_PIN_SCB0_SDAT,
457 TZ1090_PIN_SCB0_SCLK,
458};
459
460static const unsigned int scb1_pins[] = {
461 TZ1090_PIN_SCB1_SDAT,
462 TZ1090_PIN_SCB1_SCLK,
463};
464
465static const unsigned int scb2_pins[] = {
466 TZ1090_PIN_SCB2_SDAT,
467 TZ1090_PIN_SCB2_SCLK,
468};
469
470static const unsigned int i2s_pins[] = {
471 TZ1090_PIN_I2S_MCLK,
472 TZ1090_PIN_I2S_BCLK_OUT,
473 TZ1090_PIN_I2S_LRCLK_OUT,
474 TZ1090_PIN_I2S_DOUT0,
475 TZ1090_PIN_I2S_DOUT1,
476 TZ1090_PIN_I2S_DOUT2,
477 TZ1090_PIN_I2S_DIN,
478};
479
480static const unsigned int jtag_pins[] = {
481 TZ1090_PIN_TCK,
482 TZ1090_PIN_TRST,
483 TZ1090_PIN_TDI,
484 TZ1090_PIN_TDO,
485 TZ1090_PIN_TMS,
486};
487
488/* Pins in each drive pin group */
489
490static const unsigned int drive_sdio_pins[] = {
491 TZ1090_PIN_SDIO_CLK,
492 TZ1090_PIN_SDIO_CMD,
493 TZ1090_PIN_SDIO_D0,
494 TZ1090_PIN_SDIO_D1,
495 TZ1090_PIN_SDIO_D2,
496 TZ1090_PIN_SDIO_D3,
497 TZ1090_PIN_SDH_WP,
498 TZ1090_PIN_SDH_CD,
499 TZ1090_PIN_SDH_CLK_IN,
500};
501
502static const unsigned int drive_i2s_pins[] = {
503 TZ1090_PIN_CLK_OUT1,
504 TZ1090_PIN_I2S_DIN,
505 TZ1090_PIN_I2S_DOUT0,
506 TZ1090_PIN_I2S_DOUT1,
507 TZ1090_PIN_I2S_DOUT2,
508 TZ1090_PIN_I2S_LRCLK_OUT,
509 TZ1090_PIN_I2S_BCLK_OUT,
510 TZ1090_PIN_I2S_MCLK,
511};
512
513static const unsigned int drive_scb0_pins[] = {
514 TZ1090_PIN_SCB0_SCLK,
515 TZ1090_PIN_SCB0_SDAT,
516 TZ1090_PIN_PDM_D,
517 TZ1090_PIN_PDM_C,
518};
519
520static const unsigned int drive_pdm_pins[] = {
521 TZ1090_PIN_CLK_OUT0,
522 TZ1090_PIN_PDM_B,
523 TZ1090_PIN_PDM_A,
524};
525
526/* Pin groups each function can be muxed to */
527
528/*
529 * The magic "perip" function allows otherwise non-muxing pins to be enabled in
530 * peripheral mode.
531 */
532static const char * const perip_groups[] = {
533 /* non-muxing convenient gpio pingroups */
534 "uart",
535 "uart0",
536 "uart1",
537 "spi0",
538 "spi1",
539 "scb0",
540 "scb1",
541 "scb2",
542 "i2s",
543 /* individual pins not part of a pin mux group */
544 "spi0_mclk",
545 "spi0_cs0",
546 "spi0_cs1",
547 "spi0_cs2",
548 "spi0_dout",
549 "spi0_din",
550 "spi1_mclk",
551 "spi1_cs0",
552 "spi1_cs1",
553 "spi1_dout",
554 "spi1_din",
555 "uart0_rxd",
556 "uart0_txd",
557 "uart0_cts",
558 "uart0_rts",
559 "uart1_rxd",
560 "uart1_txd",
561 "scb0_sdat",
562 "scb0_sclk",
563 "scb1_sdat",
564 "scb1_sclk",
565 "scb2_sdat",
566 "scb2_sclk",
567 "i2s_mclk",
568 "i2s_bclk_out",
569 "i2s_lrclk_out",
570 "i2s_dout0",
571 "i2s_dout1",
572 "i2s_dout2",
573 "i2s_din",
574 "pdm_a",
575 "pdm_b",
576 "pdm_c",
577};
578
579static const char * const sdh_sdio_groups[] = {
580 "sdh",
581 "sdio",
582 /* sdh pins */
583 "sdh_cd",
584 "sdh_wp",
585 "sdh_clk_in",
586 /* sdio pins */
587 "sdio_clk",
588 "sdio_cmd",
589 "sdio_d0",
590 "sdio_d1",
591 "sdio_d2",
592 "sdio_d3",
593};
594
595static const char * const spi1_cs2_groups[] = {
596 "spi1_cs2",
597};
598
599static const char * const pdm_dac_groups[] = {
600 "pdm_d",
601};
602
603static const char * const usb_vbus_groups[] = {
604 "spi1_cs2",
605 "pdm_d",
606};
607
608static const char * const afe_groups[] = {
609 "afe",
610 /* afe pins */
611 "tx_on",
612 "rx_on",
613 "pll_on",
614 "pa_on",
615 "rx_hp",
616 "ant_sel0",
617 "ant_sel1",
618 "gain0",
619 "gain1",
620 "gain2",
621 "gain3",
622 "gain4",
623 "gain5",
624 "gain6",
625 "gain7",
626};
627
628static const char * const tft_groups[] = {
629 "tft",
630 /* tft pins */
631 "tft_red0",
632 "tft_red1",
633 "tft_red2",
634 "tft_red3",
635 "tft_red4",
636 "tft_red5",
637 "tft_red6",
638 "tft_red7",
639 "tft_green0",
640 "tft_green1",
641 "tft_green2",
642 "tft_green3",
643 "tft_green4",
644 "tft_green5",
645 "tft_green6",
646 "tft_green7",
647 "tft_blue0",
648 "tft_blue1",
649 "tft_blue2",
650 "tft_blue3",
651 "tft_blue4",
652 "tft_blue5",
653 "tft_blue6",
654 "tft_blue7",
655 "tft_vdden_gd",
656 "tft_panelclk",
657 "tft_blank_ls",
658 "tft_vsync_ns",
659 "tft_hsync_nr",
660 "tft_vd12acb",
661 "tft_pwrsave",
662};
663
664/* Mux functions that can be used by a mux */
665
666enum tz1090_mux {
667 /* internal placeholder */
668 TZ1090_MUX_NA = -1,
669 /* magic per-non-muxing-GPIO-pin peripheral mode mux */
670 TZ1090_MUX_PERIP,
671 /* SDH/SDIO mux */
672 TZ1090_MUX_SDH,
673 TZ1090_MUX_SDIO,
674 /* USB_VBUS muxes */
675 TZ1090_MUX_SPI1_CS2,
676 TZ1090_MUX_PDM_DAC,
677 TZ1090_MUX_USB_VBUS,
678 /* AFE mux */
679 TZ1090_MUX_AFE,
680 TZ1090_MUX_TS_OUT_0,
681 /* EXT_DAC mux */
682 TZ1090_MUX_DAC,
683 TZ1090_MUX_NOT_IQADC_STB,
684 TZ1090_MUX_IQDAC_STB,
685 /* TFT mux */
686 TZ1090_MUX_TFT,
687 TZ1090_MUX_EXT_DAC,
688 TZ1090_MUX_TS_OUT_1,
689 TZ1090_MUX_LCD_TRACE,
690 TZ1090_MUX_PHY_RINGOSC,
691};
692
693#define FUNCTION(mux, fname, group) \
694 [(TZ1090_MUX_ ## mux)] = { \
695 .name = #fname, \
696 .groups = group##_groups, \
697 .ngroups = ARRAY_SIZE(group##_groups), \
698 }
699/* For intermediate functions with submuxes */
700#define NULL_FUNCTION(mux, fname) \
701 [(TZ1090_MUX_ ## mux)] = { \
702 .name = #fname, \
703 }
704
705/* Must correlate with enum tz1090_mux */
706static const struct tz1090_function tz1090_functions[] = {
707 /* FUNCTION function name pingroups */
708 FUNCTION(PERIP, perip, perip),
709 FUNCTION(SDH, sdh, sdh_sdio),
710 FUNCTION(SDIO, sdio, sdh_sdio),
711 FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2),
712 FUNCTION(PDM_DAC, pdm_dac, pdm_dac),
713 FUNCTION(USB_VBUS, usb_vbus, usb_vbus),
714 FUNCTION(AFE, afe, afe),
715 FUNCTION(TS_OUT_0, ts_out_0, afe),
716 FUNCTION(DAC, ext_dac, tft),
717 FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft),
718 FUNCTION(IQDAC_STB, iqdac_stb, tft),
719 FUNCTION(TFT, tft, tft),
720 NULL_FUNCTION(EXT_DAC, _ext_dac),
721 FUNCTION(TS_OUT_1, ts_out_1, tft),
722 FUNCTION(LCD_TRACE, lcd_trace, tft),
723 FUNCTION(PHY_RINGOSC, phy_ringosc, tft),
724};
725
726/* Sub muxes */
727
728/**
729 * MUX() - Initialise a mux description.
730 * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
731 * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
732 * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
733 * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
734 * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
735 * @mux_r: Mux register (REG_PINCTRL_ is prepended)
736 * @mux_b: Bit number in register that the mux field begins
737 * @mux_w: Width of mux field in register
738 */
739#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \
740 { \
741 .funcs = { \
742 TZ1090_MUX_ ## f0, \
743 TZ1090_MUX_ ## f1, \
744 TZ1090_MUX_ ## f2, \
745 TZ1090_MUX_ ## f3, \
746 TZ1090_MUX_ ## f4, \
747 }, \
748 .reg = (REG_PINCTRL_ ## mux_r), \
749 .bit = (mux_b), \
750 .width = (mux_w), \
751 }
752
753/**
754 * DEFINE_SUBMUX() - Defines a submux description separate from a pin group.
755 * @mux: Mux name (_submux is appended)
756 * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
757 * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
758 * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
759 * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
760 * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
761 * @mux_r: Mux register (REG_PINCTRL_ is prepended)
762 * @mux_b: Bit number in register that the mux field begins
763 * @mux_w: Width of mux field in register
764 *
765 * A sub mux is a nested mux that can be bound to a magic function number used
766 * by another mux description. For example value 4 of the top level mux might
767 * correspond to a function which has a submux pointed to in tz1090_submux[].
768 * The outer mux can then take on any function in the top level mux or the
769 * submux, and if a submux function is chosen both muxes are updated to route
770 * the signal from the submux.
771 *
772 * The submux can be defined with DEFINE_SUBMUX and pointed to from
773 * tz1090_submux[] using SUBMUX.
774 */
775#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \
776 static struct tz1090_muxdesc mux ## _submux = \
777 MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w)
778
779/**
780 * SUBMUX() - Link a submux to a function number.
781 * @f: Function name (TZ1090_MUX_ is prepended)
782 * @submux: Submux name (_submux is appended)
783 *
784 * For use in tz1090_submux[] initialisation to link an intermediate function
785 * number to a particular submux description. It indicates that when the
786 * function is chosen the signal is connected to the submux.
787 */
788#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux)
789
790/**
791 * MUX_PG() - Initialise a pin group with mux control
792 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
793 * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none)
794 * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none)
795 * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none)
796 * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none)
797 * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none)
798 * @mux_r: Mux register (REG_PINCTRL_ is prepended)
799 * @mux_b: Bit number in register that the mux field begins
800 * @mux_w: Width of mux field in register
801 */
802#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \
803 mux_r, mux_b, mux_w) \
804 { \
805 .name = #pg_name, \
806 .pins = pg_name##_pins, \
807 .npins = ARRAY_SIZE(pg_name##_pins), \
808 .mux = MUX(f0, f1, f2, f3, f4, \
809 mux_r, mux_b, mux_w), \
810 }
811
812/**
813 * SIMPLE_PG() - Initialise a simple convenience pin group
814 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
815 *
816 * A simple pin group is simply used for binding pins together so they can be
817 * referred to by a single name instead of having to list every pin
818 * individually.
819 */
820#define SIMPLE_PG(pg_name) \
821 { \
822 .name = #pg_name, \
823 .pins = pg_name##_pins, \
824 .npins = ARRAY_SIZE(pg_name##_pins), \
825 }
826
827/**
828 * DRV_PG() - Initialise a pin group with drive control
829 * @pg_name: Pin group name (stringified, _pins appended to get pins array)
830 * @slw_b: Slew register bit.
831 * The same bit is used for Schmitt, and Drive (*2).
832 */
833#define DRV_PG(pg_name, slw_b) \
834 { \
835 .name = #pg_name, \
836 .pins = pg_name##_pins, \
837 .npins = ARRAY_SIZE(pg_name##_pins), \
838 .drv = true, \
839 .slw_bit = (slw_b), \
840 }
841
842/*
843 * Define main muxing pin groups
844 */
845
846/* submuxes */
847
848/* name f0, f1, f2, f3, f4, mux r/b/w */
849DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2);
850
851/* bind submuxes to internal functions */
852static struct tz1090_muxdesc *tz1090_submux[] = {
853 SUBMUX(EXT_DAC, ext_dac),
854};
855
856/*
857 * These are the pin mux groups. Pin muxing can be enabled and disabled for each
858 * pin individually so these groups are internal. The mapping of pins to pin mux
859 * group is below (tz1090_mux_pins).
860 */
861static struct tz1090_pingroup tz1090_mux_groups[] = {
862 /* Muxing pin groups */
863 /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */
864 MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2),
865 MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2),
866 MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2),
867 MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2),
868 MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2),
869 MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3),
870};
871
872/*
873 * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[].
874 * Pins which aren't muxable to multiple peripherals are set to
875 * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable
876 * peripheral control of the pin.
877 *
878 * This array is initialised in tz1090_init_mux_pins().
879 */
880static u8 tz1090_mux_pins[NUM_GPIOS];
881
882/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */
883#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups)
884
885/**
886 * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping.
887 *
888 * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in
889 * each pin mux group in tz1090_mux_groups[].
890 *
891 * It is assumed that no pin mux groups overlap (share pins).
892 */
893static void __init tz1090_init_mux_pins(void)
894{
895 unsigned int g, p;
896 const struct tz1090_pingroup *grp;
897 const unsigned int *pin;
898
899 for (p = 0; p < NUM_GPIOS; ++p)
900 tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX;
901
902 grp = tz1090_mux_groups;
903 for (g = 0, grp = tz1090_mux_groups;
904 g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp)
905 for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin)
906 tz1090_mux_pins[*pin] = g;
907}
908
909/*
910 * These are the externally visible pin groups. Some of them allow group control
911 * of drive configuration. Some are just simple convenience pingroups. All the
912 * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the
913 * same pins.
914 * Pseudo pin groups follow in the group numbers after this array for each GPIO
915 * pin. Any group used for muxing must have all pins belonging to the same pin
916 * mux group.
917 */
918static struct tz1090_pingroup tz1090_groups[] = {
919 /* Pin groups with drive control (with no out of place pins) */
920 /* pg_name, slw/schmitt/drv b */
921 DRV_PG(jtag, 11 /* 11, 22 */),
922 DRV_PG(tft, 10 /* 10, 20 */),
923 DRV_PG(scb2, 9 /* 9, 18 */),
924 DRV_PG(spi0, 7 /* 7, 14 */),
925 DRV_PG(uart, 5 /* 5, 10 */),
926 DRV_PG(scb1, 4 /* 4, 8 */),
927 DRV_PG(spi1, 3 /* 3, 6 */),
928 DRV_PG(afe, 0 /* 0, 0 */),
929
930 /*
931 * Drive specific pin groups (with odd combinations of pins which makes
932 * the pin group naming somewhat arbitrary)
933 */
934 /* pg_name, slw/schmitt/drv b */
935 DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */
936 DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */
937 DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */
938 DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */
939
940 /* Convenience pin groups */
941 /* pg_name */
942 SIMPLE_PG(uart0),
943 SIMPLE_PG(uart1),
944 SIMPLE_PG(scb0),
945 SIMPLE_PG(i2s),
946 SIMPLE_PG(sdh),
947 SIMPLE_PG(sdio),
948
949 /* pseudo-pingroups for each GPIO pin follow */
950};
951
952/**
953 * struct tz1090_pmx - Private pinctrl data
954 * @dev: Platform device
955 * @pctl: Pin control device
956 * @regs: Register region
957 * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs
958 * @pin_en: Pins that have been enabled (32 pins packed into each element)
959 * @gpio_en: GPIOs that have been enabled (32 pins packed into each element)
960 */
961struct tz1090_pmx {
962 struct device *dev;
963 struct pinctrl_dev *pctl;
964 void __iomem *regs;
965 spinlock_t lock;
966 u32 pin_en[3];
967 u32 gpio_en[3];
968};
969
970static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg)
971{
972 return ioread32(pmx->regs + reg);
973}
974
975static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg)
976{
977 iowrite32(val, pmx->regs + reg);
978}
979
980/*
981 * Pin control operations
982 */
983
984/* each GPIO pin has it's own pseudo pingroup containing only itself */
985
986static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
987{
988 return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS;
989}
990
991static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
992 unsigned int group)
993{
994 if (group < ARRAY_SIZE(tz1090_groups)) {
995 /* normal pingroup */
996 return tz1090_groups[group].name;
997 } else {
998 /* individual gpio pin pseudo-pingroup */
999 unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
1000 return tz1090_pins[pin].name;
1001 }
1002}
1003
1004static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1005 unsigned int group,
1006 const unsigned int **pins,
1007 unsigned int *num_pins)
1008{
1009 if (group < ARRAY_SIZE(tz1090_groups)) {
1010 /* normal pingroup */
1011 *pins = tz1090_groups[group].pins;
1012 *num_pins = tz1090_groups[group].npins;
1013 } else {
1014 /* individual gpio pin pseudo-pingroup */
1015 unsigned int pin = group - ARRAY_SIZE(tz1090_groups);
1016 *pins = &tz1090_pins[pin].number;
1017 *num_pins = 1;
1018 }
1019
1020 return 0;
1021}
1022
1023#ifdef CONFIG_DEBUG_FS
1024static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1025 struct seq_file *s,
1026 unsigned int offset)
1027{
1028 seq_printf(s, " %s", dev_name(pctldev->dev));
1029}
1030#endif
1031
1032static int reserve_map(struct device *dev, struct pinctrl_map **map,
1033 unsigned int *reserved_maps, unsigned int *num_maps,
1034 unsigned int reserve)
1035{
1036 unsigned int old_num = *reserved_maps;
1037 unsigned int new_num = *num_maps + reserve;
1038 struct pinctrl_map *new_map;
1039
1040 if (old_num >= new_num)
1041 return 0;
1042
1043 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1044 if (!new_map) {
1045 dev_err(dev, "krealloc(map) failed\n");
1046 return -ENOMEM;
1047 }
1048
1049 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1050
1051 *map = new_map;
1052 *reserved_maps = new_num;
1053
1054 return 0;
1055}
1056
1057static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
1058 unsigned int *num_maps, const char *group,
1059 const char *function)
1060{
1061 if (WARN_ON(*num_maps == *reserved_maps))
1062 return -ENOSPC;
1063
1064 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1065 (*map)[*num_maps].data.mux.group = group;
1066 (*map)[*num_maps].data.mux.function = function;
1067 (*num_maps)++;
1068
1069 return 0;
1070}
1071
1072static int add_map_configs(struct device *dev,
1073 struct pinctrl_map **map,
1074 unsigned int *reserved_maps, unsigned int *num_maps,
1075 const char *group, unsigned long *configs,
1076 unsigned int num_configs)
1077{
1078 unsigned long *dup_configs;
1079
1080 if (WARN_ON(*num_maps == *reserved_maps))
1081 return -ENOSPC;
1082
1083 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1084 GFP_KERNEL);
1085 if (!dup_configs) {
1086 dev_err(dev, "kmemdup(configs) failed\n");
1087 return -ENOMEM;
1088 }
1089
1090 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
1091 (*map)[*num_maps].data.configs.group_or_pin = group;
1092 (*map)[*num_maps].data.configs.configs = dup_configs;
1093 (*map)[*num_maps].data.configs.num_configs = num_configs;
1094 (*num_maps)++;
1095
1096 return 0;
1097}
1098
1099static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1100 struct pinctrl_map *map,
1101 unsigned int num_maps)
1102{
1103 int i;
1104
1105 for (i = 0; i < num_maps; i++)
1106 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1107 kfree(map[i].data.configs.configs);
1108
1109 kfree(map);
1110}
1111
1112static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev,
1113 struct device_node *np,
1114 struct pinctrl_map **map,
1115 unsigned int *reserved_maps,
1116 unsigned int *num_maps)
1117{
1118 int ret;
1119 const char *function;
1120 unsigned long *configs = NULL;
1121 unsigned int num_configs = 0;
1122 unsigned int reserve;
1123 struct property *prop;
1124 const char *group;
1125
1126 ret = of_property_read_string(np, "tz1090,function", &function);
1127 if (ret < 0) {
1128 /* EINVAL=missing, which is fine since it's optional */
1129 if (ret != -EINVAL)
1130 dev_err(dev, "could not parse property function\n");
1131 function = NULL;
1132 }
1133
1134 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
1135 if (ret)
1136 return ret;
1137
1138 reserve = 0;
1139 if (function != NULL)
1140 reserve++;
1141 if (num_configs)
1142 reserve++;
1143 ret = of_property_count_strings(np, "tz1090,pins");
1144 if (ret < 0) {
1145 dev_err(dev, "could not parse property pins\n");
1146 goto exit;
1147 }
1148 reserve *= ret;
1149
1150 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
1151 if (ret < 0)
1152 goto exit;
1153
1154 of_property_for_each_string(np, "tz1090,pins", prop, group) {
1155 if (function) {
1156 ret = add_map_mux(map, reserved_maps, num_maps,
1157 group, function);
1158 if (ret < 0)
1159 goto exit;
1160 }
1161
1162 if (num_configs) {
1163 ret = add_map_configs(dev, map, reserved_maps,
1164 num_maps, group, configs,
1165 num_configs);
1166 if (ret < 0)
1167 goto exit;
1168 }
1169 }
1170
1171 ret = 0;
1172
1173exit:
1174 kfree(configs);
1175 return ret;
1176}
1177
1178static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1179 struct device_node *np_config,
1180 struct pinctrl_map **map,
1181 unsigned int *num_maps)
1182{
1183 unsigned int reserved_maps;
1184 struct device_node *np;
1185 int ret;
1186
1187 reserved_maps = 0;
1188 *map = NULL;
1189 *num_maps = 0;
1190
1191 for_each_child_of_node(np_config, np) {
1192 ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
1193 &reserved_maps,
1194 num_maps);
1195 if (ret < 0) {
1196 tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1197 return ret;
1198 }
1199 }
1200
1201 return 0;
1202}
1203
1204static struct pinctrl_ops tz1090_pinctrl_ops = {
1205 .get_groups_count = tz1090_pinctrl_get_groups_count,
1206 .get_group_name = tz1090_pinctrl_get_group_name,
1207 .get_group_pins = tz1090_pinctrl_get_group_pins,
1208#ifdef CONFIG_DEBUG_FS
1209 .pin_dbg_show = tz1090_pinctrl_pin_dbg_show,
1210#endif
1211 .dt_node_to_map = tz1090_pinctrl_dt_node_to_map,
1212 .dt_free_map = tz1090_pinctrl_dt_free_map,
1213};
1214
1215/*
1216 * Pin mux operations
1217 */
1218
1219static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
1220{
1221 return ARRAY_SIZE(tz1090_functions);
1222}
1223
1224static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
1225 unsigned int function)
1226{
1227 return tz1090_functions[function].name;
1228}
1229
1230static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
1231 unsigned int function,
1232 const char * const **groups,
1233 unsigned int * const num_groups)
1234{
1235 /* pingroup functions */
1236 *groups = tz1090_functions[function].groups;
1237 *num_groups = tz1090_functions[function].ngroups;
1238 return 0;
1239}
1240
1241/**
1242 * tz1090_pinctrl_select() - update bit in SELECT register
1243 * @pmx: Pinmux data
1244 * @pin: Pin number (must be within GPIO range)
1245 */
1246static void tz1090_pinctrl_select(struct tz1090_pmx *pmx,
1247 unsigned int pin)
1248{
1249 u32 reg, reg_shift, select, val;
1250 unsigned int pmx_index, pmx_shift;
1251 unsigned long flags;
1252
1253 /* uses base 32 instead of base 30 */
1254 pmx_index = pin >> 5;
1255 pmx_shift = pin & 0x1f;
1256
1257 /* select = !perip || gpio */
1258 select = ((~pmx->pin_en[pmx_index] |
1259 pmx->gpio_en[pmx_index]) >> pmx_shift) & 1;
1260
1261 /* find register and bit offset (base 30) */
1262 reg = REG_PINCTRL_SELECT + 4*(pin / 30);
1263 reg_shift = pin % 30;
1264
1265 /* modify gpio select bit */
1266 __global_lock2(flags);
1267 val = pmx_read(pmx, reg);
1268 val &= ~BIT(reg_shift);
1269 val |= select << reg_shift;
1270 pmx_write(pmx, val, reg);
1271 __global_unlock2(flags);
1272}
1273
1274/**
1275 * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin
1276 * @pmx: Pinmux data
1277 * @pin: Pin number
1278 * @gpio_select: true to enable pin as GPIO,
1279 * false to leave control to whatever function is enabled
1280 *
1281 * Records that GPIO usage is enabled/disabled so that enabling a function
1282 * doesn't override the SELECT register bit.
1283 */
1284static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx,
1285 unsigned int pin,
1286 bool gpio_select)
1287{
1288 unsigned int index, shift;
1289 u32 gpio_en;
1290
1291 if (pin >= NUM_GPIOS)
1292 return;
1293
1294 /* uses base 32 instead of base 30 */
1295 index = pin >> 5;
1296 shift = pin & 0x1f;
1297
1298 spin_lock(&pmx->lock);
1299
1300 /* keep a record whether gpio is selected */
1301 gpio_en = pmx->gpio_en[index];
1302 gpio_en &= ~BIT(shift);
1303 if (gpio_select)
1304 gpio_en |= BIT(shift);
1305 pmx->gpio_en[index] = gpio_en;
1306
1307 /* update the select bit */
1308 tz1090_pinctrl_select(pmx, pin);
1309
1310 spin_unlock(&pmx->lock);
1311}
1312
1313/**
1314 * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin
1315 * @pmx: Pinmux data
1316 * @pin: Pin number
1317 * @perip_select: true to enable peripheral interface when not GPIO,
1318 * false to leave pin in GPIO mode
1319 *
1320 * Records that peripheral usage is enabled/disabled so that SELECT register can
1321 * be set appropriately when GPIO is disabled.
1322 */
1323static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx,
1324 unsigned int pin,
1325 bool perip_select)
1326{
1327 unsigned int index, shift;
1328 u32 pin_en;
1329
1330 if (pin >= NUM_GPIOS)
1331 return;
1332
1333 /* uses base 32 instead of base 30 */
1334 index = pin >> 5;
1335 shift = pin & 0x1f;
1336
1337 spin_lock(&pmx->lock);
1338
1339 /* keep a record whether peripheral is selected */
1340 pin_en = pmx->pin_en[index];
1341 pin_en &= ~BIT(shift);
1342 if (perip_select)
1343 pin_en |= BIT(shift);
1344 pmx->pin_en[index] = pin_en;
1345
1346 /* update the select bit */
1347 tz1090_pinctrl_select(pmx, pin);
1348
1349 spin_unlock(&pmx->lock);
1350}
1351
1352/**
1353 * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function.
1354 * @pmx: Pinmux data
1355 * @desc: Pinmux description
1356 * @function: Function to switch to
1357 *
1358 * Enable a particular function on a pin mux group. Since pin mux descriptions
1359 * are nested this function is recursive.
1360 */
1361static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx,
1362 const struct tz1090_muxdesc *desc,
1363 unsigned int function)
1364{
1365 const int *fit;
1366 unsigned long flags;
1367 int mux;
1368 unsigned int func, ret;
1369 u32 reg, mask;
1370
1371 /* find the mux value for this function, searching recursively */
1372 for (mux = 0, fit = desc->funcs;
1373 mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) {
1374 func = *fit;
1375 if (func == function)
1376 goto found_mux;
1377
1378 /* maybe it's a sub-mux */
1379 if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) {
1380 ret = tz1090_pinctrl_enable_mux(pmx,
1381 tz1090_submux[func],
1382 function);
1383 if (!ret)
1384 goto found_mux;
1385 }
1386 }
1387
1388 return -EINVAL;
1389found_mux:
1390
1391 /* Set up the mux */
1392 if (desc->width) {
1393 mask = (BIT(desc->width) - 1) << desc->bit;
1394 __global_lock2(flags);
1395 reg = pmx_read(pmx, desc->reg);
1396 reg &= ~mask;
1397 reg |= (mux << desc->bit) & mask;
1398 pmx_write(pmx, reg, desc->reg);
1399 __global_unlock2(flags);
1400 }
1401
1402 return 0;
1403}
1404
1405/**
1406 * tz1090_pinctrl_enable() - Enable a function on a pin group.
1407 * @pctldev: Pin control data
1408 * @function: Function index to enable
1409 * @group: Group index to enable
1410 *
1411 * Enable a particular function on a group of pins. The per GPIO pin pseudo pin
1412 * groups can be used (in which case the pin will be enabled in peripheral mode
1413 * and if it belongs to a pin mux group the mux will be switched if it isn't
1414 * already in use. Some convenience pin groups can also be used in which case
1415 * the effect is the same as enabling the function on each individual pin in the
1416 * group.
1417 */
1418static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev,
1419 unsigned int function, unsigned int group)
1420{
1421 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1422 struct tz1090_pingroup *grp;
1423 int ret;
1424 unsigned int pin_num, mux_group, i, npins;
1425 const unsigned int *pins;
1426
1427 /* group of pins? */
1428 if (group < ARRAY_SIZE(tz1090_groups)) {
1429 grp = &tz1090_groups[group];
1430 npins = grp->npins;
1431 pins = grp->pins;
1432 /*
1433 * All pins in the group must belong to the same mux group,
1434 * which allows us to just use the mux group of the first pin.
1435 * By explicitly listing permitted pingroups for each function
1436 * the pinmux core should ensure this is always the case.
1437 */
1438 } else {
1439 pin_num = group - ARRAY_SIZE(tz1090_groups);
1440 npins = 1;
1441 pins = &pin_num;
1442 }
1443 mux_group = tz1090_mux_pins[*pins];
1444
1445 /* no mux group, but can still be individually muxed to peripheral */
1446 if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1447 if (function == TZ1090_MUX_PERIP)
1448 goto mux_pins;
1449 return -EINVAL;
1450 }
1451
1452 /* mux group already set to a different function? */
1453 grp = &tz1090_mux_groups[mux_group];
1454 if (grp->func_count && grp->func != function) {
1455 dev_err(pctldev->dev,
1456 "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n",
1457 __func__, tz1090_functions[function].name,
1458 tz1090_functions[grp->func].name);
1459 return -EBUSY;
1460 }
1461
1462 dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n",
1463 __func__, npins, grp->name, tz1090_functions[function].name);
1464
1465 /* if first pin in mux group to be enabled, enable the group mux */
1466 if (!grp->func_count) {
1467 grp->func = function;
1468 ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function);
1469 if (ret)
1470 return ret;
1471 }
1472 /* add pins to ref count and mux individually to peripheral */
1473 grp->func_count += npins;
1474mux_pins:
1475 for (i = 0; i < npins; ++i)
1476 tz1090_pinctrl_perip_select(pmx, pins[i], true);
1477
1478 return 0;
1479}
1480
1481/**
1482 * tz1090_pinctrl_disable() - Disable a function on a pin group.
1483 * @pctldev: Pin control data
1484 * @function: Function index to disable
1485 * @group: Group index to disable
1486 *
1487 * Disable a particular function on a group of pins. The per GPIO pin pseudo pin
1488 * groups can be used (in which case the pin will be taken out of peripheral
1489 * mode. Some convenience pin groups can also be used in which case the effect
1490 * is the same as enabling the function on each individual pin in the group.
1491 */
1492static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev,
1493 unsigned int function, unsigned int group)
1494{
1495 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1496 struct tz1090_pingroup *grp;
1497 unsigned int pin_num, mux_group, i, npins;
1498 const unsigned int *pins;
1499
1500 /* group of pins? */
1501 if (group < ARRAY_SIZE(tz1090_groups)) {
1502 grp = &tz1090_groups[group];
1503 npins = grp->npins;
1504 pins = grp->pins;
1505 /*
1506 * All pins in the group must belong to the same mux group,
1507 * which allows us to just use the mux group of the first pin.
1508 * By explicitly listing permitted pingroups for each function
1509 * the pinmux core should ensure this is always the case.
1510 */
1511 } else {
1512 pin_num = group - ARRAY_SIZE(tz1090_groups);
1513 npins = 1;
1514 pins = &pin_num;
1515 }
1516 mux_group = tz1090_mux_pins[*pins];
1517
1518 /* no mux group, but can still be individually muxed to peripheral */
1519 if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1520 if (function == TZ1090_MUX_PERIP)
1521 goto unmux_pins;
1522 return;
1523 }
1524
1525 /* mux group already set to a different function? */
1526 grp = &tz1090_mux_groups[mux_group];
1527 dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n",
1528 __func__, npins, grp->name, tz1090_functions[function].name);
1529
1530 /* subtract pins from ref count and unmux individually */
1531 WARN_ON(grp->func_count < npins);
1532 grp->func_count -= npins;
1533unmux_pins:
1534 for (i = 0; i < npins; ++i)
1535 tz1090_pinctrl_perip_select(pmx, pins[i], false);
1536}
1537
1538/**
1539 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
1540 * @pctldev: Pin control data
1541 * @range: GPIO range
1542 * @pin: Pin number
1543 *
1544 * Puts a particular pin into GPIO mode, disabling peripheral control until it's
1545 * disabled again.
1546 */
1547static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
1548 struct pinctrl_gpio_range *range,
1549 unsigned int pin)
1550{
1551 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1552 tz1090_pinctrl_gpio_select(pmx, pin, true);
1553 return 0;
1554}
1555
1556/**
1557 * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode.
1558 * @pctldev: Pin control data
1559 * @range: GPIO range
1560 * @pin: Pin number
1561 *
1562 * Take a particular pin out of GPIO mode. If the pin is enabled for a
1563 * peripheral it will return to peripheral mode.
1564 */
1565static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
1566 struct pinctrl_gpio_range *range,
1567 unsigned int pin)
1568{
1569 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1570 tz1090_pinctrl_gpio_select(pmx, pin, false);
1571}
1572
1573static struct pinmux_ops tz1090_pinmux_ops = {
1574 .get_functions_count = tz1090_pinctrl_get_funcs_count,
1575 .get_function_name = tz1090_pinctrl_get_func_name,
1576 .get_function_groups = tz1090_pinctrl_get_func_groups,
1577 .enable = tz1090_pinctrl_enable,
1578 .disable = tz1090_pinctrl_disable,
1579 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
1580 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
1581};
1582
1583/*
1584 * Pin config operations
1585 */
1586
1587struct tz1090_pinconf_pullup {
1588 unsigned char index;
1589 unsigned char shift;
1590};
1591
1592/* The mapping of pin to pull up/down register index and shift */
1593static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = {
1594 {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */
1595 {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */
1596 {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */
1597 {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */
1598 {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */
1599 {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */
1600 {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */
1601 {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */
1602 {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */
1603 {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */
1604 {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */
1605 {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */
1606 {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */
1607 {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */
1608 {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */
1609 {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */
1610 {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */
1611 {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */
1612 {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */
1613 {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */
1614 {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */
1615 {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */
1616 {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */
1617 {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */
1618 {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */
1619 {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */
1620 {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */
1621 {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */
1622 {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */
1623 {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */
1624
1625 {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */
1626 {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */
1627 {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */
1628 {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */
1629 {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */
1630 {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */
1631 {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */
1632 {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */
1633 {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */
1634 {4, 12}, /* 39 - TZ1090_PIN_PDM_A */
1635 {4, 14}, /* 40 - TZ1090_PIN_PDM_B */
1636 {4, 18}, /* 41 - TZ1090_PIN_PDM_C */
1637 {4, 20}, /* 42 - TZ1090_PIN_PDM_D */
1638 {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */
1639 {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */
1640 {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */
1641 {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */
1642 {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */
1643 {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */
1644 {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */
1645 {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */
1646 {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */
1647 {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */
1648 {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */
1649 {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */
1650 {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */
1651 {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */
1652 {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */
1653 {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */
1654 {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */
1655
1656 {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */
1657 {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */
1658 {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */
1659 {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */
1660 {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */
1661 {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */
1662 {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */
1663 {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */
1664 {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */
1665 {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */
1666 {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */
1667 {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */
1668 {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */
1669 {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */
1670 {4, 24}, /* 74 - TZ1090_PIN_TX_ON */
1671 {4, 26}, /* 75 - TZ1090_PIN_RX_ON */
1672 {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */
1673 {4, 30}, /* 77 - TZ1090_PIN_PA_ON */
1674 {5, 0}, /* 78 - TZ1090_PIN_RX_HP */
1675 {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */
1676 {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */
1677 {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */
1678 {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */
1679 {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */
1680 {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */
1681 {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */
1682 {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */
1683 {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */
1684 {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */
1685 {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */
1686
1687 {5, 24}, /* 90 - TZ1090_PIN_TCK */
1688 {5, 26}, /* 91 - TZ1090_PIN_TRST */
1689 {5, 28}, /* 92 - TZ1090_PIN_TDI */
1690 {5, 30}, /* 93 - TZ1090_PIN_TDO */
1691 {6, 0}, /* 94 - TZ1090_PIN_TMS */
1692 {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */
1693 {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */
1694};
1695
1696static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev,
1697 unsigned int pin,
1698 enum pin_config_param param,
1699 bool report_err,
1700 u32 *reg, u32 *width, u32 *mask, u32 *shift,
1701 u32 *val)
1702{
1703 struct tz1090_pinconf_pullup *pu;
1704
1705 /* All supported pins have controllable input bias */
1706 switch (param) {
1707 case PIN_CONFIG_BIAS_DISABLE:
1708 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1709 *val = REG_PU_PD_TRISTATE;
1710 break;
1711 case PIN_CONFIG_BIAS_PULL_UP:
1712 *val = REG_PU_PD_UP;
1713 break;
1714 case PIN_CONFIG_BIAS_PULL_DOWN:
1715 *val = REG_PU_PD_DOWN;
1716 break;
1717 case PIN_CONFIG_BIAS_BUS_HOLD:
1718 *val = REG_PU_PD_REPEATER;
1719 break;
1720 default:
1721 return -ENOTSUPP;
1722 };
1723
1724 /* Only input bias parameters supported */
1725 pu = &tz1090_pinconf_pullup[pin];
1726 *reg = REG_PINCTRL_PU_PD + 4*pu->index;
1727 *shift = pu->shift;
1728 *width = 2;
1729
1730 /* Calculate field information */
1731 *mask = (BIT(*width) - 1) << *shift;
1732
1733 return 0;
1734}
1735
1736static int tz1090_pinconf_get(struct pinctrl_dev *pctldev,
1737 unsigned int pin, unsigned long *config)
1738{
1739 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1740 enum pin_config_param param = pinconf_to_config_param(*config);
1741 int ret;
1742 u32 reg, width, mask, shift, val, tmp, arg;
1743
1744 /* Get register information */
1745 ret = tz1090_pinconf_reg(pctldev, pin, param, true,
1746 &reg, &width, &mask, &shift, &val);
1747 if (ret < 0)
1748 return ret;
1749
1750 /* Extract field from register */
1751 tmp = pmx_read(pmx, reg);
1752 arg = ((tmp & mask) >> shift) == val;
1753
1754 /* Config not active */
1755 if (!arg)
1756 return -EINVAL;
1757
1758 /* And pack config */
1759 *config = pinconf_to_config_packed(param, arg);
1760
1761 return 0;
1762}
1763
1764static int tz1090_pinconf_set(struct pinctrl_dev *pctldev,
1765 unsigned int pin, unsigned long config)
1766{
1767 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1768 enum pin_config_param param = pinconf_to_config_param(config);
1769 unsigned int arg = pinconf_to_config_argument(config);
1770 int ret;
1771 u32 reg, width, mask, shift, val, tmp;
1772 unsigned long flags;
1773
1774 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
1775 __func__, tz1090_pins[pin].name, config);
1776
1777 /* Get register information */
1778 ret = tz1090_pinconf_reg(pctldev, pin, param, true,
1779 &reg, &width, &mask, &shift, &val);
1780 if (ret < 0)
1781 return ret;
1782
1783 /* Unpack argument and range check it */
1784 if (arg > 1) {
1785 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
1786 __func__, arg);
1787 return -EINVAL;
1788 }
1789
1790 /* Write register field */
1791 __global_lock2(flags);
1792 tmp = pmx_read(pmx, reg);
1793 tmp &= ~mask;
1794 if (arg)
1795 tmp |= val << shift;
1796 pmx_write(pmx, tmp, reg);
1797 __global_unlock2(flags);
1798
1799 return 0;
1800}
1801
1802static const int tz1090_boolean_map[] = {
1803 [0] = -EINVAL,
1804 [1] = 1,
1805};
1806
1807static const int tz1090_dr_map[] = {
1808 [REG_DR_2mA] = 2,
1809 [REG_DR_4mA] = 4,
1810 [REG_DR_8mA] = 8,
1811 [REG_DR_12mA] = 12,
1812};
1813
1814static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev,
1815 const struct tz1090_pingroup *g,
1816 enum pin_config_param param,
1817 bool report_err,
1818 u32 *reg, u32 *width, u32 *mask, u32 *shift,
1819 const int **map)
1820{
1821 /* Drive configuration applies in groups, but not to all groups. */
1822 if (!g->drv) {
1823 if (report_err)
1824 dev_dbg(pctldev->dev,
1825 "%s: group %s has no drive control\n",
1826 __func__, g->name);
1827 return -ENOTSUPP;
1828 }
1829
1830 /* Find information about drive parameter's register */
1831 switch (param) {
1832 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1833 *reg = REG_PINCTRL_SCHMITT;
1834 *width = 1;
1835 *map = tz1090_boolean_map;
1836 break;
1837 case PIN_CONFIG_DRIVE_STRENGTH:
1838 *reg = REG_PINCTRL_DR;
1839 *width = 2;
1840 *map = tz1090_dr_map;
1841 break;
1842 default:
1843 return -ENOTSUPP;
1844 };
1845
1846 /* Calculate field information */
1847 *shift = g->slw_bit * *width;
1848 *mask = (BIT(*width) - 1) << *shift;
1849
1850 return 0;
1851}
1852
1853static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev,
1854 unsigned int group,
1855 unsigned long *config)
1856{
1857 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1858 const struct tz1090_pingroup *g;
1859 enum pin_config_param param = pinconf_to_config_param(*config);
1860 int ret, arg;
1861 unsigned int pin;
1862 u32 reg, width, mask, shift, val;
1863 const int *map;
1864
1865 if (group >= ARRAY_SIZE(tz1090_groups)) {
1866 pin = group - ARRAY_SIZE(tz1090_groups);
1867 return tz1090_pinconf_get(pctldev, pin, config);
1868 }
1869
1870 g = &tz1090_groups[group];
1871 if (g->npins == 1) {
1872 pin = g->pins[0];
1873 ret = tz1090_pinconf_get(pctldev, pin, config);
1874 if (ret != -ENOTSUPP)
1875 return ret;
1876 }
1877
1878 /* Get register information */
1879 ret = tz1090_pinconf_group_reg(pctldev, g, param, true,
1880 &reg, &width, &mask, &shift, &map);
1881 if (ret < 0)
1882 return ret;
1883
1884 /* Extract field from register */
1885 val = pmx_read(pmx, reg);
1886 arg = map[(val & mask) >> shift];
1887 if (arg < 0)
1888 return arg;
1889
1890 /* And pack config */
1891 *config = pinconf_to_config_packed(param, arg);
1892
1893 return 0;
1894}
1895
1896static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev,
1897 unsigned int group, unsigned long config)
1898{
1899 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1900 const struct tz1090_pingroup *g;
1901 enum pin_config_param param = pinconf_to_config_param(config);
1902 unsigned int arg, pin, i;
1903 const unsigned int *pit;
1904 int ret;
1905 u32 reg, width, mask, shift, val;
1906 unsigned long flags;
1907 const int *map;
1908
1909 if (group >= ARRAY_SIZE(tz1090_groups)) {
1910 pin = group - ARRAY_SIZE(tz1090_groups);
1911 return tz1090_pinconf_set(pctldev, pin, config);
1912 }
1913
1914 g = &tz1090_groups[group];
1915 if (g->npins == 1) {
1916 pin = g->pins[0];
1917 ret = tz1090_pinconf_set(pctldev, pin, config);
1918 if (ret != -ENOTSUPP)
1919 return ret;
1920 }
1921
1922 dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
1923 __func__, g->name, config);
1924
1925 /* Get register information */
1926 ret = tz1090_pinconf_group_reg(pctldev, g, param, true,
1927 &reg, &width, &mask, &shift, &map);
1928 if (ret < 0) {
1929 /*
1930 * Maybe we're trying to set a per-pin configuration of a group,
1931 * so do the pins one by one. This is mainly as a convenience.
1932 */
1933 for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
1934 ret = tz1090_pinconf_set(pctldev, *pit, config);
1935 if (ret)
1936 return ret;
1937 }
1938 return 0;
1939 }
1940
1941 /* Unpack argument and map it to register value */
1942 arg = pinconf_to_config_argument(config);
1943 for (i = 0; i < BIT(width); ++i) {
1944 if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
1945 /* Write register field */
1946 __global_lock2(flags);
1947 val = pmx_read(pmx, reg);
1948 val &= ~mask;
1949 val |= i << shift;
1950 pmx_write(pmx, val, reg);
1951 __global_unlock2(flags);
1952 return 0;
1953 }
1954 }
1955
1956 dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
1957 __func__, arg);
1958 return -EINVAL;
1959}
1960
1961static struct pinconf_ops tz1090_pinconf_ops = {
1962 .is_generic = true,
1963 .pin_config_get = tz1090_pinconf_get,
1964 .pin_config_set = tz1090_pinconf_set,
1965 .pin_config_group_get = tz1090_pinconf_group_get,
1966 .pin_config_group_set = tz1090_pinconf_group_set,
1967 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1968};
1969
1970/*
1971 * Pin control driver setup
1972 */
1973
1974static struct pinctrl_desc tz1090_pinctrl_desc = {
1975 .pctlops = &tz1090_pinctrl_ops,
1976 .pmxops = &tz1090_pinmux_ops,
1977 .confops = &tz1090_pinconf_ops,
1978 .owner = THIS_MODULE,
1979};
1980
1981static int tz1090_pinctrl_probe(struct platform_device *pdev)
1982{
1983 struct tz1090_pmx *pmx;
1984 struct resource *res;
1985
1986 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
1987 if (!pmx) {
1988 dev_err(&pdev->dev, "Can't alloc tz1090_pmx\n");
1989 return -ENOMEM;
1990 }
1991 pmx->dev = &pdev->dev;
1992 spin_lock_init(&pmx->lock);
1993
1994 tz1090_pinctrl_desc.name = dev_name(&pdev->dev);
1995 tz1090_pinctrl_desc.pins = tz1090_pins;
1996 tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins);
1997
1998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1999 if (!res) {
2000 dev_err(&pdev->dev, "Missing MEM resource\n");
2001 return -ENODEV;
2002 }
2003
2004 if (!devm_request_mem_region(&pdev->dev, res->start,
2005 resource_size(res),
2006 dev_name(&pdev->dev))) {
2007 dev_err(&pdev->dev,
2008 "Couldn't request MEM resource\n");
2009 return -ENODEV;
2010 }
2011
2012 pmx->regs = devm_ioremap(&pdev->dev, res->start,
2013 resource_size(res));
2014 if (!pmx->regs) {
2015 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
2016 return -ENODEV;
2017 }
2018
2019 pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx);
2020 if (!pmx->pctl) {
2021 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
2022 return -ENODEV;
2023 }
2024
2025 platform_set_drvdata(pdev, pmx);
2026
2027 dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n");
2028
2029 return 0;
2030}
2031
2032static int tz1090_pinctrl_remove(struct platform_device *pdev)
2033{
2034 struct tz1090_pmx *pmx = platform_get_drvdata(pdev);
2035
2036 pinctrl_unregister(pmx->pctl);
2037
2038 return 0;
2039}
2040
2041static struct of_device_id tz1090_pinctrl_of_match[] = {
2042 { .compatible = "img,tz1090-pinctrl", },
2043 { },
2044};
2045
2046static struct platform_driver tz1090_pinctrl_driver = {
2047 .driver = {
2048 .name = "tz1090-pinctrl",
2049 .owner = THIS_MODULE,
2050 .of_match_table = tz1090_pinctrl_of_match,
2051 },
2052 .probe = tz1090_pinctrl_probe,
2053 .remove = tz1090_pinctrl_remove,
2054};
2055
2056static int __init tz1090_pinctrl_init(void)
2057{
2058 tz1090_init_mux_pins();
2059 return platform_driver_register(&tz1090_pinctrl_driver);
2060}
2061arch_initcall(tz1090_pinctrl_init);
2062
2063static void __exit tz1090_pinctrl_exit(void)
2064{
2065 platform_driver_unregister(&tz1090_pinctrl_driver);
2066}
2067module_exit(tz1090_pinctrl_exit);
2068
2069MODULE_AUTHOR("Imagination Technologies Ltd.");
2070MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver");
2071MODULE_LICENSE("GPL v2");
2072MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 06bfa09bb15c..46a152d17355 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1100,7 +1100,6 @@ static int u300_pmx_remove(struct platform_device *pdev)
1100 struct u300_pmx *upmx = platform_get_drvdata(pdev); 1100 struct u300_pmx *upmx = platform_get_drvdata(pdev);
1101 1101
1102 pinctrl_unregister(upmx->pctl); 1102 pinctrl_unregister(upmx->pctl);
1103 platform_set_drvdata(pdev, NULL);
1104 1103
1105 return 0; 1104 return 0;
1106} 1105}
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
new file mode 100644
index 000000000000..68a970b1dbcf
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-vf610.c
@@ -0,0 +1,338 @@
1/*
2 * VF610 pinctrl driver based on imx pinmux and pinconf core
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-imx.h"
21
22enum vf610_pads {
23 VF610_PAD_PTA6 = 0,
24 VF610_PAD_PTA8 = 1,
25 VF610_PAD_PTA9 = 2,
26 VF610_PAD_PTA10 = 3,
27 VF610_PAD_PTA11 = 4,
28 VF610_PAD_PTA12 = 5,
29 VF610_PAD_PTA16 = 6,
30 VF610_PAD_PTA17 = 7,
31 VF610_PAD_PTA18 = 8,
32 VF610_PAD_PTA19 = 9,
33 VF610_PAD_PTA20 = 10,
34 VF610_PAD_PTA21 = 11,
35 VF610_PAD_PTA22 = 12,
36 VF610_PAD_PTA23 = 13,
37 VF610_PAD_PTA24 = 14,
38 VF610_PAD_PTA25 = 15,
39 VF610_PAD_PTA26 = 16,
40 VF610_PAD_PTA27 = 17,
41 VF610_PAD_PTA28 = 18,
42 VF610_PAD_PTA29 = 19,
43 VF610_PAD_PTA30 = 20,
44 VF610_PAD_PTA31 = 21,
45 VF610_PAD_PTB0 = 22,
46 VF610_PAD_PTB1 = 23,
47 VF610_PAD_PTB2 = 24,
48 VF610_PAD_PTB3 = 25,
49 VF610_PAD_PTB4 = 26,
50 VF610_PAD_PTB5 = 27,
51 VF610_PAD_PTB6 = 28,
52 VF610_PAD_PTB7 = 29,
53 VF610_PAD_PTB8 = 30,
54 VF610_PAD_PTB9 = 31,
55 VF610_PAD_PTB10 = 32,
56 VF610_PAD_PTB11 = 33,
57 VF610_PAD_PTB12 = 34,
58 VF610_PAD_PTB13 = 35,
59 VF610_PAD_PTB14 = 36,
60 VF610_PAD_PTB15 = 37,
61 VF610_PAD_PTB16 = 38,
62 VF610_PAD_PTB17 = 39,
63 VF610_PAD_PTB18 = 40,
64 VF610_PAD_PTB19 = 41,
65 VF610_PAD_PTB20 = 42,
66 VF610_PAD_PTB21 = 43,
67 VF610_PAD_PTB22 = 44,
68 VF610_PAD_PTC0 = 45,
69 VF610_PAD_PTC1 = 46,
70 VF610_PAD_PTC2 = 47,
71 VF610_PAD_PTC3 = 48,
72 VF610_PAD_PTC4 = 49,
73 VF610_PAD_PTC5 = 50,
74 VF610_PAD_PTC6 = 51,
75 VF610_PAD_PTC7 = 52,
76 VF610_PAD_PTC8 = 53,
77 VF610_PAD_PTC9 = 54,
78 VF610_PAD_PTC10 = 55,
79 VF610_PAD_PTC11 = 56,
80 VF610_PAD_PTC12 = 57,
81 VF610_PAD_PTC13 = 58,
82 VF610_PAD_PTC14 = 59,
83 VF610_PAD_PTC15 = 60,
84 VF610_PAD_PTC16 = 61,
85 VF610_PAD_PTC17 = 62,
86 VF610_PAD_PTD31 = 63,
87 VF610_PAD_PTD30 = 64,
88 VF610_PAD_PTD29 = 65,
89 VF610_PAD_PTD28 = 66,
90 VF610_PAD_PTD27 = 67,
91 VF610_PAD_PTD26 = 68,
92 VF610_PAD_PTD25 = 69,
93 VF610_PAD_PTD24 = 70,
94 VF610_PAD_PTD23 = 71,
95 VF610_PAD_PTD22 = 72,
96 VF610_PAD_PTD21 = 73,
97 VF610_PAD_PTD20 = 74,
98 VF610_PAD_PTD19 = 75,
99 VF610_PAD_PTD18 = 76,
100 VF610_PAD_PTD17 = 77,
101 VF610_PAD_PTD16 = 78,
102 VF610_PAD_PTD0 = 79,
103 VF610_PAD_PTD1 = 80,
104 VF610_PAD_PTD2 = 81,
105 VF610_PAD_PTD3 = 82,
106 VF610_PAD_PTD4 = 83,
107 VF610_PAD_PTD5 = 84,
108 VF610_PAD_PTD6 = 85,
109 VF610_PAD_PTD7 = 86,
110 VF610_PAD_PTD8 = 87,
111 VF610_PAD_PTD9 = 88,
112 VF610_PAD_PTD10 = 89,
113 VF610_PAD_PTD11 = 90,
114 VF610_PAD_PTD12 = 91,
115 VF610_PAD_PTD13 = 92,
116 VF610_PAD_PTB23 = 93,
117 VF610_PAD_PTB24 = 94,
118 VF610_PAD_PTB25 = 95,
119 VF610_PAD_PTB26 = 96,
120 VF610_PAD_PTB27 = 97,
121 VF610_PAD_PTB28 = 98,
122 VF610_PAD_PTC26 = 99,
123 VF610_PAD_PTC27 = 100,
124 VF610_PAD_PTC28 = 101,
125 VF610_PAD_PTC29 = 102,
126 VF610_PAD_PTC30 = 103,
127 VF610_PAD_PTC31 = 104,
128 VF610_PAD_PTE0 = 105,
129 VF610_PAD_PTE1 = 106,
130 VF610_PAD_PTE2 = 107,
131 VF610_PAD_PTE3 = 108,
132 VF610_PAD_PTE4 = 109,
133 VF610_PAD_PTE5 = 110,
134 VF610_PAD_PTE6 = 111,
135 VF610_PAD_PTE7 = 112,
136 VF610_PAD_PTE8 = 113,
137 VF610_PAD_PTE9 = 114,
138 VF610_PAD_PTE10 = 115,
139 VF610_PAD_PTE11 = 116,
140 VF610_PAD_PTE12 = 117,
141 VF610_PAD_PTE13 = 118,
142 VF610_PAD_PTE14 = 119,
143 VF610_PAD_PTE15 = 120,
144 VF610_PAD_PTE16 = 121,
145 VF610_PAD_PTE17 = 122,
146 VF610_PAD_PTE18 = 123,
147 VF610_PAD_PTE19 = 124,
148 VF610_PAD_PTE20 = 125,
149 VF610_PAD_PTE21 = 126,
150 VF610_PAD_PTE22 = 127,
151 VF610_PAD_PTE23 = 128,
152 VF610_PAD_PTE24 = 129,
153 VF610_PAD_PTE25 = 130,
154 VF610_PAD_PTE26 = 131,
155 VF610_PAD_PTE27 = 132,
156 VF610_PAD_PTE28 = 133,
157 VF610_PAD_PTA7 = 134,
158};
159
160/* Pad names for the pinmux subsystem */
161static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
162 IMX_PINCTRL_PIN(VF610_PAD_PTA6),
163 IMX_PINCTRL_PIN(VF610_PAD_PTA8),
164 IMX_PINCTRL_PIN(VF610_PAD_PTA9),
165 IMX_PINCTRL_PIN(VF610_PAD_PTA10),
166 IMX_PINCTRL_PIN(VF610_PAD_PTA11),
167 IMX_PINCTRL_PIN(VF610_PAD_PTA12),
168 IMX_PINCTRL_PIN(VF610_PAD_PTA16),
169 IMX_PINCTRL_PIN(VF610_PAD_PTA17),
170 IMX_PINCTRL_PIN(VF610_PAD_PTA18),
171 IMX_PINCTRL_PIN(VF610_PAD_PTA19),
172 IMX_PINCTRL_PIN(VF610_PAD_PTA20),
173 IMX_PINCTRL_PIN(VF610_PAD_PTA21),
174 IMX_PINCTRL_PIN(VF610_PAD_PTA22),
175 IMX_PINCTRL_PIN(VF610_PAD_PTA23),
176 IMX_PINCTRL_PIN(VF610_PAD_PTA24),
177 IMX_PINCTRL_PIN(VF610_PAD_PTA25),
178 IMX_PINCTRL_PIN(VF610_PAD_PTA26),
179 IMX_PINCTRL_PIN(VF610_PAD_PTA27),
180 IMX_PINCTRL_PIN(VF610_PAD_PTA28),
181 IMX_PINCTRL_PIN(VF610_PAD_PTA29),
182 IMX_PINCTRL_PIN(VF610_PAD_PTA30),
183 IMX_PINCTRL_PIN(VF610_PAD_PTA31),
184 IMX_PINCTRL_PIN(VF610_PAD_PTB0),
185 IMX_PINCTRL_PIN(VF610_PAD_PTB1),
186 IMX_PINCTRL_PIN(VF610_PAD_PTB2),
187 IMX_PINCTRL_PIN(VF610_PAD_PTB3),
188 IMX_PINCTRL_PIN(VF610_PAD_PTB4),
189 IMX_PINCTRL_PIN(VF610_PAD_PTB5),
190 IMX_PINCTRL_PIN(VF610_PAD_PTB6),
191 IMX_PINCTRL_PIN(VF610_PAD_PTB7),
192 IMX_PINCTRL_PIN(VF610_PAD_PTB8),
193 IMX_PINCTRL_PIN(VF610_PAD_PTB9),
194 IMX_PINCTRL_PIN(VF610_PAD_PTB10),
195 IMX_PINCTRL_PIN(VF610_PAD_PTB11),
196 IMX_PINCTRL_PIN(VF610_PAD_PTB12),
197 IMX_PINCTRL_PIN(VF610_PAD_PTB13),
198 IMX_PINCTRL_PIN(VF610_PAD_PTB14),
199 IMX_PINCTRL_PIN(VF610_PAD_PTB15),
200 IMX_PINCTRL_PIN(VF610_PAD_PTB16),
201 IMX_PINCTRL_PIN(VF610_PAD_PTB17),
202 IMX_PINCTRL_PIN(VF610_PAD_PTB18),
203 IMX_PINCTRL_PIN(VF610_PAD_PTB19),
204 IMX_PINCTRL_PIN(VF610_PAD_PTB20),
205 IMX_PINCTRL_PIN(VF610_PAD_PTB21),
206 IMX_PINCTRL_PIN(VF610_PAD_PTB22),
207 IMX_PINCTRL_PIN(VF610_PAD_PTC0),
208 IMX_PINCTRL_PIN(VF610_PAD_PTC1),
209 IMX_PINCTRL_PIN(VF610_PAD_PTC2),
210 IMX_PINCTRL_PIN(VF610_PAD_PTC3),
211 IMX_PINCTRL_PIN(VF610_PAD_PTC4),
212 IMX_PINCTRL_PIN(VF610_PAD_PTC5),
213 IMX_PINCTRL_PIN(VF610_PAD_PTC6),
214 IMX_PINCTRL_PIN(VF610_PAD_PTC7),
215 IMX_PINCTRL_PIN(VF610_PAD_PTC8),
216 IMX_PINCTRL_PIN(VF610_PAD_PTC9),
217 IMX_PINCTRL_PIN(VF610_PAD_PTC10),
218 IMX_PINCTRL_PIN(VF610_PAD_PTC11),
219 IMX_PINCTRL_PIN(VF610_PAD_PTC12),
220 IMX_PINCTRL_PIN(VF610_PAD_PTC13),
221 IMX_PINCTRL_PIN(VF610_PAD_PTC14),
222 IMX_PINCTRL_PIN(VF610_PAD_PTC15),
223 IMX_PINCTRL_PIN(VF610_PAD_PTC16),
224 IMX_PINCTRL_PIN(VF610_PAD_PTC17),
225 IMX_PINCTRL_PIN(VF610_PAD_PTD31),
226 IMX_PINCTRL_PIN(VF610_PAD_PTD30),
227 IMX_PINCTRL_PIN(VF610_PAD_PTD29),
228 IMX_PINCTRL_PIN(VF610_PAD_PTD28),
229 IMX_PINCTRL_PIN(VF610_PAD_PTD27),
230 IMX_PINCTRL_PIN(VF610_PAD_PTD26),
231 IMX_PINCTRL_PIN(VF610_PAD_PTD25),
232 IMX_PINCTRL_PIN(VF610_PAD_PTD24),
233 IMX_PINCTRL_PIN(VF610_PAD_PTD23),
234 IMX_PINCTRL_PIN(VF610_PAD_PTD22),
235 IMX_PINCTRL_PIN(VF610_PAD_PTD21),
236 IMX_PINCTRL_PIN(VF610_PAD_PTD20),
237 IMX_PINCTRL_PIN(VF610_PAD_PTD19),
238 IMX_PINCTRL_PIN(VF610_PAD_PTD18),
239 IMX_PINCTRL_PIN(VF610_PAD_PTD17),
240 IMX_PINCTRL_PIN(VF610_PAD_PTD16),
241 IMX_PINCTRL_PIN(VF610_PAD_PTD0),
242 IMX_PINCTRL_PIN(VF610_PAD_PTD1),
243 IMX_PINCTRL_PIN(VF610_PAD_PTD2),
244 IMX_PINCTRL_PIN(VF610_PAD_PTD3),
245 IMX_PINCTRL_PIN(VF610_PAD_PTD4),
246 IMX_PINCTRL_PIN(VF610_PAD_PTD5),
247 IMX_PINCTRL_PIN(VF610_PAD_PTD6),
248 IMX_PINCTRL_PIN(VF610_PAD_PTD7),
249 IMX_PINCTRL_PIN(VF610_PAD_PTD8),
250 IMX_PINCTRL_PIN(VF610_PAD_PTD9),
251 IMX_PINCTRL_PIN(VF610_PAD_PTD10),
252 IMX_PINCTRL_PIN(VF610_PAD_PTD11),
253 IMX_PINCTRL_PIN(VF610_PAD_PTD12),
254 IMX_PINCTRL_PIN(VF610_PAD_PTD13),
255 IMX_PINCTRL_PIN(VF610_PAD_PTB23),
256 IMX_PINCTRL_PIN(VF610_PAD_PTB24),
257 IMX_PINCTRL_PIN(VF610_PAD_PTB25),
258 IMX_PINCTRL_PIN(VF610_PAD_PTB26),
259 IMX_PINCTRL_PIN(VF610_PAD_PTB27),
260 IMX_PINCTRL_PIN(VF610_PAD_PTB28),
261 IMX_PINCTRL_PIN(VF610_PAD_PTC26),
262 IMX_PINCTRL_PIN(VF610_PAD_PTC27),
263 IMX_PINCTRL_PIN(VF610_PAD_PTC28),
264 IMX_PINCTRL_PIN(VF610_PAD_PTC29),
265 IMX_PINCTRL_PIN(VF610_PAD_PTC30),
266 IMX_PINCTRL_PIN(VF610_PAD_PTC31),
267 IMX_PINCTRL_PIN(VF610_PAD_PTE0),
268 IMX_PINCTRL_PIN(VF610_PAD_PTE1),
269 IMX_PINCTRL_PIN(VF610_PAD_PTE2),
270 IMX_PINCTRL_PIN(VF610_PAD_PTE3),
271 IMX_PINCTRL_PIN(VF610_PAD_PTE4),
272 IMX_PINCTRL_PIN(VF610_PAD_PTE5),
273 IMX_PINCTRL_PIN(VF610_PAD_PTE6),
274 IMX_PINCTRL_PIN(VF610_PAD_PTE7),
275 IMX_PINCTRL_PIN(VF610_PAD_PTE8),
276 IMX_PINCTRL_PIN(VF610_PAD_PTE9),
277 IMX_PINCTRL_PIN(VF610_PAD_PTE10),
278 IMX_PINCTRL_PIN(VF610_PAD_PTE11),
279 IMX_PINCTRL_PIN(VF610_PAD_PTE12),
280 IMX_PINCTRL_PIN(VF610_PAD_PTE13),
281 IMX_PINCTRL_PIN(VF610_PAD_PTE14),
282 IMX_PINCTRL_PIN(VF610_PAD_PTE15),
283 IMX_PINCTRL_PIN(VF610_PAD_PTE16),
284 IMX_PINCTRL_PIN(VF610_PAD_PTE17),
285 IMX_PINCTRL_PIN(VF610_PAD_PTE18),
286 IMX_PINCTRL_PIN(VF610_PAD_PTE19),
287 IMX_PINCTRL_PIN(VF610_PAD_PTE20),
288 IMX_PINCTRL_PIN(VF610_PAD_PTE21),
289 IMX_PINCTRL_PIN(VF610_PAD_PTE22),
290 IMX_PINCTRL_PIN(VF610_PAD_PTE23),
291 IMX_PINCTRL_PIN(VF610_PAD_PTE24),
292 IMX_PINCTRL_PIN(VF610_PAD_PTE25),
293 IMX_PINCTRL_PIN(VF610_PAD_PTE26),
294 IMX_PINCTRL_PIN(VF610_PAD_PTE27),
295 IMX_PINCTRL_PIN(VF610_PAD_PTE28),
296 IMX_PINCTRL_PIN(VF610_PAD_PTA7),
297};
298
299static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
300 .pins = vf610_pinctrl_pads,
301 .npins = ARRAY_SIZE(vf610_pinctrl_pads),
302 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
303};
304
305static struct of_device_id vf610_pinctrl_of_match[] = {
306 { .compatible = "fsl,vf610-iomuxc", },
307 { /* sentinel */ }
308};
309
310static int vf610_pinctrl_probe(struct platform_device *pdev)
311{
312 return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
313}
314
315static struct platform_driver vf610_pinctrl_driver = {
316 .driver = {
317 .name = "vf610-pinctrl",
318 .owner = THIS_MODULE,
319 .of_match_table = of_match_ptr(vf610_pinctrl_of_match),
320 },
321 .probe = vf610_pinctrl_probe,
322 .remove = imx_pinctrl_remove,
323};
324
325static int __init vf610_pinctrl_init(void)
326{
327 return platform_driver_register(&vf610_pinctrl_driver);
328}
329arch_initcall(vf610_pinctrl_init);
330
331static void __exit vf610_pinctrl_exit(void)
332{
333 platform_driver_unregister(&vf610_pinctrl_driver);
334}
335module_exit(vf610_pinctrl_exit);
336
337MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
338MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 3b2fd43ff294..f3fc66b24370 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -18,6 +18,8 @@
18#include <linux/ioport.h> 18#include <linux/ioport.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
21#include <linux/pinctrl/machine.h> 23#include <linux/pinctrl/machine.h>
22#include <linux/platform_device.h> 24#include <linux/platform_device.h>
23#include <linux/slab.h> 25#include <linux/slab.h>
@@ -348,14 +350,72 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
348 return 0; 350 return 0;
349} 351}
350 352
353#ifdef CONFIG_OF
354static const struct of_device_id sh_pfc_of_table[] = {
355#ifdef CONFIG_PINCTRL_PFC_R8A73A4
356 {
357 .compatible = "renesas,pfc-r8a73a4",
358 .data = &r8a73a4_pinmux_info,
359 },
360#endif
361#ifdef CONFIG_PINCTRL_PFC_R8A7740
362 {
363 .compatible = "renesas,pfc-r8a7740",
364 .data = &r8a7740_pinmux_info,
365 },
366#endif
367#ifdef CONFIG_PINCTRL_PFC_R8A7778
368 {
369 .compatible = "renesas,pfc-r8a7778",
370 .data = &r8a7778_pinmux_info,
371 },
372#endif
373#ifdef CONFIG_PINCTRL_PFC_R8A7779
374 {
375 .compatible = "renesas,pfc-r8a7779",
376 .data = &r8a7779_pinmux_info,
377 },
378#endif
379#ifdef CONFIG_PINCTRL_PFC_R8A7790
380 {
381 .compatible = "renesas,pfc-r8a7790",
382 .data = &r8a7790_pinmux_info,
383 },
384#endif
385#ifdef CONFIG_PINCTRL_PFC_SH7372
386 {
387 .compatible = "renesas,pfc-sh7372",
388 .data = &sh7372_pinmux_info,
389 },
390#endif
391#ifdef CONFIG_PINCTRL_PFC_SH73A0
392 {
393 .compatible = "renesas,pfc-sh73a0",
394 .data = &sh73a0_pinmux_info,
395 },
396#endif
397 { },
398};
399MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
400#endif
401
351static int sh_pfc_probe(struct platform_device *pdev) 402static int sh_pfc_probe(struct platform_device *pdev)
352{ 403{
404 const struct platform_device_id *platid = platform_get_device_id(pdev);
405#ifdef CONFIG_OF
406 struct device_node *np = pdev->dev.of_node;
407#endif
353 const struct sh_pfc_soc_info *info; 408 const struct sh_pfc_soc_info *info;
354 struct sh_pfc *pfc; 409 struct sh_pfc *pfc;
355 int ret; 410 int ret;
356 411
357 info = pdev->id_entry->driver_data 412#ifdef CONFIG_OF
358 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; 413 if (np)
414 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
415 else
416#endif
417 info = platid ? (const void *)platid->driver_data : NULL;
418
359 if (info == NULL) 419 if (info == NULL)
360 return -ENODEV; 420 return -ENODEV;
361 421
@@ -501,6 +561,7 @@ static struct platform_driver sh_pfc_driver = {
501 .driver = { 561 .driver = {
502 .name = DRV_NAME, 562 .name = DRV_NAME,
503 .owner = THIS_MODULE, 563 .owner = THIS_MODULE,
564 .of_match_table = of_match_ptr(sh_pfc_of_table),
504 }, 565 },
505}; 566};
506 567
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 3492ec9a33b7..bc8b028bb5d2 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -14,7 +14,9 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/of.h>
17#include <linux/pinctrl/consumer.h> 18#include <linux/pinctrl/consumer.h>
19#include <linux/pinctrl/machine.h>
18#include <linux/pinctrl/pinconf.h> 20#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinconf-generic.h> 21#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinctrl.h>
@@ -72,11 +74,214 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
72 seq_printf(s, "%s", DRV_NAME); 74 seq_printf(s, "%s", DRV_NAME);
73} 75}
74 76
77#ifdef CONFIG_OF
78static int sh_pfc_map_add_config(struct pinctrl_map *map,
79 const char *group_or_pin,
80 enum pinctrl_map_type type,
81 unsigned long *configs,
82 unsigned int num_configs)
83{
84 unsigned long *cfgs;
85
86 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
87 GFP_KERNEL);
88 if (cfgs == NULL)
89 return -ENOMEM;
90
91 map->type = type;
92 map->data.configs.group_or_pin = group_or_pin;
93 map->data.configs.configs = cfgs;
94 map->data.configs.num_configs = num_configs;
95
96 return 0;
97}
98
99static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
100 struct pinctrl_map **map,
101 unsigned int *num_maps, unsigned int *index)
102{
103 struct pinctrl_map *maps = *map;
104 unsigned int nmaps = *num_maps;
105 unsigned int idx = *index;
106 unsigned int num_configs;
107 const char *function = NULL;
108 unsigned long *configs;
109 struct property *prop;
110 unsigned int num_groups;
111 unsigned int num_pins;
112 const char *group;
113 const char *pin;
114 int ret;
115
116 /* Parse the function and configuration properties. At least a function
117 * or one configuration must be specified.
118 */
119 ret = of_property_read_string(np, "renesas,function", &function);
120 if (ret < 0 && ret != -EINVAL) {
121 dev_err(dev, "Invalid function in DT\n");
122 return ret;
123 }
124
125 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
126 if (ret < 0)
127 return ret;
128
129 if (!function && num_configs == 0) {
130 dev_err(dev,
131 "DT node must contain at least a function or config\n");
132 goto done;
133 }
134
135 /* Count the number of pins and groups and reallocate mappings. */
136 ret = of_property_count_strings(np, "renesas,pins");
137 if (ret == -EINVAL) {
138 num_pins = 0;
139 } else if (ret < 0) {
140 dev_err(dev, "Invalid pins list in DT\n");
141 goto done;
142 } else {
143 num_pins = ret;
144 }
145
146 ret = of_property_count_strings(np, "renesas,groups");
147 if (ret == -EINVAL) {
148 num_groups = 0;
149 } else if (ret < 0) {
150 dev_err(dev, "Invalid pin groups list in DT\n");
151 goto done;
152 } else {
153 num_groups = ret;
154 }
155
156 if (!num_pins && !num_groups) {
157 dev_err(dev, "No pin or group provided in DT node\n");
158 ret = -ENODEV;
159 goto done;
160 }
161
162 if (function)
163 nmaps += num_groups;
164 if (configs)
165 nmaps += num_pins + num_groups;
166
167 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
168 if (maps == NULL) {
169 ret = -ENOMEM;
170 goto done;
171 }
172
173 *map = maps;
174 *num_maps = nmaps;
175
176 /* Iterate over pins and groups and create the mappings. */
177 of_property_for_each_string(np, "renesas,groups", prop, group) {
178 if (function) {
179 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
180 maps[idx].data.mux.group = group;
181 maps[idx].data.mux.function = function;
182 idx++;
183 }
184
185 if (configs) {
186 ret = sh_pfc_map_add_config(&maps[idx], group,
187 PIN_MAP_TYPE_CONFIGS_GROUP,
188 configs, num_configs);
189 if (ret < 0)
190 goto done;
191
192 idx++;
193 }
194 }
195
196 if (!configs) {
197 ret = 0;
198 goto done;
199 }
200
201 of_property_for_each_string(np, "renesas,pins", prop, pin) {
202 ret = sh_pfc_map_add_config(&maps[idx], pin,
203 PIN_MAP_TYPE_CONFIGS_PIN,
204 configs, num_configs);
205 if (ret < 0)
206 goto done;
207
208 idx++;
209 }
210
211done:
212 *index = idx;
213 kfree(configs);
214 return ret;
215}
216
217static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
218 struct pinctrl_map *map, unsigned num_maps)
219{
220 unsigned int i;
221
222 if (map == NULL)
223 return;
224
225 for (i = 0; i < num_maps; ++i) {
226 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
227 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
228 kfree(map[i].data.configs.configs);
229 }
230
231 kfree(map);
232}
233
234static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
235 struct device_node *np,
236 struct pinctrl_map **map, unsigned *num_maps)
237{
238 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
239 struct device *dev = pmx->pfc->dev;
240 struct device_node *child;
241 unsigned int index;
242 int ret;
243
244 *map = NULL;
245 *num_maps = 0;
246 index = 0;
247
248 for_each_child_of_node(np, child) {
249 ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
250 &index);
251 if (ret < 0)
252 goto done;
253 }
254
255 /* If no mapping has been found in child nodes try the config node. */
256 if (*num_maps == 0) {
257 ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
258 if (ret < 0)
259 goto done;
260 }
261
262 if (*num_maps)
263 return 0;
264
265 dev_err(dev, "no mapping found in node %s\n", np->full_name);
266 ret = -EINVAL;
267
268done:
269 if (ret < 0)
270 sh_pfc_dt_free_map(pctldev, *map, *num_maps);
271
272 return ret;
273}
274#endif /* CONFIG_OF */
275
75static const struct pinctrl_ops sh_pfc_pinctrl_ops = { 276static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
76 .get_groups_count = sh_pfc_get_groups_count, 277 .get_groups_count = sh_pfc_get_groups_count,
77 .get_group_name = sh_pfc_get_group_name, 278 .get_group_name = sh_pfc_get_group_name,
78 .get_group_pins = sh_pfc_get_group_pins, 279 .get_group_pins = sh_pfc_get_group_pins,
79 .pin_dbg_show = sh_pfc_pin_dbg_show, 280 .pin_dbg_show = sh_pfc_pin_dbg_show,
281#ifdef CONFIG_OF
282 .dt_node_to_map = sh_pfc_dt_node_to_map,
283 .dt_free_map = sh_pfc_dt_free_map,
284#endif
80}; 285};
81 286
82static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) 287static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile
new file mode 100644
index 000000000000..3ffc475ce40c
--- /dev/null
+++ b/drivers/pinctrl/sirf/Makefile
@@ -0,0 +1,5 @@
1# CSR SiRFsoc pinmux support
2
3obj-y += pinctrl-sirf.o
4obj-y += pinctrl-prima2.o
5obj-y += pinctrl-atlas6.o
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
new file mode 100644
index 000000000000..1fa39a444171
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -0,0 +1,947 @@
1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVI
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/bitops.h>
11
12#include "pinctrl-sirf.h"
13
14/*
15 * pad list for the pinmux subsystem
16 * refer to atlasVI_io_table_v0.93.xls
17 */
18static const struct pinctrl_pin_desc sirfsoc_pads[] = {
19 PINCTRL_PIN(0, "gpio0-0"),
20 PINCTRL_PIN(1, "gpio0-1"),
21 PINCTRL_PIN(2, "gpio0-2"),
22 PINCTRL_PIN(3, "gpio0-3"),
23 PINCTRL_PIN(4, "pwm0"),
24 PINCTRL_PIN(5, "pwm1"),
25 PINCTRL_PIN(6, "pwm2"),
26 PINCTRL_PIN(7, "pwm3"),
27 PINCTRL_PIN(8, "warm_rst_b"),
28 PINCTRL_PIN(9, "odo_0"),
29 PINCTRL_PIN(10, "odo_1"),
30 PINCTRL_PIN(11, "dr_dir"),
31 PINCTRL_PIN(12, "rts_0"),
32 PINCTRL_PIN(13, "scl_1"),
33 PINCTRL_PIN(14, "ntrst"),
34 PINCTRL_PIN(15, "sda_1"),
35 PINCTRL_PIN(16, "x_ldd[16]"),
36 PINCTRL_PIN(17, "x_ldd[17]"),
37 PINCTRL_PIN(18, "x_ldd[18]"),
38 PINCTRL_PIN(19, "x_ldd[19]"),
39 PINCTRL_PIN(20, "x_ldd[20]"),
40 PINCTRL_PIN(21, "x_ldd[21]"),
41 PINCTRL_PIN(22, "x_ldd[22]"),
42 PINCTRL_PIN(23, "x_ldd[23]"),
43 PINCTRL_PIN(24, "gps_sgn"),
44 PINCTRL_PIN(25, "gps_mag"),
45 PINCTRL_PIN(26, "gps_clk"),
46 PINCTRL_PIN(27, "sd_cd_b_2"),
47 PINCTRL_PIN(28, "sd_vcc_on_2"),
48 PINCTRL_PIN(29, "sd_wp_b_2"),
49 PINCTRL_PIN(30, "sd_clk_3"),
50 PINCTRL_PIN(31, "sd_cmd_3"),
51
52 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56 PINCTRL_PIN(36, "usb_clk"),
57 PINCTRL_PIN(37, "usb_dir"),
58 PINCTRL_PIN(38, "usb_nxt"),
59 PINCTRL_PIN(39, "usb_stp"),
60 PINCTRL_PIN(40, "usb_dat[7]"),
61 PINCTRL_PIN(41, "usb_dat[6]"),
62 PINCTRL_PIN(42, "x_cko_1"),
63 PINCTRL_PIN(43, "spi_clk_1"),
64 PINCTRL_PIN(44, "spi_dout_1"),
65 PINCTRL_PIN(45, "spi_din_1"),
66 PINCTRL_PIN(46, "spi_en_1"),
67 PINCTRL_PIN(47, "x_txd_1"),
68 PINCTRL_PIN(48, "x_txd_2"),
69 PINCTRL_PIN(49, "x_rxd_1"),
70 PINCTRL_PIN(50, "x_rxd_2"),
71 PINCTRL_PIN(51, "x_usclk_0"),
72 PINCTRL_PIN(52, "x_utxd_0"),
73 PINCTRL_PIN(53, "x_urxd_0"),
74 PINCTRL_PIN(54, "x_utfs_0"),
75 PINCTRL_PIN(55, "x_urfs_0"),
76 PINCTRL_PIN(56, "usb_dat5"),
77 PINCTRL_PIN(57, "usb_dat4"),
78 PINCTRL_PIN(58, "usb_dat3"),
79 PINCTRL_PIN(59, "usb_dat2"),
80 PINCTRL_PIN(60, "usb_dat1"),
81 PINCTRL_PIN(61, "usb_dat0"),
82 PINCTRL_PIN(62, "x_ldd[14]"),
83 PINCTRL_PIN(63, "x_ldd[15]"),
84
85 PINCTRL_PIN(64, "x_gps_gpio"),
86 PINCTRL_PIN(65, "x_ldd[13]"),
87 PINCTRL_PIN(66, "x_df_we_b"),
88 PINCTRL_PIN(67, "x_df_re_b"),
89 PINCTRL_PIN(68, "x_txd_0"),
90 PINCTRL_PIN(69, "x_rxd_0"),
91 PINCTRL_PIN(70, "x_l_lck"),
92 PINCTRL_PIN(71, "x_l_fck"),
93 PINCTRL_PIN(72, "x_l_de"),
94 PINCTRL_PIN(73, "x_ldd[0]"),
95 PINCTRL_PIN(74, "x_ldd[1]"),
96 PINCTRL_PIN(75, "x_ldd[2]"),
97 PINCTRL_PIN(76, "x_ldd[3]"),
98 PINCTRL_PIN(77, "x_ldd[4]"),
99 PINCTRL_PIN(78, "x_cko_0"),
100 PINCTRL_PIN(79, "x_ldd[5]"),
101 PINCTRL_PIN(80, "x_ldd[6]"),
102 PINCTRL_PIN(81, "x_ldd[7]"),
103 PINCTRL_PIN(82, "x_ldd[8]"),
104 PINCTRL_PIN(83, "x_ldd[9]"),
105 PINCTRL_PIN(84, "x_ldd[10]"),
106 PINCTRL_PIN(85, "x_ldd[11]"),
107 PINCTRL_PIN(86, "x_ldd[12]"),
108 PINCTRL_PIN(87, "x_vip_vsync"),
109 PINCTRL_PIN(88, "x_vip_hsync"),
110 PINCTRL_PIN(89, "x_vip_pxclk"),
111 PINCTRL_PIN(90, "x_sda_0"),
112 PINCTRL_PIN(91, "x_scl_0"),
113 PINCTRL_PIN(92, "x_df_ry_by"),
114 PINCTRL_PIN(93, "x_df_cs_b[1]"),
115 PINCTRL_PIN(94, "x_df_cs_b[0]"),
116 PINCTRL_PIN(95, "x_l_pclk"),
117
118 PINCTRL_PIN(96, "x_df_dqs"),
119 PINCTRL_PIN(97, "x_df_wp_b"),
120 PINCTRL_PIN(98, "ac97_sync"),
121 PINCTRL_PIN(99, "ac97_bit_clk "),
122 PINCTRL_PIN(100, "ac97_dout"),
123 PINCTRL_PIN(101, "ac97_din"),
124 PINCTRL_PIN(102, "x_rtc_io"),
125};
126
127static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
128 {
129 .group = 1,
130 .mask = BIT(30) | BIT(31),
131 }, {
132 .group = 2,
133 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
134 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
135 BIT(20) | BIT(21) | BIT(22) | BIT(31),
136 },
137};
138
139static const struct sirfsoc_padmux lcd_16bits_padmux = {
140 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
141 .muxmask = lcd_16bits_sirfsoc_muxmask,
142 .funcmask = BIT(4),
143 .funcval = 0,
144};
145
146static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
147 84, 85, 86, 95 };
148
149static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
150 {
151 .group = 2,
152 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
153 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
154 BIT(20) | BIT(21) | BIT(22) | BIT(31),
155 }, {
156 .group = 1,
157 .mask = BIT(30) | BIT(31),
158 }, {
159 .group = 0,
160 .mask = BIT(16) | BIT(17),
161 },
162};
163
164static const struct sirfsoc_padmux lcd_18bits_padmux = {
165 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
166 .muxmask = lcd_18bits_muxmask,
167 .funcmask = BIT(4) | BIT(15),
168 .funcval = 0,
169};
170
171static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
172 84, 85, 86, 95 };
173
174static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
175 {
176 .group = 2,
177 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
178 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
179 BIT(20) | BIT(21) | BIT(22) | BIT(31),
180 }, {
181 .group = 1,
182 .mask = BIT(30) | BIT(31),
183 }, {
184 .group = 0,
185 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
186 },
187};
188
189static const struct sirfsoc_padmux lcd_24bits_padmux = {
190 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
191 .muxmask = lcd_24bits_muxmask,
192 .funcmask = BIT(4) | BIT(15),
193 .funcval = 0,
194};
195
196static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
197 80, 81, 82, 83, 84, 85, 86, 95};
198
199static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
200 {
201 .group = 2,
202 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
203 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
204 BIT(20) | BIT(21) | BIT(22) | BIT(31),
205 }, {
206 .group = 1,
207 .mask = BIT(30) | BIT(31),
208 }, {
209 .group = 0,
210 .mask = BIT(8),
211 },
212};
213
214static const struct sirfsoc_padmux lcdrom_padmux = {
215 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
216 .muxmask = lcdrom_muxmask,
217 .funcmask = BIT(4),
218 .funcval = BIT(4),
219};
220
221static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
222 84, 85, 86, 95};
223
224static const struct sirfsoc_muxmask uart0_muxmask[] = {
225 {
226 .group = 0,
227 .mask = BIT(12),
228 }, {
229 .group = 1,
230 .mask = BIT(23),
231 }, {
232 .group = 2,
233 .mask = BIT(4) | BIT(5),
234 },
235};
236
237static const struct sirfsoc_padmux uart0_padmux = {
238 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
239 .muxmask = uart0_muxmask,
240 .funcmask = BIT(9),
241 .funcval = BIT(9),
242};
243
244static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
245
246static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
247 {
248 .group = 2,
249 .mask = BIT(4) | BIT(5),
250 },
251};
252
253static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
254 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
255 .muxmask = uart0_nostreamctrl_muxmask,
256};
257
258static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
259
260static const struct sirfsoc_muxmask uart1_muxmask[] = {
261 {
262 .group = 1,
263 .mask = BIT(15) | BIT(17),
264 },
265};
266
267static const struct sirfsoc_padmux uart1_padmux = {
268 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
269 .muxmask = uart1_muxmask,
270};
271
272static const unsigned uart1_pins[] = { 47, 49 };
273
274static const struct sirfsoc_muxmask uart2_muxmask[] = {
275 {
276 .group = 0,
277 .mask = BIT(10) | BIT(14),
278 }, {
279 .group = 1,
280 .mask = BIT(16) | BIT(18),
281 },
282};
283
284static const struct sirfsoc_padmux uart2_padmux = {
285 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
286 .muxmask = uart2_muxmask,
287 .funcmask = BIT(10),
288 .funcval = BIT(10),
289};
290
291static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
292
293static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
294 {
295 .group = 1,
296 .mask = BIT(16) | BIT(18),
297 },
298};
299
300static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
301 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
302 .muxmask = uart2_nostreamctrl_muxmask,
303};
304
305static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
306
307static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
308 {
309 .group = 0,
310 .mask = BIT(30) | BIT(31),
311 }, {
312 .group = 1,
313 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
314 },
315};
316
317static const struct sirfsoc_padmux sdmmc3_padmux = {
318 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
319 .muxmask = sdmmc3_muxmask,
320 .funcmask = BIT(7),
321 .funcval = 0,
322};
323
324static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
325
326static const struct sirfsoc_muxmask spi0_muxmask[] = {
327 {
328 .group = 0,
329 .mask = BIT(30),
330 }, {
331 .group = 1,
332 .mask = BIT(0) | BIT(2) | BIT(3),
333 },
334};
335
336static const struct sirfsoc_padmux spi0_padmux = {
337 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
338 .muxmask = spi0_muxmask,
339 .funcmask = BIT(7),
340 .funcval = BIT(7),
341};
342
343static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
344
345static const struct sirfsoc_muxmask cko1_muxmask[] = {
346 {
347 .group = 1,
348 .mask = BIT(10),
349 },
350};
351
352static const struct sirfsoc_padmux cko1_padmux = {
353 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
354 .muxmask = cko1_muxmask,
355 .funcmask = BIT(3),
356 .funcval = 0,
357};
358
359static const unsigned cko1_pins[] = { 42 };
360
361static const struct sirfsoc_muxmask i2s_muxmask[] = {
362 {
363 .group = 1,
364 .mask = BIT(10),
365 }, {
366 .group = 3,
367 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
368 },
369};
370
371static const struct sirfsoc_padmux i2s_padmux = {
372 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
373 .muxmask = i2s_muxmask,
374 .funcmask = BIT(3),
375 .funcval = BIT(3),
376};
377
378static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
379
380static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
381 {
382 .group = 1,
383 .mask = BIT(10),
384 }, {
385 .group = 3,
386 .mask = BIT(2) | BIT(3) | BIT(4),
387 },
388};
389
390static const struct sirfsoc_padmux i2s_no_din_padmux = {
391 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
392 .muxmask = i2s_no_din_muxmask,
393 .funcmask = BIT(3),
394 .funcval = BIT(3),
395};
396
397static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
398
399static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
400 {
401 .group = 1,
402 .mask = BIT(10) | BIT(20) | BIT(23),
403 }, {
404 .group = 3,
405 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
406 },
407};
408
409static const struct sirfsoc_padmux i2s_6chn_padmux = {
410 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
411 .muxmask = i2s_6chn_muxmask,
412 .funcmask = BIT(1) | BIT(3) | BIT(9),
413 .funcval = BIT(1) | BIT(3) | BIT(9),
414};
415
416static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
417
418static const struct sirfsoc_muxmask ac97_muxmask[] = {
419 {
420 .group = 3,
421 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
422 },
423};
424
425static const struct sirfsoc_padmux ac97_padmux = {
426 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
427 .muxmask = ac97_muxmask,
428};
429
430static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
431
432static const struct sirfsoc_muxmask spi1_muxmask[] = {
433 {
434 .group = 1,
435 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
436 },
437};
438
439static const struct sirfsoc_padmux spi1_padmux = {
440 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
441 .muxmask = spi1_muxmask,
442 .funcmask = BIT(16),
443 .funcval = 0,
444};
445
446static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
447
448static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
449 {
450 .group = 2,
451 .mask = BIT(2) | BIT(3),
452 },
453};
454
455static const struct sirfsoc_padmux sdmmc1_padmux = {
456 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
457 .muxmask = sdmmc1_muxmask,
458 .funcmask = BIT(5),
459 .funcval = BIT(5),
460};
461
462static const unsigned sdmmc1_pins[] = { 66, 67 };
463
464static const struct sirfsoc_muxmask gps_muxmask[] = {
465 {
466 .group = 0,
467 .mask = BIT(24) | BIT(25) | BIT(26),
468 },
469};
470
471static const struct sirfsoc_padmux gps_padmux = {
472 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
473 .muxmask = gps_muxmask,
474 .funcmask = BIT(13),
475 .funcval = 0,
476};
477
478static const unsigned gps_pins[] = { 24, 25, 26 };
479
480static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
481 {
482 .group = 0,
483 .mask = BIT(24) | BIT(25) | BIT(26),
484 },
485};
486
487static const struct sirfsoc_padmux sdmmc5_padmux = {
488 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
489 .muxmask = sdmmc5_muxmask,
490 .funcmask = BIT(13),
491 .funcval = BIT(13),
492};
493
494static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
495
496static const struct sirfsoc_muxmask usp0_muxmask[] = {
497 {
498 .group = 1,
499 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
500 },
501};
502
503static const struct sirfsoc_padmux usp0_padmux = {
504 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
505 .muxmask = usp0_muxmask,
506 .funcmask = BIT(1) | BIT(2) | BIT(9),
507 .funcval = 0,
508};
509
510static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
511
512static const struct sirfsoc_muxmask usp1_muxmask[] = {
513 {
514 .group = 0,
515 .mask = BIT(15),
516 }, {
517 .group = 1,
518 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
519 },
520};
521
522static const struct sirfsoc_padmux usp1_padmux = {
523 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
524 .muxmask = usp1_muxmask,
525 .funcmask = BIT(16),
526 .funcval = BIT(16),
527};
528
529static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
530
531static const struct sirfsoc_muxmask nand_muxmask[] = {
532 {
533 .group = 2,
534 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
535 }, {
536 .group = 3,
537 .mask = BIT(0) | BIT(1),
538 },
539};
540
541static const struct sirfsoc_padmux nand_padmux = {
542 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
543 .muxmask = nand_muxmask,
544 .funcmask = BIT(5) | BIT(19),
545 .funcval = 0,
546};
547
548static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
549
550static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
551 {
552 .group = 3,
553 .mask = BIT(1),
554 },
555};
556
557static const struct sirfsoc_padmux sdmmc0_padmux = {
558 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
559 .muxmask = sdmmc0_muxmask,
560 .funcmask = BIT(5) | BIT(19),
561 .funcval = BIT(19),
562};
563
564static const unsigned sdmmc0_pins[] = { 97 };
565
566static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
567 {
568 .group = 0,
569 .mask = BIT(27) | BIT(28) | BIT(29),
570 },
571};
572
573static const struct sirfsoc_padmux sdmmc2_padmux = {
574 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
575 .muxmask = sdmmc2_muxmask,
576 .funcmask = BIT(11),
577 .funcval = 0,
578};
579
580static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
581
582static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
583 {
584 .group = 0,
585 .mask = BIT(27) | BIT(28),
586 },
587};
588
589static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
590 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
591 .muxmask = sdmmc2_nowp_muxmask,
592 .funcmask = BIT(11),
593 .funcval = 0,
594};
595
596static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
597
598static const struct sirfsoc_muxmask cko0_muxmask[] = {
599 {
600 .group = 2,
601 .mask = BIT(14),
602 },
603};
604
605static const struct sirfsoc_padmux cko0_padmux = {
606 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
607 .muxmask = cko0_muxmask,
608};
609
610static const unsigned cko0_pins[] = { 78 };
611
612static const struct sirfsoc_muxmask vip_muxmask[] = {
613 {
614 .group = 1,
615 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
616 | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
617 BIT(29),
618 },
619};
620
621static const struct sirfsoc_padmux vip_padmux = {
622 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
623 .muxmask = vip_muxmask,
624 .funcmask = BIT(18),
625 .funcval = BIT(18),
626};
627
628static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
629
630static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
631 {
632 .group = 0,
633 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
634 | BIT(21) | BIT(22) | BIT(23),
635 }, {
636 .group = 2,
637 .mask = BIT(23) | BIT(24) | BIT(25),
638 },
639};
640
641static const struct sirfsoc_padmux vip_noupli_padmux = {
642 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
643 .muxmask = vip_noupli_muxmask,
644 .funcmask = BIT(15),
645 .funcval = BIT(15),
646};
647
648static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
649
650static const struct sirfsoc_muxmask i2c0_muxmask[] = {
651 {
652 .group = 2,
653 .mask = BIT(26) | BIT(27),
654 },
655};
656
657static const struct sirfsoc_padmux i2c0_padmux = {
658 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
659 .muxmask = i2c0_muxmask,
660};
661
662static const unsigned i2c0_pins[] = { 90, 91 };
663
664static const struct sirfsoc_muxmask i2c1_muxmask[] = {
665 {
666 .group = 0,
667 .mask = BIT(13) | BIT(15),
668 },
669};
670
671static const struct sirfsoc_padmux i2c1_padmux = {
672 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
673 .muxmask = i2c1_muxmask,
674 .funcmask = BIT(16),
675 .funcval = 0,
676};
677
678static const unsigned i2c1_pins[] = { 13, 15 };
679
680static const struct sirfsoc_muxmask pwm0_muxmask[] = {
681 {
682 .group = 0,
683 .mask = BIT(4),
684 },
685};
686
687static const struct sirfsoc_padmux pwm0_padmux = {
688 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
689 .muxmask = pwm0_muxmask,
690 .funcmask = BIT(12),
691 .funcval = 0,
692};
693
694static const unsigned pwm0_pins[] = { 4 };
695
696static const struct sirfsoc_muxmask pwm1_muxmask[] = {
697 {
698 .group = 0,
699 .mask = BIT(5),
700 },
701};
702
703static const struct sirfsoc_padmux pwm1_padmux = {
704 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
705 .muxmask = pwm1_muxmask,
706};
707
708static const unsigned pwm1_pins[] = { 5 };
709
710static const struct sirfsoc_muxmask pwm2_muxmask[] = {
711 {
712 .group = 0,
713 .mask = BIT(6),
714 },
715};
716
717static const struct sirfsoc_padmux pwm2_padmux = {
718 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
719 .muxmask = pwm2_muxmask,
720};
721
722static const unsigned pwm2_pins[] = { 6 };
723
724static const struct sirfsoc_muxmask pwm3_muxmask[] = {
725 {
726 .group = 0,
727 .mask = BIT(7),
728 },
729};
730
731static const struct sirfsoc_padmux pwm3_padmux = {
732 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
733 .muxmask = pwm3_muxmask,
734};
735
736static const unsigned pwm3_pins[] = { 7 };
737
738static const struct sirfsoc_muxmask pwm4_muxmask[] = {
739 {
740 .group = 2,
741 .mask = BIT(14),
742 },
743};
744
745static const struct sirfsoc_padmux pwm4_padmux = {
746 .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
747 .muxmask = pwm4_muxmask,
748};
749
750static const unsigned pwm4_pins[] = { 78 };
751
752static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
753 {
754 .group = 0,
755 .mask = BIT(8),
756 },
757};
758
759static const struct sirfsoc_padmux warm_rst_padmux = {
760 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
761 .muxmask = warm_rst_muxmask,
762 .funcmask = BIT(4),
763 .funcval = 0,
764};
765
766static const unsigned warm_rst_pins[] = { 8 };
767
768static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
769 {
770 .group = 1,
771 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
772 | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
773 BIT(27) | BIT(28) | BIT(29),
774 },
775};
776static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
777 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
778 .muxmask = usb0_upli_drvbus_muxmask,
779 .funcmask = BIT(18),
780 .funcval = 0,
781};
782
783static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
784
785static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
786 {
787 .group = 0,
788 .mask = BIT(28),
789 },
790};
791
792static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
793 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
794 .muxmask = usb1_utmi_drvbus_muxmask,
795 .funcmask = BIT(11),
796 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
797};
798
799static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
800
801static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
802 {
803 .group = 0,
804 .mask = BIT(9) | BIT(10) | BIT(11),
805 },
806};
807
808static const struct sirfsoc_padmux pulse_count_padmux = {
809 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
810 .muxmask = pulse_count_muxmask,
811};
812
813static const unsigned pulse_count_pins[] = { 9, 10, 11 };
814
815static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
816 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
817 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
818 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
819 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
820 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
821 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
822 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
823 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
824 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
825 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
826 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
827 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
828 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
829 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
830 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
831 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
832 SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
833 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
834 SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
835 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
836 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
837 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
838 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
839 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
840 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
841 SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
842 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
843 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
844 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
845 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
846 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
847 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
848 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
849 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
850 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
851 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
852 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
853 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
854 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
855};
856
857static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
858static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
859static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
860static const char * const lcdromgrp[] = { "lcdromgrp" };
861static const char * const uart0grp[] = { "uart0grp" };
862static const char * const uart1grp[] = { "uart1grp" };
863static const char * const uart2grp[] = { "uart2grp" };
864static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
865static const char * const usp0grp[] = { "usp0grp" };
866static const char * const usp1grp[] = { "usp1grp" };
867static const char * const i2c0grp[] = { "i2c0grp" };
868static const char * const i2c1grp[] = { "i2c1grp" };
869static const char * const pwm0grp[] = { "pwm0grp" };
870static const char * const pwm1grp[] = { "pwm1grp" };
871static const char * const pwm2grp[] = { "pwm2grp" };
872static const char * const pwm3grp[] = { "pwm3grp" };
873static const char * const pwm4grp[] = { "pwm4grp" };
874static const char * const vipgrp[] = { "vipgrp" };
875static const char * const vip_noupligrp[] = { "vip_noupligrp" };
876static const char * const warm_rstgrp[] = { "warm_rstgrp" };
877static const char * const cko0grp[] = { "cko0grp" };
878static const char * const cko1grp[] = { "cko1grp" };
879static const char * const sdmmc0grp[] = { "sdmmc0grp" };
880static const char * const sdmmc1grp[] = { "sdmmc1grp" };
881static const char * const sdmmc2grp[] = { "sdmmc2grp" };
882static const char * const sdmmc3grp[] = { "sdmmc3grp" };
883static const char * const sdmmc5grp[] = { "sdmmc5grp" };
884static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
885static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
886static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
887static const char * const pulse_countgrp[] = { "pulse_countgrp" };
888static const char * const i2sgrp[] = { "i2sgrp" };
889static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
890static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
891static const char * const ac97grp[] = { "ac97grp" };
892static const char * const nandgrp[] = { "nandgrp" };
893static const char * const spi0grp[] = { "spi0grp" };
894static const char * const spi1grp[] = { "spi1grp" };
895static const char * const gpsgrp[] = { "gpsgrp" };
896
897static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
898 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
899 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
900 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
901 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
902 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
903 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
904 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
905 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
906 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
907 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
908 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
909 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
910 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
911 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
912 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
913 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
914 SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
915 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
916 SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
917 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
918 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
919 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
920 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
921 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
922 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
923 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
924 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
925 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
926 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
927 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
928 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
929 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
930 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
931 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
932 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
933 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
934 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
935 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
936 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
937};
938
939struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
940 (struct pinctrl_pin_desc *)sirfsoc_pads,
941 ARRAY_SIZE(sirfsoc_pads),
942 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
943 ARRAY_SIZE(sirfsoc_pin_groups),
944 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
945 ARRAY_SIZE(sirfsoc_pmx_functions),
946};
947
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index bc9d1be27fb0..1f0ad1ef5a3a 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -1,70 +1,15 @@
1/* 1/*
2 * pinmux driver for CSR SiRFprimaII 2 * pinctrl pads, groups, functions for CSR SiRFprimaII
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 * 5 *
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/pinctrl/pinctrl.h> 9#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/of_platform.h>
26#include <linux/bitops.h> 10#include <linux/bitops.h>
27#include <linux/gpio.h> 11
28#include <linux/of_gpio.h> 12#include "pinctrl-sirf.h"
29
30#define DRIVER_NAME "pinmux-sirf"
31
32#define SIRFSOC_NUM_PADS 622
33#define SIRFSOC_RSC_PIN_MUX 0x4
34
35#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
36#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
37#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
38#define SIRFSOC_GPIO_DSP_EN0 (0x80)
39#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
40
41#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
42#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
43#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
44#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
45#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
46#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
47#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
48#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
49#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
50#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
51#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
52
53#define SIRFSOC_GPIO_NO_OF_BANKS 5
54#define SIRFSOC_GPIO_BANK_SIZE 32
55#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
56
57struct sirfsoc_gpio_bank {
58 struct of_mm_gpio_chip chip;
59 struct irq_domain *domain;
60 int id;
61 int parent_irq;
62 spinlock_t lock;
63 bool is_marco; /* for marco, some registers are different with prima2 */
64};
65
66static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
67static DEFINE_SPINLOCK(sgpio_lock);
68 13
69/* 14/*
70 * pad list for the pinmux subsystem 15 * pad list for the pinmux subsystem
@@ -183,46 +128,6 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
183 PINCTRL_PIN(114, "x_ldd[15]"), 128 PINCTRL_PIN(114, "x_ldd[15]"),
184}; 129};
185 130
186/**
187 * @dev: a pointer back to containing device
188 * @virtbase: the offset to the controller in virtual memory
189 */
190struct sirfsoc_pmx {
191 struct device *dev;
192 struct pinctrl_dev *pmx;
193 void __iomem *gpio_virtbase;
194 void __iomem *rsc_virtbase;
195 bool is_marco;
196};
197
198/* SIRFSOC_GPIO_PAD_EN set */
199struct sirfsoc_muxmask {
200 unsigned long group;
201 unsigned long mask;
202};
203
204struct sirfsoc_padmux {
205 unsigned long muxmask_counts;
206 const struct sirfsoc_muxmask *muxmask;
207 /* RSC_PIN_MUX set */
208 unsigned long funcmask;
209 unsigned long funcval;
210};
211
212 /**
213 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
214 * @name: the name of this specific pin group
215 * @pins: an array of discrete physical pins used in this group, taken
216 * from the driver-local pin enumeration space
217 * @num_pins: the number of pins in this group array, i.e. the number of
218 * elements in .pins so we can iterate over that array
219 */
220struct sirfsoc_pin_group {
221 const char *name;
222 const unsigned int *pins;
223 const unsigned num_pins;
224};
225
226static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 131static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
227 { 132 {
228 .group = 3, 133 .group = 3,
@@ -351,7 +256,7 @@ static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
351 .muxmask = uart0_nostreamctrl_muxmask, 256 .muxmask = uart0_nostreamctrl_muxmask,
352}; 257};
353 258
354static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; 259static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
355 260
356static const struct sirfsoc_muxmask uart1_muxmask[] = { 261static const struct sirfsoc_muxmask uart1_muxmask[] = {
357 { 262 {
@@ -853,13 +758,6 @@ static const struct sirfsoc_padmux pulse_count_padmux = {
853 758
854static const unsigned pulse_count_pins[] = { 9, 10, 11 }; 759static const unsigned pulse_count_pins[] = { 9, 10, 11 };
855 760
856#define SIRFSOC_PIN_GROUP(n, p) \
857 { \
858 .name = n, \
859 .pins = p, \
860 .num_pins = ARRAY_SIZE(p), \
861 }
862
863static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { 761static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
864 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), 762 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
865 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), 763 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
@@ -881,8 +779,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
881 SIRFSOC_PIN_GROUP("vipgrp", vip_pins), 779 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
882 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), 780 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
883 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), 781 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
884 SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), 782 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
885 SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), 783 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
886 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), 784 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
887 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), 785 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
888 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), 786 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
@@ -900,101 +798,6 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
900 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 798 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
901}; 799};
902 800
903static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
904{
905 return ARRAY_SIZE(sirfsoc_pin_groups);
906}
907
908static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
909 unsigned selector)
910{
911 return sirfsoc_pin_groups[selector].name;
912}
913
914static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
915 const unsigned **pins,
916 unsigned *num_pins)
917{
918 *pins = sirfsoc_pin_groups[selector].pins;
919 *num_pins = sirfsoc_pin_groups[selector].num_pins;
920 return 0;
921}
922
923static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
924 unsigned offset)
925{
926 seq_printf(s, " " DRIVER_NAME);
927}
928
929static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
930 struct device_node *np_config,
931 struct pinctrl_map **map, unsigned *num_maps)
932{
933 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
934 struct device_node *np;
935 struct property *prop;
936 const char *function, *group;
937 int ret, index = 0, count = 0;
938
939 /* calculate number of maps required */
940 for_each_child_of_node(np_config, np) {
941 ret = of_property_read_string(np, "sirf,function", &function);
942 if (ret < 0)
943 return ret;
944
945 ret = of_property_count_strings(np, "sirf,pins");
946 if (ret < 0)
947 return ret;
948
949 count += ret;
950 }
951
952 if (!count) {
953 dev_err(spmx->dev, "No child nodes passed via DT\n");
954 return -ENODEV;
955 }
956
957 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
958 if (!*map)
959 return -ENOMEM;
960
961 for_each_child_of_node(np_config, np) {
962 of_property_read_string(np, "sirf,function", &function);
963 of_property_for_each_string(np, "sirf,pins", prop, group) {
964 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
965 (*map)[index].data.mux.group = group;
966 (*map)[index].data.mux.function = function;
967 index++;
968 }
969 }
970
971 *num_maps = count;
972
973 return 0;
974}
975
976static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
977 struct pinctrl_map *map, unsigned num_maps)
978{
979 kfree(map);
980}
981
982static const struct pinctrl_ops sirfsoc_pctrl_ops = {
983 .get_groups_count = sirfsoc_get_groups_count,
984 .get_group_name = sirfsoc_get_group_name,
985 .get_group_pins = sirfsoc_get_group_pins,
986 .pin_dbg_show = sirfsoc_pin_dbg_show,
987 .dt_node_to_map = sirfsoc_dt_node_to_map,
988 .dt_free_map = sirfsoc_dt_free_map,
989};
990
991struct sirfsoc_pmx_func {
992 const char *name;
993 const char * const *groups;
994 const unsigned num_groups;
995 const struct sirfsoc_padmux *padmux;
996};
997
998static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; 801static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
999static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; 802static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1000static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; 803static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
@@ -1033,14 +836,6 @@ static const char * const spi0grp[] = { "spi0grp" };
1033static const char * const spi1grp[] = { "spi1grp" }; 836static const char * const spi1grp[] = { "spi1grp" };
1034static const char * const gpsgrp[] = { "gpsgrp" }; 837static const char * const gpsgrp[] = { "gpsgrp" };
1035 838
1036#define SIRFSOC_PMX_FUNCTION(n, g, m) \
1037 { \
1038 .name = n, \
1039 .groups = g, \
1040 .num_groups = ARRAY_SIZE(g), \
1041 .padmux = &m, \
1042 }
1043
1044static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { 839static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1045 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), 840 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1046 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), 841 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
@@ -1081,730 +876,12 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1081 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), 876 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1082}; 877};
1083 878
1084static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, 879struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1085 bool enable) 880 (struct pinctrl_pin_desc *)sirfsoc_pads,
1086{ 881 ARRAY_SIZE(sirfsoc_pads),
1087 int i; 882 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1088 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; 883 ARRAY_SIZE(sirfsoc_pin_groups),
1089 const struct sirfsoc_muxmask *mask = mux->muxmask; 884 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1090 885 ARRAY_SIZE(sirfsoc_pmx_functions),
1091 for (i = 0; i < mux->muxmask_counts; i++) {
1092 u32 muxval;
1093 if (!spmx->is_marco) {
1094 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1095 if (enable)
1096 muxval = muxval & ~mask[i].mask;
1097 else
1098 muxval = muxval | mask[i].mask;
1099 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1100 } else {
1101 if (enable)
1102 writel(mask[i].mask, spmx->gpio_virtbase +
1103 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
1104 else
1105 writel(mask[i].mask, spmx->gpio_virtbase +
1106 SIRFSOC_GPIO_PAD_EN(mask[i].group));
1107 }
1108 }
1109
1110 if (mux->funcmask && enable) {
1111 u32 func_en_val;
1112 func_en_val =
1113 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1114 func_en_val =
1115 (func_en_val & ~mux->funcmask) | (mux->
1116 funcval);
1117 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1118 }
1119}
1120
1121static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1122 unsigned group)
1123{
1124 struct sirfsoc_pmx *spmx;
1125
1126 spmx = pinctrl_dev_get_drvdata(pmxdev);
1127 sirfsoc_pinmux_endisable(spmx, selector, true);
1128
1129 return 0;
1130}
1131
1132static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1133 unsigned group)
1134{
1135 struct sirfsoc_pmx *spmx;
1136
1137 spmx = pinctrl_dev_get_drvdata(pmxdev);
1138 sirfsoc_pinmux_endisable(spmx, selector, false);
1139}
1140
1141static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1142{
1143 return ARRAY_SIZE(sirfsoc_pmx_functions);
1144}
1145
1146static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1147 unsigned selector)
1148{
1149 return sirfsoc_pmx_functions[selector].name;
1150}
1151
1152static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1153 const char * const **groups,
1154 unsigned * const num_groups)
1155{
1156 *groups = sirfsoc_pmx_functions[selector].groups;
1157 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1158 return 0;
1159}
1160
1161static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1162 struct pinctrl_gpio_range *range, unsigned offset)
1163{
1164 struct sirfsoc_pmx *spmx;
1165
1166 int group = range->id;
1167
1168 u32 muxval;
1169
1170 spmx = pinctrl_dev_get_drvdata(pmxdev);
1171
1172 if (!spmx->is_marco) {
1173 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1174 muxval = muxval | (1 << (offset - range->pin_base));
1175 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1176 } else {
1177 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
1178 SIRFSOC_GPIO_PAD_EN(group));
1179 }
1180
1181 return 0;
1182}
1183
1184static const struct pinmux_ops sirfsoc_pinmux_ops = {
1185 .enable = sirfsoc_pinmux_enable,
1186 .disable = sirfsoc_pinmux_disable,
1187 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1188 .get_function_name = sirfsoc_pinmux_get_func_name,
1189 .get_function_groups = sirfsoc_pinmux_get_groups,
1190 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1191};
1192
1193static struct pinctrl_desc sirfsoc_pinmux_desc = {
1194 .name = DRIVER_NAME,
1195 .pins = sirfsoc_pads,
1196 .npins = ARRAY_SIZE(sirfsoc_pads),
1197 .pctlops = &sirfsoc_pctrl_ops,
1198 .pmxops = &sirfsoc_pinmux_ops,
1199 .owner = THIS_MODULE,
1200};
1201
1202/*
1203 * Todo: bind irq_chip to every pinctrl_gpio_range
1204 */
1205static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1206 {
1207 .name = "sirfsoc-gpio*",
1208 .id = 0,
1209 .base = 0,
1210 .pin_base = 0,
1211 .npins = 32,
1212 }, {
1213 .name = "sirfsoc-gpio*",
1214 .id = 1,
1215 .base = 32,
1216 .pin_base = 32,
1217 .npins = 32,
1218 }, {
1219 .name = "sirfsoc-gpio*",
1220 .id = 2,
1221 .base = 64,
1222 .pin_base = 64,
1223 .npins = 32,
1224 }, {
1225 .name = "sirfsoc-gpio*",
1226 .id = 3,
1227 .base = 96,
1228 .pin_base = 96,
1229 .npins = 19,
1230 },
1231};
1232
1233static void __iomem *sirfsoc_rsc_of_iomap(void)
1234{
1235 const struct of_device_id rsc_ids[] = {
1236 { .compatible = "sirf,prima2-rsc" },
1237 { .compatible = "sirf,marco-rsc" },
1238 {}
1239 };
1240 struct device_node *np;
1241
1242 np = of_find_matching_node(NULL, rsc_ids);
1243 if (!np)
1244 panic("unable to find compatible rsc node in dtb\n");
1245
1246 return of_iomap(np, 0);
1247}
1248
1249static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
1250 const struct of_phandle_args *gpiospec,
1251 u32 *flags)
1252{
1253 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
1254 return -EINVAL;
1255
1256 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
1257 return -EINVAL;
1258
1259 if (flags)
1260 *flags = gpiospec->args[1];
1261
1262 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
1263}
1264
1265static int sirfsoc_pinmux_probe(struct platform_device *pdev)
1266{
1267 int ret;
1268 struct sirfsoc_pmx *spmx;
1269 struct device_node *np = pdev->dev.of_node;
1270 int i;
1271
1272 /* Create state holders etc for this driver */
1273 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1274 if (!spmx)
1275 return -ENOMEM;
1276
1277 spmx->dev = &pdev->dev;
1278
1279 platform_set_drvdata(pdev, spmx);
1280
1281 spmx->gpio_virtbase = of_iomap(np, 0);
1282 if (!spmx->gpio_virtbase) {
1283 ret = -ENOMEM;
1284 dev_err(&pdev->dev, "can't map gpio registers\n");
1285 goto out_no_gpio_remap;
1286 }
1287
1288 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1289 if (!spmx->rsc_virtbase) {
1290 ret = -ENOMEM;
1291 dev_err(&pdev->dev, "can't map rsc registers\n");
1292 goto out_no_rsc_remap;
1293 }
1294
1295 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1296 spmx->is_marco = 1;
1297
1298 /* Now register the pin controller and all pins it handles */
1299 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1300 if (!spmx->pmx) {
1301 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1302 ret = -EINVAL;
1303 goto out_no_pmx;
1304 }
1305
1306 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
1307 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
1308 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1309 }
1310
1311 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1312
1313 return 0;
1314
1315out_no_pmx:
1316 iounmap(spmx->rsc_virtbase);
1317out_no_rsc_remap:
1318 iounmap(spmx->gpio_virtbase);
1319out_no_gpio_remap:
1320 platform_set_drvdata(pdev, NULL);
1321 return ret;
1322}
1323
1324static const struct of_device_id pinmux_ids[] = {
1325 { .compatible = "sirf,prima2-pinctrl" },
1326 { .compatible = "sirf,marco-pinctrl" },
1327 {}
1328};
1329
1330static struct platform_driver sirfsoc_pinmux_driver = {
1331 .driver = {
1332 .name = DRIVER_NAME,
1333 .owner = THIS_MODULE,
1334 .of_match_table = pinmux_ids,
1335 },
1336 .probe = sirfsoc_pinmux_probe,
1337}; 886};
1338 887
1339static int __init sirfsoc_pinmux_init(void)
1340{
1341 return platform_driver_register(&sirfsoc_pinmux_driver);
1342}
1343arch_initcall(sirfsoc_pinmux_init);
1344
1345static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1346{
1347 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1348 struct sirfsoc_gpio_bank, chip);
1349
1350 return irq_create_mapping(bank->domain, offset);
1351}
1352
1353static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1354{
1355 return gpio % SIRFSOC_GPIO_BANK_SIZE;
1356}
1357
1358static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1359{
1360 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1361}
1362
1363static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1364{
1365 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1366}
1367
1368static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1369{
1370 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1371 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1372 u32 val, offset;
1373 unsigned long flags;
1374
1375 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1376
1377 spin_lock_irqsave(&sgpio_lock, flags);
1378
1379 val = readl(bank->chip.regs + offset);
1380
1381 writel(val, bank->chip.regs + offset);
1382
1383 spin_unlock_irqrestore(&sgpio_lock, flags);
1384}
1385
1386static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1387{
1388 u32 val, offset;
1389 unsigned long flags;
1390
1391 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1392
1393 spin_lock_irqsave(&sgpio_lock, flags);
1394
1395 val = readl(bank->chip.regs + offset);
1396 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1397 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1398 writel(val, bank->chip.regs + offset);
1399
1400 spin_unlock_irqrestore(&sgpio_lock, flags);
1401}
1402
1403static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1404{
1405 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1406
1407 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1408}
1409
1410static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1411{
1412 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1413 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1414 u32 val, offset;
1415 unsigned long flags;
1416
1417 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1418
1419 spin_lock_irqsave(&sgpio_lock, flags);
1420
1421 val = readl(bank->chip.regs + offset);
1422 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1423 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1424 writel(val, bank->chip.regs + offset);
1425
1426 spin_unlock_irqrestore(&sgpio_lock, flags);
1427}
1428
1429static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1430{
1431 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1432 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1433 u32 val, offset;
1434 unsigned long flags;
1435
1436 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1437
1438 spin_lock_irqsave(&sgpio_lock, flags);
1439
1440 val = readl(bank->chip.regs + offset);
1441 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1442
1443 switch (type) {
1444 case IRQ_TYPE_NONE:
1445 break;
1446 case IRQ_TYPE_EDGE_RISING:
1447 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1448 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1449 break;
1450 case IRQ_TYPE_EDGE_FALLING:
1451 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1452 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1453 break;
1454 case IRQ_TYPE_EDGE_BOTH:
1455 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1456 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1457 break;
1458 case IRQ_TYPE_LEVEL_LOW:
1459 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1460 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1461 break;
1462 case IRQ_TYPE_LEVEL_HIGH:
1463 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1464 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1465 break;
1466 }
1467
1468 writel(val, bank->chip.regs + offset);
1469
1470 spin_unlock_irqrestore(&sgpio_lock, flags);
1471
1472 return 0;
1473}
1474
1475static struct irq_chip sirfsoc_irq_chip = {
1476 .name = "sirf-gpio-irq",
1477 .irq_ack = sirfsoc_gpio_irq_ack,
1478 .irq_mask = sirfsoc_gpio_irq_mask,
1479 .irq_unmask = sirfsoc_gpio_irq_unmask,
1480 .irq_set_type = sirfsoc_gpio_irq_type,
1481};
1482
1483static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1484{
1485 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1486 u32 status, ctrl;
1487 int idx = 0;
1488 struct irq_chip *chip = irq_get_chip(irq);
1489
1490 chained_irq_enter(chip, desc);
1491
1492 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1493 if (!status) {
1494 printk(KERN_WARNING
1495 "%s: gpio id %d status %#x no interrupt is flaged\n",
1496 __func__, bank->id, status);
1497 handle_bad_irq(irq, desc);
1498 return;
1499 }
1500
1501 while (status) {
1502 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1503
1504 /*
1505 * Here we must check whether the corresponding GPIO's interrupt
1506 * has been enabled, otherwise just skip it
1507 */
1508 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1509 pr_debug("%s: gpio id %d idx %d happens\n",
1510 __func__, bank->id, idx);
1511 generic_handle_irq(irq_find_mapping(bank->domain, idx));
1512 }
1513
1514 idx++;
1515 status = status >> 1;
1516 }
1517
1518 chained_irq_exit(chip, desc);
1519}
1520
1521static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1522{
1523 u32 val;
1524
1525 val = readl(bank->chip.regs + ctrl_offset);
1526 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1527 writel(val, bank->chip.regs + ctrl_offset);
1528}
1529
1530static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1531{
1532 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1533 unsigned long flags;
1534
1535 if (pinctrl_request_gpio(chip->base + offset))
1536 return -ENODEV;
1537
1538 spin_lock_irqsave(&bank->lock, flags);
1539
1540 /*
1541 * default status:
1542 * set direction as input and mask irq
1543 */
1544 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1545 __sirfsoc_gpio_irq_mask(bank, offset);
1546
1547 spin_unlock_irqrestore(&bank->lock, flags);
1548
1549 return 0;
1550}
1551
1552static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1553{
1554 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1555 unsigned long flags;
1556
1557 spin_lock_irqsave(&bank->lock, flags);
1558
1559 __sirfsoc_gpio_irq_mask(bank, offset);
1560 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1561
1562 spin_unlock_irqrestore(&bank->lock, flags);
1563
1564 pinctrl_free_gpio(chip->base + offset);
1565}
1566
1567static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1568{
1569 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1570 int idx = sirfsoc_gpio_to_offset(gpio);
1571 unsigned long flags;
1572 unsigned offset;
1573
1574 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1575
1576 spin_lock_irqsave(&bank->lock, flags);
1577
1578 sirfsoc_gpio_set_input(bank, offset);
1579
1580 spin_unlock_irqrestore(&bank->lock, flags);
1581
1582 return 0;
1583}
1584
1585static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1586 int value)
1587{
1588 u32 out_ctrl;
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(&bank->lock, flags);
1592
1593 out_ctrl = readl(bank->chip.regs + offset);
1594 if (value)
1595 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1596 else
1597 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1598
1599 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1600 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1601 writel(out_ctrl, bank->chip.regs + offset);
1602
1603 spin_unlock_irqrestore(&bank->lock, flags);
1604}
1605
1606static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1607{
1608 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1609 int idx = sirfsoc_gpio_to_offset(gpio);
1610 u32 offset;
1611 unsigned long flags;
1612
1613 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1614
1615 spin_lock_irqsave(&sgpio_lock, flags);
1616
1617 sirfsoc_gpio_set_output(bank, offset, value);
1618
1619 spin_unlock_irqrestore(&sgpio_lock, flags);
1620
1621 return 0;
1622}
1623
1624static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1625{
1626 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1627 u32 val;
1628 unsigned long flags;
1629
1630 spin_lock_irqsave(&bank->lock, flags);
1631
1632 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1633
1634 spin_unlock_irqrestore(&bank->lock, flags);
1635
1636 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1637}
1638
1639static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1640 int value)
1641{
1642 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1643 u32 ctrl;
1644 unsigned long flags;
1645
1646 spin_lock_irqsave(&bank->lock, flags);
1647
1648 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1649 if (value)
1650 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1651 else
1652 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1653 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1654
1655 spin_unlock_irqrestore(&bank->lock, flags);
1656}
1657
1658static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1659 irq_hw_number_t hwirq)
1660{
1661 struct sirfsoc_gpio_bank *bank = d->host_data;
1662
1663 if (!bank)
1664 return -EINVAL;
1665
1666 irq_set_chip(irq, &sirfsoc_irq_chip);
1667 irq_set_handler(irq, handle_level_irq);
1668 irq_set_chip_data(irq, bank);
1669 set_irq_flags(irq, IRQF_VALID);
1670
1671 return 0;
1672}
1673
1674const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1675 .map = sirfsoc_gpio_irq_map,
1676 .xlate = irq_domain_xlate_twocell,
1677};
1678
1679static void sirfsoc_gpio_set_pullup(const u32 *pullups)
1680{
1681 int i, n;
1682 const unsigned long *p = (const unsigned long *)pullups;
1683
1684 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1685 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1686 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1687 u32 val = readl(sgpio_bank[i].chip.regs + offset);
1688 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1689 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1690 writel(val, sgpio_bank[i].chip.regs + offset);
1691 }
1692 }
1693}
1694
1695static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
1696{
1697 int i, n;
1698 const unsigned long *p = (const unsigned long *)pulldowns;
1699
1700 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1701 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1702 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1703 u32 val = readl(sgpio_bank[i].chip.regs + offset);
1704 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1705 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1706 writel(val, sgpio_bank[i].chip.regs + offset);
1707 }
1708 }
1709}
1710
1711static int sirfsoc_gpio_probe(struct device_node *np)
1712{
1713 int i, err = 0;
1714 struct sirfsoc_gpio_bank *bank;
1715 void *regs;
1716 struct platform_device *pdev;
1717 bool is_marco = false;
1718
1719 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
1720
1721 pdev = of_find_device_by_node(np);
1722 if (!pdev)
1723 return -ENODEV;
1724
1725 regs = of_iomap(np, 0);
1726 if (!regs)
1727 return -ENOMEM;
1728
1729 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1730 is_marco = 1;
1731
1732 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1733 bank = &sgpio_bank[i];
1734 spin_lock_init(&bank->lock);
1735 bank->chip.gc.request = sirfsoc_gpio_request;
1736 bank->chip.gc.free = sirfsoc_gpio_free;
1737 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1738 bank->chip.gc.get = sirfsoc_gpio_get_value;
1739 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1740 bank->chip.gc.set = sirfsoc_gpio_set_value;
1741 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1742 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1743 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1744 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1745 bank->chip.gc.of_node = np;
1746 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
1747 bank->chip.gc.of_gpio_n_cells = 2;
1748 bank->chip.regs = regs;
1749 bank->id = i;
1750 bank->is_marco = is_marco;
1751 bank->parent_irq = platform_get_irq(pdev, i);
1752 if (bank->parent_irq < 0) {
1753 err = bank->parent_irq;
1754 goto out;
1755 }
1756
1757 err = gpiochip_add(&bank->chip.gc);
1758 if (err) {
1759 pr_err("%s: error in probe function with status %d\n",
1760 np->full_name, err);
1761 goto out;
1762 }
1763
1764 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
1765 &sirfsoc_gpio_irq_simple_ops, bank);
1766
1767 if (!bank->domain) {
1768 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1769 err = -ENOSYS;
1770 goto out;
1771 }
1772
1773 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1774 irq_set_handler_data(bank->parent_irq, bank);
1775 }
1776
1777 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
1778 SIRFSOC_GPIO_NO_OF_BANKS))
1779 sirfsoc_gpio_set_pullup(pullups);
1780
1781 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
1782 SIRFSOC_GPIO_NO_OF_BANKS))
1783 sirfsoc_gpio_set_pulldown(pulldowns);
1784
1785 return 0;
1786
1787out:
1788 iounmap(regs);
1789 return err;
1790}
1791
1792static int __init sirfsoc_gpio_init(void)
1793{
1794
1795 struct device_node *np;
1796
1797 np = of_find_matching_node(NULL, pinmux_ids);
1798
1799 if (!np)
1800 return -ENODEV;
1801
1802 return sirfsoc_gpio_probe(np);
1803}
1804subsys_initcall(sirfsoc_gpio_init);
1805
1806MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1807 "Yuping Luo <yuping.luo@csr.com>, "
1808 "Barry Song <baohua.song@csr.com>");
1809MODULE_DESCRIPTION("SIRFSOC pin control driver");
1810MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
new file mode 100644
index 000000000000..0677e198db60
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -0,0 +1,929 @@
1/*
2 * pinmux driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/of_platform.h>
26#include <linux/bitops.h>
27#include <linux/gpio.h>
28#include <linux/of_gpio.h>
29#include <asm/mach/irq.h>
30
31#include "pinctrl-sirf.h"
32
33#define DRIVER_NAME "pinmux-sirf"
34
35struct sirfsoc_gpio_bank {
36 struct of_mm_gpio_chip chip;
37 struct irq_domain *domain;
38 int id;
39 int parent_irq;
40 spinlock_t lock;
41 bool is_marco; /* for marco, some registers are different with prima2 */
42};
43
44static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45static DEFINE_SPINLOCK(sgpio_lock);
46
47static struct sirfsoc_pin_group *sirfsoc_pin_groups;
48static int sirfsoc_pingrp_cnt;
49
50static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
51{
52 return sirfsoc_pingrp_cnt;
53}
54
55static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
56 unsigned selector)
57{
58 return sirfsoc_pin_groups[selector].name;
59}
60
61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
62 const unsigned **pins,
63 unsigned *num_pins)
64{
65 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins;
67 return 0;
68}
69
70static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
71 unsigned offset)
72{
73 seq_printf(s, " " DRIVER_NAME);
74}
75
76static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
77 struct device_node *np_config,
78 struct pinctrl_map **map, unsigned *num_maps)
79{
80 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
81 struct device_node *np;
82 struct property *prop;
83 const char *function, *group;
84 int ret, index = 0, count = 0;
85
86 /* calculate number of maps required */
87 for_each_child_of_node(np_config, np) {
88 ret = of_property_read_string(np, "sirf,function", &function);
89 if (ret < 0)
90 return ret;
91
92 ret = of_property_count_strings(np, "sirf,pins");
93 if (ret < 0)
94 return ret;
95
96 count += ret;
97 }
98
99 if (!count) {
100 dev_err(spmx->dev, "No child nodes passed via DT\n");
101 return -ENODEV;
102 }
103
104 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
105 if (!*map)
106 return -ENOMEM;
107
108 for_each_child_of_node(np_config, np) {
109 of_property_read_string(np, "sirf,function", &function);
110 of_property_for_each_string(np, "sirf,pins", prop, group) {
111 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
112 (*map)[index].data.mux.group = group;
113 (*map)[index].data.mux.function = function;
114 index++;
115 }
116 }
117
118 *num_maps = count;
119
120 return 0;
121}
122
123static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
124 struct pinctrl_map *map, unsigned num_maps)
125{
126 kfree(map);
127}
128
129static struct pinctrl_ops sirfsoc_pctrl_ops = {
130 .get_groups_count = sirfsoc_get_groups_count,
131 .get_group_name = sirfsoc_get_group_name,
132 .get_group_pins = sirfsoc_get_group_pins,
133 .pin_dbg_show = sirfsoc_pin_dbg_show,
134 .dt_node_to_map = sirfsoc_dt_node_to_map,
135 .dt_free_map = sirfsoc_dt_free_map,
136};
137
138static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139static int sirfsoc_pmxfunc_cnt;
140
141static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
142 bool enable)
143{
144 int i;
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask;
147
148 for (i = 0; i < mux->muxmask_counts; i++) {
149 u32 muxval;
150 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
152 if (enable)
153 muxval = muxval & ~mask[i].mask;
154 else
155 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
157 } else {
158 if (enable)
159 writel(mask[i].mask, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
161 else
162 writel(mask[i].mask, spmx->gpio_virtbase +
163 SIRFSOC_GPIO_PAD_EN(mask[i].group));
164 }
165 }
166
167 if (mux->funcmask && enable) {
168 u32 func_en_val;
169 func_en_val =
170 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
171 func_en_val =
172 (func_en_val & ~mux->funcmask) | (mux->
173 funcval);
174 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
175 }
176}
177
178static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
179 unsigned group)
180{
181 struct sirfsoc_pmx *spmx;
182
183 spmx = pinctrl_dev_get_drvdata(pmxdev);
184 sirfsoc_pinmux_endisable(spmx, selector, true);
185
186 return 0;
187}
188
189static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
190 unsigned group)
191{
192 struct sirfsoc_pmx *spmx;
193
194 spmx = pinctrl_dev_get_drvdata(pmxdev);
195 sirfsoc_pinmux_endisable(spmx, selector, false);
196}
197
198static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
199{
200 return sirfsoc_pmxfunc_cnt;
201}
202
203static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
204 unsigned selector)
205{
206 return sirfsoc_pmx_functions[selector].name;
207}
208
209static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
210 const char * const **groups,
211 unsigned * const num_groups)
212{
213 *groups = sirfsoc_pmx_functions[selector].groups;
214 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
215 return 0;
216}
217
218static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
219 struct pinctrl_gpio_range *range, unsigned offset)
220{
221 struct sirfsoc_pmx *spmx;
222
223 int group = range->id;
224
225 u32 muxval;
226
227 spmx = pinctrl_dev_get_drvdata(pmxdev);
228
229 if (!spmx->is_marco) {
230 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
231 muxval = muxval | (1 << (offset - range->pin_base));
232 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
233 } else {
234 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
235 SIRFSOC_GPIO_PAD_EN(group));
236 }
237
238 return 0;
239}
240
241static struct pinmux_ops sirfsoc_pinmux_ops = {
242 .enable = sirfsoc_pinmux_enable,
243 .disable = sirfsoc_pinmux_disable,
244 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
245 .get_function_name = sirfsoc_pinmux_get_func_name,
246 .get_function_groups = sirfsoc_pinmux_get_groups,
247 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
248};
249
250static struct pinctrl_desc sirfsoc_pinmux_desc = {
251 .name = DRIVER_NAME,
252 .pctlops = &sirfsoc_pctrl_ops,
253 .pmxops = &sirfsoc_pinmux_ops,
254 .owner = THIS_MODULE,
255};
256
257/*
258 * Todo: bind irq_chip to every pinctrl_gpio_range
259 */
260static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
261 {
262 .name = "sirfsoc-gpio*",
263 .id = 0,
264 .base = 0,
265 .pin_base = 0,
266 .npins = 32,
267 }, {
268 .name = "sirfsoc-gpio*",
269 .id = 1,
270 .base = 32,
271 .pin_base = 32,
272 .npins = 32,
273 }, {
274 .name = "sirfsoc-gpio*",
275 .id = 2,
276 .base = 64,
277 .pin_base = 64,
278 .npins = 32,
279 }, {
280 .name = "sirfsoc-gpio*",
281 .id = 3,
282 .base = 96,
283 .pin_base = 96,
284 .npins = 19,
285 },
286};
287
288static void __iomem *sirfsoc_rsc_of_iomap(void)
289{
290 const struct of_device_id rsc_ids[] = {
291 { .compatible = "sirf,prima2-rsc" },
292 { .compatible = "sirf,marco-rsc" },
293 {}
294 };
295 struct device_node *np;
296
297 np = of_find_matching_node(NULL, rsc_ids);
298 if (!np)
299 panic("unable to find compatible rsc node in dtb\n");
300
301 return of_iomap(np, 0);
302}
303
304static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
305 const struct of_phandle_args *gpiospec,
306 u32 *flags)
307{
308 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
309 return -EINVAL;
310
311 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
312 return -EINVAL;
313
314 if (flags)
315 *flags = gpiospec->args[1];
316
317 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
318}
319
320static const struct of_device_id pinmux_ids[] = {
321 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
322 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
323 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
324 {}
325};
326
327static int sirfsoc_pinmux_probe(struct platform_device *pdev)
328{
329 int ret;
330 struct sirfsoc_pmx *spmx;
331 struct device_node *np = pdev->dev.of_node;
332 const struct sirfsoc_pinctrl_data *pdata;
333 int i;
334
335 /* Create state holders etc for this driver */
336 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
337 if (!spmx)
338 return -ENOMEM;
339
340 spmx->dev = &pdev->dev;
341
342 platform_set_drvdata(pdev, spmx);
343
344 spmx->gpio_virtbase = of_iomap(np, 0);
345 if (!spmx->gpio_virtbase) {
346 dev_err(&pdev->dev, "can't map gpio registers\n");
347 return -ENOMEM;
348 }
349
350 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
351 if (!spmx->rsc_virtbase) {
352 ret = -ENOMEM;
353 dev_err(&pdev->dev, "can't map rsc registers\n");
354 goto out_no_rsc_remap;
355 }
356
357 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
358 spmx->is_marco = 1;
359
360 pdata = of_match_node(pinmux_ids, np)->data;
361 sirfsoc_pin_groups = pdata->grps;
362 sirfsoc_pingrp_cnt = pdata->grps_cnt;
363 sirfsoc_pmx_functions = pdata->funcs;
364 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
365 sirfsoc_pinmux_desc.pins = pdata->pads;
366 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
367
368
369 /* Now register the pin controller and all pins it handles */
370 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
371 if (!spmx->pmx) {
372 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
373 ret = -EINVAL;
374 goto out_no_pmx;
375 }
376
377 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
378 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
379 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
380 }
381
382 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
383
384 return 0;
385
386out_no_pmx:
387 iounmap(spmx->rsc_virtbase);
388out_no_rsc_remap:
389 iounmap(spmx->gpio_virtbase);
390 return ret;
391}
392
393#ifdef CONFIG_PM_SLEEP
394static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
395{
396 int i, j;
397 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
398
399 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
400 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
401 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
402 SIRFSOC_GPIO_CTRL(i, j));
403 }
404 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
405 SIRFSOC_GPIO_INT_STATUS(i));
406 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
407 SIRFSOC_GPIO_PAD_EN(i));
408 }
409 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
410
411 for (i = 0; i < 3; i++)
412 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
413
414 return 0;
415}
416
417static int sirfsoc_pinmux_resume_noirq(struct device *dev)
418{
419 int i, j;
420 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
421
422 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
423 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
424 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
425 SIRFSOC_GPIO_CTRL(i, j));
426 }
427 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
428 SIRFSOC_GPIO_INT_STATUS(i));
429 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
430 SIRFSOC_GPIO_PAD_EN(i));
431 }
432 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
433
434 for (i = 0; i < 3; i++)
435 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
436
437 return 0;
438}
439
440static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
441 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
442 .resume_noirq = sirfsoc_pinmux_resume_noirq,
443};
444#endif
445
446static struct platform_driver sirfsoc_pinmux_driver = {
447 .driver = {
448 .name = DRIVER_NAME,
449 .owner = THIS_MODULE,
450 .of_match_table = pinmux_ids,
451#ifdef CONFIG_PM_SLEEP
452 .pm = &sirfsoc_pinmux_pm_ops,
453#endif
454 },
455 .probe = sirfsoc_pinmux_probe,
456};
457
458static int __init sirfsoc_pinmux_init(void)
459{
460 return platform_driver_register(&sirfsoc_pinmux_driver);
461}
462arch_initcall(sirfsoc_pinmux_init);
463
464static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
465{
466 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
467 struct sirfsoc_gpio_bank, chip);
468
469 return irq_create_mapping(bank->domain, offset);
470}
471
472static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
473{
474 return gpio % SIRFSOC_GPIO_BANK_SIZE;
475}
476
477static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
478{
479 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
480}
481
482static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
483{
484 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
485}
486
487static void sirfsoc_gpio_irq_ack(struct irq_data *d)
488{
489 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
490 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
491 u32 val, offset;
492 unsigned long flags;
493
494 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
495
496 spin_lock_irqsave(&sgpio_lock, flags);
497
498 val = readl(bank->chip.regs + offset);
499
500 writel(val, bank->chip.regs + offset);
501
502 spin_unlock_irqrestore(&sgpio_lock, flags);
503}
504
505static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
506{
507 u32 val, offset;
508 unsigned long flags;
509
510 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
511
512 spin_lock_irqsave(&sgpio_lock, flags);
513
514 val = readl(bank->chip.regs + offset);
515 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
516 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
517 writel(val, bank->chip.regs + offset);
518
519 spin_unlock_irqrestore(&sgpio_lock, flags);
520}
521
522static void sirfsoc_gpio_irq_mask(struct irq_data *d)
523{
524 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
525
526 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
527}
528
529static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
530{
531 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
532 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
533 u32 val, offset;
534 unsigned long flags;
535
536 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
537
538 spin_lock_irqsave(&sgpio_lock, flags);
539
540 val = readl(bank->chip.regs + offset);
541 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
542 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
543 writel(val, bank->chip.regs + offset);
544
545 spin_unlock_irqrestore(&sgpio_lock, flags);
546}
547
548static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
549{
550 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
551 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
552 u32 val, offset;
553 unsigned long flags;
554
555 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
556
557 spin_lock_irqsave(&sgpio_lock, flags);
558
559 val = readl(bank->chip.regs + offset);
560 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
561
562 switch (type) {
563 case IRQ_TYPE_NONE:
564 break;
565 case IRQ_TYPE_EDGE_RISING:
566 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
567 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
568 break;
569 case IRQ_TYPE_EDGE_FALLING:
570 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
571 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
572 break;
573 case IRQ_TYPE_EDGE_BOTH:
574 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
575 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
576 break;
577 case IRQ_TYPE_LEVEL_LOW:
578 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
579 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
580 break;
581 case IRQ_TYPE_LEVEL_HIGH:
582 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
583 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
584 break;
585 }
586
587 writel(val, bank->chip.regs + offset);
588
589 spin_unlock_irqrestore(&sgpio_lock, flags);
590
591 return 0;
592}
593
594static struct irq_chip sirfsoc_irq_chip = {
595 .name = "sirf-gpio-irq",
596 .irq_ack = sirfsoc_gpio_irq_ack,
597 .irq_mask = sirfsoc_gpio_irq_mask,
598 .irq_unmask = sirfsoc_gpio_irq_unmask,
599 .irq_set_type = sirfsoc_gpio_irq_type,
600};
601
602static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
603{
604 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
605 u32 status, ctrl;
606 int idx = 0;
607 struct irq_chip *chip = irq_get_chip(irq);
608
609 chained_irq_enter(chip, desc);
610
611 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
612 if (!status) {
613 printk(KERN_WARNING
614 "%s: gpio id %d status %#x no interrupt is flaged\n",
615 __func__, bank->id, status);
616 handle_bad_irq(irq, desc);
617 return;
618 }
619
620 while (status) {
621 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
622
623 /*
624 * Here we must check whether the corresponding GPIO's interrupt
625 * has been enabled, otherwise just skip it
626 */
627 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
628 pr_debug("%s: gpio id %d idx %d happens\n",
629 __func__, bank->id, idx);
630 generic_handle_irq(irq_find_mapping(bank->domain, idx));
631 }
632
633 idx++;
634 status = status >> 1;
635 }
636
637 chained_irq_exit(chip, desc);
638}
639
640static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
641{
642 u32 val;
643
644 val = readl(bank->chip.regs + ctrl_offset);
645 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
646 writel(val, bank->chip.regs + ctrl_offset);
647}
648
649static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
650{
651 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
652 unsigned long flags;
653
654 if (pinctrl_request_gpio(chip->base + offset))
655 return -ENODEV;
656
657 spin_lock_irqsave(&bank->lock, flags);
658
659 /*
660 * default status:
661 * set direction as input and mask irq
662 */
663 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
664 __sirfsoc_gpio_irq_mask(bank, offset);
665
666 spin_unlock_irqrestore(&bank->lock, flags);
667
668 return 0;
669}
670
671static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
672{
673 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
674 unsigned long flags;
675
676 spin_lock_irqsave(&bank->lock, flags);
677
678 __sirfsoc_gpio_irq_mask(bank, offset);
679 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
680
681 spin_unlock_irqrestore(&bank->lock, flags);
682
683 pinctrl_free_gpio(chip->base + offset);
684}
685
686static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
687{
688 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
689 int idx = sirfsoc_gpio_to_offset(gpio);
690 unsigned long flags;
691 unsigned offset;
692
693 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
694
695 spin_lock_irqsave(&bank->lock, flags);
696
697 sirfsoc_gpio_set_input(bank, offset);
698
699 spin_unlock_irqrestore(&bank->lock, flags);
700
701 return 0;
702}
703
704static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
705 int value)
706{
707 u32 out_ctrl;
708 unsigned long flags;
709
710 spin_lock_irqsave(&bank->lock, flags);
711
712 out_ctrl = readl(bank->chip.regs + offset);
713 if (value)
714 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
715 else
716 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
717
718 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
719 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
720 writel(out_ctrl, bank->chip.regs + offset);
721
722 spin_unlock_irqrestore(&bank->lock, flags);
723}
724
725static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
726{
727 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
728 int idx = sirfsoc_gpio_to_offset(gpio);
729 u32 offset;
730 unsigned long flags;
731
732 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
733
734 spin_lock_irqsave(&sgpio_lock, flags);
735
736 sirfsoc_gpio_set_output(bank, offset, value);
737
738 spin_unlock_irqrestore(&sgpio_lock, flags);
739
740 return 0;
741}
742
743static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
744{
745 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
746 u32 val;
747 unsigned long flags;
748
749 spin_lock_irqsave(&bank->lock, flags);
750
751 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
752
753 spin_unlock_irqrestore(&bank->lock, flags);
754
755 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
756}
757
758static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
759 int value)
760{
761 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
762 u32 ctrl;
763 unsigned long flags;
764
765 spin_lock_irqsave(&bank->lock, flags);
766
767 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
768 if (value)
769 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
770 else
771 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
772 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
773
774 spin_unlock_irqrestore(&bank->lock, flags);
775}
776
777static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
778 irq_hw_number_t hwirq)
779{
780 struct sirfsoc_gpio_bank *bank = d->host_data;
781
782 if (!bank)
783 return -EINVAL;
784
785 irq_set_chip(irq, &sirfsoc_irq_chip);
786 irq_set_handler(irq, handle_level_irq);
787 irq_set_chip_data(irq, bank);
788 set_irq_flags(irq, IRQF_VALID);
789
790 return 0;
791}
792
793static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
794 .map = sirfsoc_gpio_irq_map,
795 .xlate = irq_domain_xlate_twocell,
796};
797
798static void sirfsoc_gpio_set_pullup(const u32 *pullups)
799{
800 int i, n;
801 const unsigned long *p = (const unsigned long *)pullups;
802
803 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
804 for_each_set_bit(n, p + i, BITS_PER_LONG) {
805 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
806 u32 val = readl(sgpio_bank[i].chip.regs + offset);
807 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
808 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
809 writel(val, sgpio_bank[i].chip.regs + offset);
810 }
811 }
812}
813
814static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
815{
816 int i, n;
817 const unsigned long *p = (const unsigned long *)pulldowns;
818
819 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
820 for_each_set_bit(n, p + i, BITS_PER_LONG) {
821 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
822 u32 val = readl(sgpio_bank[i].chip.regs + offset);
823 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
824 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
825 writel(val, sgpio_bank[i].chip.regs + offset);
826 }
827 }
828}
829
830static int sirfsoc_gpio_probe(struct device_node *np)
831{
832 int i, err = 0;
833 struct sirfsoc_gpio_bank *bank;
834 void *regs;
835 struct platform_device *pdev;
836 bool is_marco = false;
837
838 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
839
840 pdev = of_find_device_by_node(np);
841 if (!pdev)
842 return -ENODEV;
843
844 regs = of_iomap(np, 0);
845 if (!regs)
846 return -ENOMEM;
847
848 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
849 is_marco = 1;
850
851 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
852 bank = &sgpio_bank[i];
853 spin_lock_init(&bank->lock);
854 bank->chip.gc.request = sirfsoc_gpio_request;
855 bank->chip.gc.free = sirfsoc_gpio_free;
856 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
857 bank->chip.gc.get = sirfsoc_gpio_get_value;
858 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
859 bank->chip.gc.set = sirfsoc_gpio_set_value;
860 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
861 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
862 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
863 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
864 bank->chip.gc.of_node = np;
865 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
866 bank->chip.gc.of_gpio_n_cells = 2;
867 bank->chip.regs = regs;
868 bank->id = i;
869 bank->is_marco = is_marco;
870 bank->parent_irq = platform_get_irq(pdev, i);
871 if (bank->parent_irq < 0) {
872 err = bank->parent_irq;
873 goto out;
874 }
875
876 err = gpiochip_add(&bank->chip.gc);
877 if (err) {
878 pr_err("%s: error in probe function with status %d\n",
879 np->full_name, err);
880 goto out;
881 }
882
883 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
884 &sirfsoc_gpio_irq_simple_ops, bank);
885
886 if (!bank->domain) {
887 pr_err("%s: Failed to create irqdomain\n", np->full_name);
888 err = -ENOSYS;
889 goto out;
890 }
891
892 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
893 irq_set_handler_data(bank->parent_irq, bank);
894 }
895
896 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
897 SIRFSOC_GPIO_NO_OF_BANKS))
898 sirfsoc_gpio_set_pullup(pullups);
899
900 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
901 SIRFSOC_GPIO_NO_OF_BANKS))
902 sirfsoc_gpio_set_pulldown(pulldowns);
903
904 return 0;
905
906out:
907 iounmap(regs);
908 return err;
909}
910
911static int __init sirfsoc_gpio_init(void)
912{
913
914 struct device_node *np;
915
916 np = of_find_matching_node(NULL, pinmux_ids);
917
918 if (!np)
919 return -ENODEV;
920
921 return sirfsoc_gpio_probe(np);
922}
923subsys_initcall(sirfsoc_gpio_init);
924
925MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
926 "Yuping Luo <yuping.luo@csr.com>, "
927 "Barry Song <baohua.song@csr.com>");
928MODULE_DESCRIPTION("SIRFSOC pin control driver");
929MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
new file mode 100644
index 000000000000..17cc108510ba
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -0,0 +1,116 @@
1/*
2 * pinmux driver shared headfile for CSR SiRFsoc
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __PINMUX_SIRF_H__
10#define __PINMUX_SIRF_H__
11
12#define SIRFSOC_NUM_PADS 622
13#define SIRFSOC_RSC_PIN_MUX 0x4
14
15#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
16#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
17#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
18#define SIRFSOC_GPIO_DSP_EN0 (0x80)
19#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
20
21#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
22#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
23#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
24#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
25#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
26#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
27#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
28#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
29#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
30#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
31#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
32
33#define SIRFSOC_GPIO_NO_OF_BANKS 5
34#define SIRFSOC_GPIO_BANK_SIZE 32
35#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
36
37/**
38 * @dev: a pointer back to containing device
39 * @virtbase: the offset to the controller in virtual memory
40 */
41struct sirfsoc_pmx {
42 struct device *dev;
43 struct pinctrl_dev *pmx;
44 void __iomem *gpio_virtbase;
45 void __iomem *rsc_virtbase;
46 u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
47 u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
48 u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
49 u32 dspen_regs;
50 u32 rsc_regs[3];
51 bool is_marco;
52};
53
54/* SIRFSOC_GPIO_PAD_EN set */
55struct sirfsoc_muxmask {
56 unsigned long group;
57 unsigned long mask;
58};
59
60struct sirfsoc_padmux {
61 unsigned long muxmask_counts;
62 const struct sirfsoc_muxmask *muxmask;
63 /* RSC_PIN_MUX set */
64 unsigned long funcmask;
65 unsigned long funcval;
66};
67
68 /**
69 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
70 * @name: the name of this specific pin group
71 * @pins: an array of discrete physical pins used in this group, taken
72 * from the driver-local pin enumeration space
73 * @num_pins: the number of pins in this group array, i.e. the number of
74 * elements in .pins so we can iterate over that array
75 */
76struct sirfsoc_pin_group {
77 const char *name;
78 const unsigned int *pins;
79 const unsigned num_pins;
80};
81
82#define SIRFSOC_PIN_GROUP(n, p) \
83 { \
84 .name = n, \
85 .pins = p, \
86 .num_pins = ARRAY_SIZE(p), \
87 }
88
89struct sirfsoc_pmx_func {
90 const char *name;
91 const char * const *groups;
92 const unsigned num_groups;
93 const struct sirfsoc_padmux *padmux;
94};
95
96#define SIRFSOC_PMX_FUNCTION(n, g, m) \
97 { \
98 .name = n, \
99 .groups = g, \
100 .num_groups = ARRAY_SIZE(g), \
101 .padmux = &m, \
102 }
103
104struct sirfsoc_pinctrl_data {
105 struct pinctrl_pin_desc *pads;
106 int pads_cnt;
107 struct sirfsoc_pin_group *grps;
108 int grps_cnt;
109 struct sirfsoc_pmx_func *funcs;
110 int funcs_cnt;
111};
112
113extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
114extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
115
116#endif
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 3e5a887216b8..0a7f0bdbaa7d 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -441,7 +441,7 @@ static int spear310_p2o(int pin)
441 return offset; 441 return offset;
442} 442}
443 443
444int spear310_o2p(int offset) 444static int spear310_o2p(int offset)
445{ 445{
446 if (offset <= 3) 446 if (offset <= 3)
447 return 101 - offset; 447 return 101 - offset;
@@ -528,18 +528,13 @@ static int plgpio_probe(struct platform_device *pdev)
528 struct resource *res; 528 struct resource *res;
529 int ret, irq, i; 529 int ret, irq, i;
530 530
531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
532 if (!res) {
533 dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
534 return -EBUSY;
535 }
536
537 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 531 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
538 if (!plgpio) { 532 if (!plgpio) {
539 dev_err(&pdev->dev, "memory allocation fail\n"); 533 dev_err(&pdev->dev, "memory allocation fail\n");
540 return -ENOMEM; 534 return -ENOMEM;
541 } 535 }
542 536
537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 plgpio->base = devm_ioremap_resource(&pdev->dev, res); 538 plgpio->base = devm_ioremap_resource(&pdev->dev, res);
544 if (IS_ERR(plgpio->base)) 539 if (IS_ERR(plgpio->base))
545 return PTR_ERR(plgpio->base); 540 return PTR_ERR(plgpio->base);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 70d986e04afb..0cc4335bc0f2 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -569,11 +569,9 @@ int wmt_pinctrl_probe(struct platform_device *pdev,
569 struct resource *res; 569 struct resource *res;
570 570
571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 data->base = devm_request_and_ioremap(&pdev->dev, res); 572 data->base = devm_ioremap_resource(&pdev->dev, res);
573 if (!data->base) { 573 if (IS_ERR(data->base))
574 dev_err(&pdev->dev, "failed to map memory resource\n"); 574 return PTR_ERR(data->base);
575 return -EBUSY;
576 }
577 575
578 wmt_desc.pins = data->pins; 576 wmt_desc.pins = data->pins;
579 wmt_desc.npins = data->npins; 577 wmt_desc.npins = data->npins;
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 3b246543282f..abef061fb84a 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -368,11 +368,6 @@ struct pl022 {
368 resource_size_t phybase; 368 resource_size_t phybase;
369 void __iomem *virtbase; 369 void __iomem *virtbase;
370 struct clk *clk; 370 struct clk *clk;
371 /* Two optional pin states - default & sleep */
372 struct pinctrl *pinctrl;
373 struct pinctrl_state *pins_default;
374 struct pinctrl_state *pins_idle;
375 struct pinctrl_state *pins_sleep;
376 struct spi_master *master; 371 struct spi_master *master;
377 struct pl022_ssp_controller *master_info; 372 struct pl022_ssp_controller *master_info;
378 /* Message per-transfer pump */ 373 /* Message per-transfer pump */
@@ -2134,32 +2129,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2134 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2129 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2135 GFP_KERNEL); 2130 GFP_KERNEL);
2136 2131
2137 pl022->pinctrl = devm_pinctrl_get(dev); 2132 pinctrl_pm_select_default_state(dev);
2138 if (IS_ERR(pl022->pinctrl)) {
2139 status = PTR_ERR(pl022->pinctrl);
2140 goto err_no_pinctrl;
2141 }
2142
2143 pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl,
2144 PINCTRL_STATE_DEFAULT);
2145 /* enable pins to be muxed in and configured */
2146 if (!IS_ERR(pl022->pins_default)) {
2147 status = pinctrl_select_state(pl022->pinctrl,
2148 pl022->pins_default);
2149 if (status)
2150 dev_err(dev, "could not set default pins\n");
2151 } else
2152 dev_err(dev, "could not get default pinstate\n");
2153
2154 pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl,
2155 PINCTRL_STATE_IDLE);
2156 if (IS_ERR(pl022->pins_idle))
2157 dev_dbg(dev, "could not get idle pinstate\n");
2158
2159 pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl,
2160 PINCTRL_STATE_SLEEP);
2161 if (IS_ERR(pl022->pins_sleep))
2162 dev_dbg(dev, "could not get sleep pinstate\n");
2163 2133
2164 /* 2134 /*
2165 * Bus Number Which has been Assigned to this SSP controller 2135 * Bus Number Which has been Assigned to this SSP controller
@@ -2309,7 +2279,6 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2309 amba_release_regions(adev); 2279 amba_release_regions(adev);
2310 err_no_ioregion: 2280 err_no_ioregion:
2311 err_no_gpio: 2281 err_no_gpio:
2312 err_no_pinctrl:
2313 spi_master_put(master); 2282 spi_master_put(master);
2314 return status; 2283 return status;
2315} 2284}
@@ -2349,44 +2318,21 @@ pl022_remove(struct amba_device *adev)
2349 */ 2318 */
2350static void pl022_suspend_resources(struct pl022 *pl022, bool runtime) 2319static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
2351{ 2320{
2352 int ret;
2353 struct pinctrl_state *pins_state;
2354
2355 clk_disable(pl022->clk); 2321 clk_disable(pl022->clk);
2356 2322
2357 pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep; 2323 if (runtime)
2358 /* Optionally let pins go into sleep states */ 2324 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2359 if (!IS_ERR(pins_state)) { 2325 else
2360 ret = pinctrl_select_state(pl022->pinctrl, pins_state); 2326 pinctrl_pm_select_sleep_state(&pl022->adev->dev);
2361 if (ret)
2362 dev_err(&pl022->adev->dev, "could not set %s pins\n",
2363 runtime ? "idle" : "sleep");
2364 }
2365} 2327}
2366 2328
2367static void pl022_resume_resources(struct pl022 *pl022, bool runtime) 2329static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
2368{ 2330{
2369 int ret;
2370
2371 /* Optionaly enable pins to be muxed in and configured */
2372 /* First go to the default state */ 2331 /* First go to the default state */
2373 if (!IS_ERR(pl022->pins_default)) { 2332 pinctrl_pm_select_default_state(&pl022->adev->dev);
2374 ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default); 2333 if (!runtime)
2375 if (ret)
2376 dev_err(&pl022->adev->dev,
2377 "could not set default pins\n");
2378 }
2379
2380 if (!runtime) {
2381 /* Then let's idle the pins until the next transfer happens */ 2334 /* Then let's idle the pins until the next transfer happens */
2382 if (!IS_ERR(pl022->pins_idle)) { 2335 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2383 ret = pinctrl_select_state(pl022->pinctrl,
2384 pl022->pins_idle);
2385 if (ret)
2386 dev_err(&pl022->adev->dev,
2387 "could not set idle pins\n");
2388 }
2389 }
2390 2336
2391 clk_enable(pl022->clk); 2337 clk_enable(pl022->clk);
2392} 2338}
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index ad41319d1d9b..28b35ad9c6cd 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -150,10 +150,6 @@ struct pl011_dmatx_data {
150struct uart_amba_port { 150struct uart_amba_port {
151 struct uart_port port; 151 struct uart_port port;
152 struct clk *clk; 152 struct clk *clk;
153 /* Two optional pin states - default & sleep */
154 struct pinctrl *pinctrl;
155 struct pinctrl_state *pins_default;
156 struct pinctrl_state *pins_sleep;
157 const struct vendor_data *vendor; 153 const struct vendor_data *vendor;
158 unsigned int dmacr; /* dma control reg */ 154 unsigned int dmacr; /* dma control reg */
159 unsigned int im; /* interrupt mask */ 155 unsigned int im; /* interrupt mask */
@@ -1479,12 +1475,7 @@ static int pl011_hwinit(struct uart_port *port)
1479 int retval; 1475 int retval;
1480 1476
1481 /* Optionaly enable pins to be muxed in and configured */ 1477 /* Optionaly enable pins to be muxed in and configured */
1482 if (!IS_ERR(uap->pins_default)) { 1478 pinctrl_pm_select_default_state(port->dev);
1483 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1484 if (retval)
1485 dev_err(port->dev,
1486 "could not set default pins\n");
1487 }
1488 1479
1489 /* 1480 /*
1490 * Try to enable the clock producer. 1481 * Try to enable the clock producer.
@@ -1610,7 +1601,6 @@ static void pl011_shutdown(struct uart_port *port)
1610{ 1601{
1611 struct uart_amba_port *uap = (struct uart_amba_port *)port; 1602 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1612 unsigned int cr; 1603 unsigned int cr;
1613 int retval;
1614 1604
1615 /* 1605 /*
1616 * disable all interrupts 1606 * disable all interrupts
@@ -1653,13 +1643,7 @@ static void pl011_shutdown(struct uart_port *port)
1653 */ 1643 */
1654 clk_disable_unprepare(uap->clk); 1644 clk_disable_unprepare(uap->clk);
1655 /* Optionally let pins go into sleep states */ 1645 /* Optionally let pins go into sleep states */
1656 if (!IS_ERR(uap->pins_sleep)) { 1646 pinctrl_pm_select_sleep_state(port->dev);
1657 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1658 if (retval)
1659 dev_err(port->dev,
1660 "could not set pins to sleep state\n");
1661 }
1662
1663 1647
1664 if (uap->port.dev->platform_data) { 1648 if (uap->port.dev->platform_data) {
1665 struct amba_pl011_data *plat; 1649 struct amba_pl011_data *plat;
@@ -2012,12 +1996,7 @@ static int __init pl011_console_setup(struct console *co, char *options)
2012 return -ENODEV; 1996 return -ENODEV;
2013 1997
2014 /* Allow pins to be muxed in and configured */ 1998 /* Allow pins to be muxed in and configured */
2015 if (!IS_ERR(uap->pins_default)) { 1999 pinctrl_pm_select_default_state(uap->port.dev);
2016 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
2017 if (ret)
2018 dev_err(uap->port.dev,
2019 "could not set default pins\n");
2020 }
2021 2000
2022 ret = clk_prepare(uap->clk); 2001 ret = clk_prepare(uap->clk);
2023 if (ret) 2002 if (ret)
@@ -2131,21 +2110,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2131 goto out; 2110 goto out;
2132 } 2111 }
2133 2112
2134 uap->pinctrl = devm_pinctrl_get(&dev->dev);
2135 if (IS_ERR(uap->pinctrl)) {
2136 ret = PTR_ERR(uap->pinctrl);
2137 goto out;
2138 }
2139 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
2140 PINCTRL_STATE_DEFAULT);
2141 if (IS_ERR(uap->pins_default))
2142 dev_err(&dev->dev, "could not get default pinstate\n");
2143
2144 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
2145 PINCTRL_STATE_SLEEP);
2146 if (IS_ERR(uap->pins_sleep))
2147 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
2148
2149 uap->clk = devm_clk_get(&dev->dev, NULL); 2113 uap->clk = devm_clk_get(&dev->dev, NULL);
2150 if (IS_ERR(uap->clk)) { 2114 if (IS_ERR(uap->clk)) {
2151 ret = PTR_ERR(uap->clk); 2115 ret = PTR_ERR(uap->clk);
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
new file mode 100644
index 000000000000..cd5788be82ce
--- /dev/null
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -0,0 +1,32 @@
1/*
2 * Header providing constants for Rockchip pinctrl bindings.
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
19#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
20
21#define RK_GPIO0 0
22#define RK_GPIO1 1
23#define RK_GPIO2 2
24#define RK_GPIO3 3
25#define RK_GPIO4 4
26#define RK_GPIO6 6
27
28#define RK_FUNC_GPIO 0
29#define RK_FUNC_1 1
30#define RK_FUNC_2 2
31
32#endif
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 4aad3cea69ae..18eccefea06e 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -40,6 +40,25 @@ extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
40extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev); 40extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
41extern void devm_pinctrl_put(struct pinctrl *p); 41extern void devm_pinctrl_put(struct pinctrl *p);
42 42
43#ifdef CONFIG_PM
44extern int pinctrl_pm_select_default_state(struct device *dev);
45extern int pinctrl_pm_select_sleep_state(struct device *dev);
46extern int pinctrl_pm_select_idle_state(struct device *dev);
47#else
48static inline int pinctrl_pm_select_default_state(struct device *dev)
49{
50 return 0;
51}
52static inline int pinctrl_pm_select_sleep_state(struct device *dev)
53{
54 return 0;
55}
56static inline int pinctrl_pm_select_idle_state(struct device *dev)
57{
58 return 0;
59}
60#endif
61
43#else /* !CONFIG_PINCTRL */ 62#else /* !CONFIG_PINCTRL */
44 63
45static inline int pinctrl_request_gpio(unsigned gpio) 64static inline int pinctrl_request_gpio(unsigned gpio)
@@ -92,6 +111,21 @@ static inline void devm_pinctrl_put(struct pinctrl *p)
92{ 111{
93} 112}
94 113
114static inline int pinctrl_pm_select_default_state(struct device *dev)
115{
116 return 0;
117}
118
119static inline int pinctrl_pm_select_sleep_state(struct device *dev)
120{
121 return 0;
122}
123
124static inline int pinctrl_pm_select_idle_state(struct device *dev)
125{
126 return 0;
127}
128
95#endif /* CONFIG_PINCTRL */ 129#endif /* CONFIG_PINCTRL */
96 130
97static inline struct pinctrl * __must_check pinctrl_get_select( 131static inline struct pinctrl * __must_check pinctrl_get_select(
@@ -158,47 +192,4 @@ static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
158 return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); 192 return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
159} 193}
160 194
161#ifdef CONFIG_PINCONF
162
163extern int pin_config_get(const char *dev_name, const char *name,
164 unsigned long *config);
165extern int pin_config_set(const char *dev_name, const char *name,
166 unsigned long config);
167extern int pin_config_group_get(const char *dev_name,
168 const char *pin_group,
169 unsigned long *config);
170extern int pin_config_group_set(const char *dev_name,
171 const char *pin_group,
172 unsigned long config);
173
174#else
175
176static inline int pin_config_get(const char *dev_name, const char *name,
177 unsigned long *config)
178{
179 return 0;
180}
181
182static inline int pin_config_set(const char *dev_name, const char *name,
183 unsigned long config)
184{
185 return 0;
186}
187
188static inline int pin_config_group_get(const char *dev_name,
189 const char *pin_group,
190 unsigned long *config)
191{
192 return 0;
193}
194
195static inline int pin_config_group_set(const char *dev_name,
196 const char *pin_group,
197 unsigned long config)
198{
199 return 0;
200}
201
202#endif
203
204#endif /* __LINUX_PINCTRL_CONSUMER_H */ 195#endif /* __LINUX_PINCTRL_CONSUMER_H */
diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h
index 6e5f8a985ea7..281cb91ddcf5 100644
--- a/include/linux/pinctrl/devinfo.h
+++ b/include/linux/pinctrl/devinfo.h
@@ -28,6 +28,10 @@
28struct dev_pin_info { 28struct dev_pin_info {
29 struct pinctrl *p; 29 struct pinctrl *p;
30 struct pinctrl_state *default_state; 30 struct pinctrl_state *default_state;
31#ifdef CONFIG_PM
32 struct pinctrl_state *sleep_state;
33 struct pinctrl_state *idle_state;
34#endif
31}; 35};
32 36
33extern int pinctrl_bind_pins(struct device *dev); 37extern int pinctrl_bind_pins(struct device *dev);
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index 6aa238096622..bf7e989abcb5 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -29,12 +29,25 @@
29 * if for example some other pin is going to drive the signal connected 29 * if for example some other pin is going to drive the signal connected
30 * to it for a while. Pins used for input are usually always high 30 * to it for a while. Pins used for input are usually always high
31 * impedance. 31 * impedance.
32 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
33 * weakly drives the last value on a tristate bus, also known as a "bus
34 * holder", "bus keeper" or "repeater". This allows another device on the
35 * bus to change the value by driving the bus high or low and switching to
36 * tristate. The argument is ignored.
32 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high 37 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
33 * impedance to VDD). If the argument is != 0 pull-up is enabled, 38 * impedance to VDD). If the argument is != 0 pull-up is enabled,
34 * if it is 0, pull-up is disabled. 39 * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
35 * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high 40 * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
36 * impedance to GROUND). If the argument is != 0 pull-down is enabled, 41 * impedance to GROUND). If the argument is != 0 pull-down is enabled,
37 * if it is 0, pull-down is disabled. 42 * if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
43 * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based
44 * on embedded knowledge of the controller hardware, like current mux
45 * function. The pull direction and possibly strength too will normally
46 * be decided completely inside the hardware block and not be readable
47 * from the kernel side.
48 * If the argument is != 0 pull up/down is enabled, if it is 0, the
49 * configuration is ignored. The proper way to disable it is to use
50 * @PIN_CONFIG_BIAS_DISABLE.
38 * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and 51 * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
39 * low, this is the most typical case and is typically achieved with two 52 * low, this is the most typical case and is typically achieved with two
40 * active transistors on the output. Setting this config will enable 53 * active transistors on the output. Setting this config will enable
@@ -57,14 +70,14 @@
57 * setting pins to this mode. 70 * setting pins to this mode.
58 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, 71 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
59 * which means it will wait for signals to settle when reading inputs. The 72 * which means it will wait for signals to settle when reading inputs. The
60 * argument gives the debounce time on a custom format. Setting the 73 * argument gives the debounce time in usecs. Setting the
61 * argument to zero turns debouncing off. 74 * argument to zero turns debouncing off.
62 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power 75 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
63 * supplies, the argument to this parameter (on a custom format) tells 76 * supplies, the argument to this parameter (on a custom format) tells
64 * the driver which alternative power source to use. 77 * the driver which alternative power source to use.
65 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to 78 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
66 * this parameter (on a custom format) tells the driver which alternative 79 * this parameter (on a custom format) tells the driver which alternative
67 * slew rate to use. 80 * slew rate to use.
68 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power 81 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
69 * operation, if several modes of operation are supported these can be 82 * operation, if several modes of operation are supported these can be
70 * passed in the argument on a custom form, else just use argument 1 83 * passed in the argument on a custom form, else just use argument 1
@@ -78,8 +91,10 @@
78enum pin_config_param { 91enum pin_config_param {
79 PIN_CONFIG_BIAS_DISABLE, 92 PIN_CONFIG_BIAS_DISABLE,
80 PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 93 PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
94 PIN_CONFIG_BIAS_BUS_HOLD,
81 PIN_CONFIG_BIAS_PULL_UP, 95 PIN_CONFIG_BIAS_PULL_UP,
82 PIN_CONFIG_BIAS_PULL_DOWN, 96 PIN_CONFIG_BIAS_PULL_DOWN,
97 PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
83 PIN_CONFIG_DRIVE_PUSH_PULL, 98 PIN_CONFIG_DRIVE_PUSH_PULL,
84 PIN_CONFIG_DRIVE_OPEN_DRAIN, 99 PIN_CONFIG_DRIVE_OPEN_DRAIN,
85 PIN_CONFIG_DRIVE_OPEN_SOURCE, 100 PIN_CONFIG_DRIVE_OPEN_SOURCE,
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index 1ad4f31ef6b8..f6998692bdc9 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -30,7 +30,7 @@ struct seq_file;
30 * @pin_config_set: configure an individual pin 30 * @pin_config_set: configure an individual pin
31 * @pin_config_group_get: get configurations for an entire pin group 31 * @pin_config_group_get: get configurations for an entire pin group
32 * @pin_config_group_set: configure all pins in a group 32 * @pin_config_group_set: configure all pins in a group
33 * @pin_config_group_dbg_set: optional debugfs to modify a pin configuration 33 * @pin_config_dbg_parse_modify: optional debugfs to modify a pin configuration
34 * @pin_config_dbg_show: optional debugfs display hook that will provide 34 * @pin_config_dbg_show: optional debugfs display hook that will provide
35 * per-device info for a certain pin in debugfs 35 * per-device info for a certain pin in debugfs
36 * @pin_config_group_dbg_show: optional debugfs display hook that will provide 36 * @pin_config_group_dbg_show: optional debugfs display hook that will provide
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 2c2a9e8d8578..5979147d2bda 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -49,7 +49,8 @@ struct pinctrl_pin_desc {
49 * @name: a name for the chip in this range 49 * @name: a name for the chip in this range
50 * @id: an ID number for the chip in this range 50 * @id: an ID number for the chip in this range
51 * @base: base offset of the GPIO range 51 * @base: base offset of the GPIO range
52 * @pin_base: base pin number of the GPIO range 52 * @pin_base: base pin number of the GPIO range if pins == NULL
53 * @pins: enumeration of pins in GPIO range or NULL
53 * @npins: number of pins in the GPIO range, including the base number 54 * @npins: number of pins in the GPIO range, including the base number
54 * @gc: an optional pointer to a gpio_chip 55 * @gc: an optional pointer to a gpio_chip
55 */ 56 */
@@ -59,6 +60,7 @@ struct pinctrl_gpio_range {
59 unsigned int id; 60 unsigned int id;
60 unsigned int base; 61 unsigned int base;
61 unsigned int pin_base; 62 unsigned int pin_base;
63 unsigned const *pins;
62 unsigned int npins; 64 unsigned int npins;
63 struct gpio_chip *gc; 65 struct gpio_chip *gc;
64}; 66};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 00:57:17 -0500