diff options
author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-07-17 13:10:15 -0400 |
---|---|---|
committer | Michal Simek <michal.simek@xilinx.com> | 2013-07-26 08:14:41 -0400 |
commit | 3db9e86029349c2c84928b5a0f7c7cf324243b4f (patch) | |
tree | f1846c75949e77ff2770ab199649dfe775d60dfc | |
parent | b5f177ff305b3db63b5ea273e6471708790133f2 (diff) |
arm: zynq: slcr: Use read-modify-write for register writes
zynq_slcr_cpu_start/stop() ignored the current register state when
writing to a register. Fixing this by implementing proper
read-modify-write.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r-- | arch/arm/mach-zynq/slcr.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 44a4ab62e9a8..1836d5a34606 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c | |||
@@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void) | |||
61 | */ | 61 | */ |
62 | void zynq_slcr_cpu_start(int cpu) | 62 | void zynq_slcr_cpu_start(int cpu) |
63 | { | 63 | { |
64 | /* enable CPUn */ | 64 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
65 | writel(SLCR_A9_CPU_CLKSTOP << cpu, | 65 | reg &= ~(SLCR_A9_CPU_RST << cpu); |
66 | zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 66 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
67 | /* enable CLK for CPUn */ | 67 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); |
68 | writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 68 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
69 | } | 69 | } |
70 | 70 | ||
71 | /** | 71 | /** |
@@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) | |||
74 | */ | 74 | */ |
75 | void zynq_slcr_cpu_stop(int cpu) | 75 | void zynq_slcr_cpu_stop(int cpu) |
76 | { | 76 | { |
77 | /* stop CLK and reset CPUn */ | 77 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
78 | writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, | 78 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; |
79 | zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 79 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
80 | } | 80 | } |
81 | 81 | ||
82 | /** | 82 | /** |