clk: ux500: Register slimbus clock lookups for u8500

At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0aae92956844..e2c17d187d98 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -254,6 +254,7 @@ void u8500_clk_init(void)
 
         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
                                 BIT(8), 0);
+        clk_register_clkdev(clk, "apb_pclk", "slimbus0");
 
         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
                                 BIT(9), 0);
@@ -441,8 +442,8 @@ void u8500_clk_init(void)
         clk_register_clkdev(clk, NULL, "nmk-i2c.2");
 
         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
-                        U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
-        /* FIXME: Redefinition of BIT(3). */
+                        U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
+        clk_register_clkdev(clk, NULL, "slimbus0");
 
         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
                         U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);