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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-03-02 18:56:33 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-03-02 18:56:33 -0500
commit3d71769014c55e05b2342b6d9c1464f7fb383322 (patch)
treeb85909f3f949e070bbba86976f81966f180a837c
parentcd70469d084fde198dc07c1a31b8463562228a5a (diff)
parentc2df85ca31645ed3c68c56bd30a3673e034224f1 (diff)
Merge tag 'dwc3-for-v3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
usb: dwc3: changes for v3.4 merge window Here are the changes for v3.4 merge window. It includes a new glue layer for Samsung's Exynos platform, a simplification of memory management on DWC3 driver by using dev_xxx functions, a few optimizations to IRQ handling by dropping memcpy() and using bitshifts, a fix for TI's OMAP5430 TX Fifo Allocation, two fixes on USB2 test mode implementation (one on debugfs and one on ep0), and several minor changes such as whitespace cleanups, simplification of a few parts of the code, decreasing a long delay to something a bit saner, dropping a header which was included twice and so on. The highlight on this merge is the support for Samsung's Exynos platform, increasing the number of different users for this driver to three. Note that Samsung Exynos glue layer will only compile on platforms which provide implementation for the clk API for now. Once Samsung supports pm_runtime, that limitation can be dropped from the Makefile. Conflicts: drivers/usb/dwc3/gadget.c
Diffstat
-rw-r--r--drivers/usb/dwc3/Makefile13
-rw-r--r--drivers/usb/dwc3/core.c108
-rw-r--r--drivers/usb/dwc3/core.h198
-rw-r--r--drivers/usb/dwc3/debugfs.c214
-rw-r--r--drivers/usb/dwc3/dwc3-exynos.c151
-rw-r--r--drivers/usb/dwc3/dwc3-omap.c116
-rw-r--r--drivers/usb/dwc3/dwc3-pci.c52
-rw-r--r--drivers/usb/dwc3/ep0.c82
-rw-r--r--drivers/usb/dwc3/gadget.c371
-rw-r--r--drivers/usb/dwc3/gadget.h3
-rw-r--r--drivers/usb/dwc3/host.c2
-rw-r--r--include/linux/platform_data/dwc3-exynos.h24
12 files changed, 921 insertions, 413 deletions
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 900ae74357f1..d441fe4c180b 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -28,6 +28,19 @@ endif
28 28
29obj-$(CONFIG_USB_DWC3) += dwc3-omap.o 29obj-$(CONFIG_USB_DWC3) += dwc3-omap.o
30 30
31##
32# REVISIT Samsung Exynos platform needs the clk API which isn't
33# defined on all architectures. If we allow dwc3-exynos.c compile
34# always we will fail the linking phase on those architectures
35# which don't provide clk api implementation and that's unnaceptable.
36#
37# When Samsung's platform start supporting pm_runtime, this check
38# for HAVE_CLK should be removed.
39##
40ifneq ($(CONFIG_HAVE_CLK),)
41 obj-$(CONFIG_USB_DWC3) += dwc3-exynos.o
42endif
43
31ifneq ($(CONFIG_PCI),) 44ifneq ($(CONFIG_PCI),)
32 obj-$(CONFIG_USB_DWC3) += dwc3-pci.o 45 obj-$(CONFIG_USB_DWC3) += dwc3-pci.o
33endif 46endif
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7c9df630dbe4..fd6917b8d0d7 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -48,10 +48,10 @@
48#include <linux/list.h> 48#include <linux/list.h>
49#include <linux/delay.h> 49#include <linux/delay.h>
50#include <linux/dma-mapping.h> 50#include <linux/dma-mapping.h>
51#include <linux/of.h>
51 52
52#include <linux/usb/ch9.h> 53#include <linux/usb/ch9.h>
53#include <linux/usb/gadget.h> 54#include <linux/usb/gadget.h>
54#include <linux/module.h>
55 55
56#include "core.h" 56#include "core.h"
57#include "gadget.h" 57#include "gadget.h"
@@ -86,7 +86,7 @@ again:
86 id = -ENOMEM; 86 id = -ENOMEM;
87 } 87 }
88 88
89 return 0; 89 return id;
90} 90}
91EXPORT_SYMBOL_GPL(dwc3_get_device_id); 91EXPORT_SYMBOL_GPL(dwc3_get_device_id);
92 92
@@ -167,11 +167,11 @@ static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
167} 167}
168 168
169/** 169/**
170 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure 170 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
171 * @dwc: Pointer to our controller context structure 171 * @dwc: Pointer to our controller context structure
172 * @length: size of the event buffer 172 * @length: size of the event buffer
173 * 173 *
174 * Returns a pointer to the allocated event buffer structure on succes 174 * Returns a pointer to the allocated event buffer structure on success
175 * otherwise ERR_PTR(errno). 175 * otherwise ERR_PTR(errno).
176 */ 176 */
177static struct dwc3_event_buffer *__devinit 177static struct dwc3_event_buffer *__devinit
@@ -215,10 +215,10 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc)
215 215
216/** 216/**
217 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 217 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
218 * @dwc: Pointer to out controller context structure 218 * @dwc: pointer to our controller context structure
219 * @length: size of event buffer 219 * @length: size of event buffer
220 * 220 *
221 * Returns 0 on success otherwise negative errno. In error the case, dwc 221 * Returns 0 on success otherwise negative errno. In the error case, dwc
222 * may contain some buffers allocated but not all which were requested. 222 * may contain some buffers allocated but not all which were requested.
223 */ 223 */
224static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 224static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
@@ -251,7 +251,7 @@ static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
251 251
252/** 252/**
253 * dwc3_event_buffers_setup - setup our allocated event buffers 253 * dwc3_event_buffers_setup - setup our allocated event buffers
254 * @dwc: Pointer to out controller context structure 254 * @dwc: pointer to our controller context structure
255 * 255 *
256 * Returns 0 on success otherwise negative errno. 256 * Returns 0 on success otherwise negative errno.
257 */ 257 */
@@ -350,7 +350,7 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc)
350 dwc3_cache_hwparams(dwc); 350 dwc3_cache_hwparams(dwc);
351 351
352 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 352 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
353 reg &= ~DWC3_GCTL_SCALEDOWN(3); 353 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
354 reg &= ~DWC3_GCTL_DISSCRAMBLE; 354 reg &= ~DWC3_GCTL_DISSCRAMBLE;
355 355
356 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 356 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
@@ -363,9 +363,9 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc)
363 363
364 /* 364 /*
365 * WORKAROUND: DWC3 revisions <1.90a have a bug 365 * WORKAROUND: DWC3 revisions <1.90a have a bug
366 * when The device fails to connect at SuperSpeed 366 * where the device can fail to connect at SuperSpeed
367 * and falls back to high-speed mode which causes 367 * and falls back to high-speed mode which causes
368 * the device to enter in a Connect/Disconnect loop 368 * the device to enter a Connect/Disconnect loop
369 */ 369 */
370 if (dwc->revision < DWC3_REVISION_190A) 370 if (dwc->revision < DWC3_REVISION_190A)
371 reg |= DWC3_GCTL_U2RSTECN; 371 reg |= DWC3_GCTL_U2RSTECN;
@@ -404,8 +404,10 @@ static void dwc3_core_exit(struct dwc3 *dwc)
404 404
405static int __devinit dwc3_probe(struct platform_device *pdev) 405static int __devinit dwc3_probe(struct platform_device *pdev)
406{ 406{
407 struct device_node *node = pdev->dev.of_node;
407 struct resource *res; 408 struct resource *res;
408 struct dwc3 *dwc; 409 struct dwc3 *dwc;
410 struct device *dev = &pdev->dev;
409 411
410 int ret = -ENOMEM; 412 int ret = -ENOMEM;
411 int irq; 413 int irq;
@@ -415,39 +417,39 @@ static int __devinit dwc3_probe(struct platform_device *pdev)
415 417
416 u8 mode; 418 u8 mode;
417 419
418 mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 420 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
419 if (!mem) { 421 if (!mem) {
420 dev_err(&pdev->dev, "not enough memory\n"); 422 dev_err(dev, "not enough memory\n");
421 goto err0; 423 return -ENOMEM;
422 } 424 }
423 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 425 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
424 dwc->mem = mem; 426 dwc->mem = mem;
425 427
426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
427 if (!res) { 429 if (!res) {
428 dev_err(&pdev->dev, "missing resource\n"); 430 dev_err(dev, "missing resource\n");
429 goto err1; 431 return -ENODEV;
430 } 432 }
431 433
432 dwc->res = res; 434 dwc->res = res;
433 435
434 res = request_mem_region(res->start, resource_size(res), 436 res = devm_request_mem_region(dev, res->start, resource_size(res),
435 dev_name(&pdev->dev)); 437 dev_name(dev));
436 if (!res) { 438 if (!res) {
437 dev_err(&pdev->dev, "can't request mem region\n"); 439 dev_err(dev, "can't request mem region\n");
438 goto err1; 440 return -ENOMEM;
439 } 441 }
440 442
441 regs = ioremap(res->start, resource_size(res)); 443 regs = devm_ioremap(dev, res->start, resource_size(res));
442 if (!regs) { 444 if (!regs) {
443 dev_err(&pdev->dev, "ioremap failed\n"); 445 dev_err(dev, "ioremap failed\n");
444 goto err2; 446 return -ENOMEM;
445 } 447 }
446 448
447 irq = platform_get_irq(pdev, 0); 449 irq = platform_get_irq(pdev, 0);
448 if (irq < 0) { 450 if (irq < 0) {
449 dev_err(&pdev->dev, "missing IRQ\n"); 451 dev_err(dev, "missing IRQ\n");
450 goto err3; 452 return -ENODEV;
451 } 453 }
452 454
453 spin_lock_init(&dwc->lock); 455 spin_lock_init(&dwc->lock);
@@ -455,7 +457,7 @@ static int __devinit dwc3_probe(struct platform_device *pdev)
455 457
456 dwc->regs = regs; 458 dwc->regs = regs;
457 dwc->regs_size = resource_size(res); 459 dwc->regs_size = resource_size(res);
458 dwc->dev = &pdev->dev; 460 dwc->dev = dev;
459 dwc->irq = irq; 461 dwc->irq = irq;
460 462
461 if (!strncmp("super", maximum_speed, 5)) 463 if (!strncmp("super", maximum_speed, 5))
@@ -469,14 +471,17 @@ static int __devinit dwc3_probe(struct platform_device *pdev)
469 else 471 else
470 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; 472 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
471 473
472 pm_runtime_enable(&pdev->dev); 474 if (of_get_property(node, "tx-fifo-resize", NULL))
473 pm_runtime_get_sync(&pdev->dev); 475 dwc->needs_fifo_resize = true;
474 pm_runtime_forbid(&pdev->dev); 476
477 pm_runtime_enable(dev);
478 pm_runtime_get_sync(dev);
479 pm_runtime_forbid(dev);
475 480
476 ret = dwc3_core_init(dwc); 481 ret = dwc3_core_init(dwc);
477 if (ret) { 482 if (ret) {
478 dev_err(&pdev->dev, "failed to initialize core\n"); 483 dev_err(dev, "failed to initialize core\n");
479 goto err3; 484 return ret;
480 } 485 }
481 486
482 mode = DWC3_MODE(dwc->hwparams.hwparams0); 487 mode = DWC3_MODE(dwc->hwparams.hwparams0);
@@ -486,49 +491,49 @@ static int __devinit dwc3_probe(struct platform_device *pdev)
486 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 491 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
487 ret = dwc3_gadget_init(dwc); 492 ret = dwc3_gadget_init(dwc);
488 if (ret) { 493 if (ret) {
489 dev_err(&pdev->dev, "failed to initialize gadget\n"); 494 dev_err(dev, "failed to initialize gadget\n");
490 goto err4; 495 goto err1;
491 } 496 }
492 break; 497 break;
493 case DWC3_MODE_HOST: 498 case DWC3_MODE_HOST:
494 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 499 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
495 ret = dwc3_host_init(dwc); 500 ret = dwc3_host_init(dwc);
496 if (ret) { 501 if (ret) {
497 dev_err(&pdev->dev, "failed to initialize host\n"); 502 dev_err(dev, "failed to initialize host\n");
498 goto err4; 503 goto err1;
499 } 504 }
500 break; 505 break;
501 case DWC3_MODE_DRD: 506 case DWC3_MODE_DRD:
502 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 507 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
503 ret = dwc3_host_init(dwc); 508 ret = dwc3_host_init(dwc);
504 if (ret) { 509 if (ret) {
505 dev_err(&pdev->dev, "failed to initialize host\n"); 510 dev_err(dev, "failed to initialize host\n");
506 goto err4; 511 goto err1;
507 } 512 }
508 513
509 ret = dwc3_gadget_init(dwc); 514 ret = dwc3_gadget_init(dwc);
510 if (ret) { 515 if (ret) {
511 dev_err(&pdev->dev, "failed to initialize gadget\n"); 516 dev_err(dev, "failed to initialize gadget\n");
512 goto err4; 517 goto err1;
513 } 518 }
514 break; 519 break;
515 default: 520 default:
516 dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode); 521 dev_err(dev, "Unsupported mode of operation %d\n", mode);
517 goto err4; 522 goto err1;
518 } 523 }
519 dwc->mode = mode; 524 dwc->mode = mode;
520 525
521 ret = dwc3_debugfs_init(dwc); 526 ret = dwc3_debugfs_init(dwc);
522 if (ret) { 527 if (ret) {
523 dev_err(&pdev->dev, "failed to initialize debugfs\n"); 528 dev_err(dev, "failed to initialize debugfs\n");
524 goto err5; 529 goto err2;
525 } 530 }
526 531
527 pm_runtime_allow(&pdev->dev); 532 pm_runtime_allow(dev);
528 533
529 return 0; 534 return 0;
530 535
531err5: 536err2:
532 switch (mode) { 537 switch (mode) {
533 case DWC3_MODE_DEVICE: 538 case DWC3_MODE_DEVICE:
534 dwc3_gadget_exit(dwc); 539 dwc3_gadget_exit(dwc);
@@ -545,19 +550,9 @@ err5:
545 break; 550 break;
546 } 551 }
547 552
548err4:
549 dwc3_core_exit(dwc);
550
551err3:
552 iounmap(regs);
553
554err2:
555 release_mem_region(res->start, resource_size(res));
556
557err1: 553err1:
558 kfree(dwc->mem); 554 dwc3_core_exit(dwc);
559 555
560err0:
561 return ret; 556 return ret;
562} 557}
563 558
@@ -590,9 +585,6 @@ static int __devexit dwc3_remove(struct platform_device *pdev)
590 } 585 }
591 586
592 dwc3_core_exit(dwc); 587 dwc3_core_exit(dwc);
593 release_mem_region(res->start, resource_size(res));
594 iounmap(dwc->regs);
595 kfree(dwc->mem);
596 588
597 return 0; 589 return 0;
598} 590}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a72f42ffbbee..6c7945b4cad3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -145,22 +145,23 @@
145/* Bit fields */ 145/* Bit fields */
146 146
147/* Global Configuration Register */ 147/* Global Configuration Register */
148#define DWC3_GCTL_PWRDNSCALE(n) (n << 19) 148#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
149#define DWC3_GCTL_U2RSTECN (1 << 16) 149#define DWC3_GCTL_U2RSTECN (1 << 16)
150#define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6) 150#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
151#define DWC3_GCTL_CLK_BUS (0) 151#define DWC3_GCTL_CLK_BUS (0)
152#define DWC3_GCTL_CLK_PIPE (1) 152#define DWC3_GCTL_CLK_PIPE (1)
153#define DWC3_GCTL_CLK_PIPEHALF (2) 153#define DWC3_GCTL_CLK_PIPEHALF (2)
154#define DWC3_GCTL_CLK_MASK (3) 154#define DWC3_GCTL_CLK_MASK (3)
155 155
156#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 156#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
157#define DWC3_GCTL_PRTCAPDIR(n) (n << 12) 157#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
158#define DWC3_GCTL_PRTCAP_HOST 1 158#define DWC3_GCTL_PRTCAP_HOST 1
159#define DWC3_GCTL_PRTCAP_DEVICE 2 159#define DWC3_GCTL_PRTCAP_DEVICE 2
160#define DWC3_GCTL_PRTCAP_OTG 3 160#define DWC3_GCTL_PRTCAP_OTG 3
161 161
162#define DWC3_GCTL_CORESOFTRESET (1 << 11) 162#define DWC3_GCTL_CORESOFTRESET (1 << 11)
163#define DWC3_GCTL_SCALEDOWN(n) (n << 4) 163#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
164#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
164#define DWC3_GCTL_DISSCRAMBLE (1 << 3) 165#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
165#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 166#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
166 167
@@ -172,8 +173,12 @@
172#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 173#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
173#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 174#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
174 175
176/* Global TX Fifo Size Register */
177#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
178#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
179
175/* Global HWPARAMS1 Register */ 180/* Global HWPARAMS1 Register */
176#define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24) 181#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
177#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 182#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
178#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 183#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
179 184
@@ -198,6 +203,15 @@
198 203
199#define DWC3_DCTL_APPL1RES (1 << 23) 204#define DWC3_DCTL_APPL1RES (1 << 23)
200 205
206#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
207#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
208
209#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
210#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
211#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
212#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
213#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
214
201#define DWC3_DCTL_INITU2ENA (1 << 12) 215#define DWC3_DCTL_INITU2ENA (1 << 12)
202#define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 216#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
203#define DWC3_DCTL_INITU1ENA (1 << 10) 217#define DWC3_DCTL_INITU1ENA (1 << 10)
@@ -260,10 +274,10 @@
260 274
261/* Device Endpoint Command Register */ 275/* Device Endpoint Command Register */
262#define DWC3_DEPCMD_PARAM_SHIFT 16 276#define DWC3_DEPCMD_PARAM_SHIFT 16
263#define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT) 277#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
264#define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 278#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
265#define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) 279#define DWC3_DEPCMD_STATUS_MASK (0x0f << 12)
266#define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12) 280#define DWC3_DEPCMD_STATUS(x) (((x) & DWC3_DEPCMD_STATUS_MASK) >> 12)
267#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 281#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
268#define DWC3_DEPCMD_CMDACT (1 << 10) 282#define DWC3_DEPCMD_CMDACT (1 << 10)
269#define DWC3_DEPCMD_CMDIOC (1 << 8) 283#define DWC3_DEPCMD_CMDIOC (1 << 8)
@@ -288,7 +302,7 @@
288 302
289/* Structures */ 303/* Structures */
290 304
291struct dwc3_trb_hw; 305struct dwc3_trb;
292 306
293/** 307/**
294 * struct dwc3_event_buffer - Software event buffer representation 308 * struct dwc3_event_buffer - Software event buffer representation
@@ -343,7 +357,7 @@ struct dwc3_ep {
343 struct list_head request_list; 357 struct list_head request_list;
344 struct list_head req_queued; 358 struct list_head req_queued;
345 359
346 struct dwc3_trb_hw *trb_pool; 360 struct dwc3_trb *trb_pool;
347 dma_addr_t trb_pool_dma; 361 dma_addr_t trb_pool_dma;
348 u32 free_slot; 362 u32 free_slot;
349 u32 busy_slot; 363 u32 busy_slot;
@@ -418,102 +432,49 @@ enum dwc3_device_state {
418 DWC3_CONFIGURED_STATE, 432 DWC3_CONFIGURED_STATE,
419}; 433};
420 434
421/** 435/* TRB Length, PCM and Status */
422 * struct dwc3_trb - transfer request block 436#define DWC3_TRB_SIZE_MASK (0x00ffffff)
423 * @bpl: lower 32bit of the buffer 437#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
424 * @bph: higher 32bit of the buffer 438#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
425 * @length: buffer size (up to 16mb - 1) 439#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28))
426 * @pcm1: packet count m1 440
427 * @trbsts: trb status 441#define DWC3_TRBSTS_OK 0
428 * 0 = ok 442#define DWC3_TRBSTS_MISSED_ISOC 1
429 * 1 = missed isoc 443#define DWC3_TRBSTS_SETUP_PENDING 2
430 * 2 = setup pending 444
431 * @hwo: hardware owner of descriptor 445/* TRB Control */
432 * @lst: last trb 446#define DWC3_TRB_CTRL_HWO (1 << 0)
433 * @chn: chain buffers 447#define DWC3_TRB_CTRL_LST (1 << 1)
434 * @csp: continue on short packets (only supported on isoc eps) 448#define DWC3_TRB_CTRL_CHN (1 << 2)
435 * @trbctl: trb control 449#define DWC3_TRB_CTRL_CSP (1 << 3)
436 * 1 = normal 450#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
437 * 2 = control-setup 451#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
438 * 3 = control-status-2 452#define DWC3_TRB_CTRL_IOC (1 << 11)
439 * 4 = control-status-3 453#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
440 * 5 = control-data (first trb of data stage) 454
441 * 6 = isochronous-first (first trb of service interval) 455#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
442 * 7 = isochronous 456#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
443 * 8 = link trb 457#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
444 * others = reserved 458#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
445 * @isp_imi: interrupt on short packet / interrupt on missed isoc 459#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
446 * @ioc: interrupt on complete 460#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
447 * @sid_sofn: Stream ID / SOF Number 461#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
448 */ 462#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
449struct dwc3_trb {
450 u64 bplh;
451
452 union {
453 struct {
454 u32 length:24;
455 u32 pcm1:2;
456 u32 reserved27_26:2;
457 u32 trbsts:4;
458#define DWC3_TRB_STS_OKAY 0
459#define DWC3_TRB_STS_MISSED_ISOC 1
460#define DWC3_TRB_STS_SETUP_PENDING 2
461 };
462 u32 len_pcm;
463 };
464
465 union {
466 struct {
467 u32 hwo:1;
468 u32 lst:1;
469 u32 chn:1;
470 u32 csp:1;
471 u32 trbctl:6;
472 u32 isp_imi:1;
473 u32 ioc:1;
474 u32 reserved13_12:2;
475 u32 sid_sofn:16;
476 u32 reserved31_30:2;
477 };
478 u32 control;
479 };
480} __packed;
481 463
482/** 464/**
483 * struct dwc3_trb_hw - transfer request block (hw format) 465 * struct dwc3_trb - transfer request block (hw format)
484 * @bpl: DW0-3 466 * @bpl: DW0-3
485 * @bph: DW4-7 467 * @bph: DW4-7
486 * @size: DW8-B 468 * @size: DW8-B
487 * @trl: DWC-F 469 * @trl: DWC-F
488 */ 470 */
489struct dwc3_trb_hw { 471struct dwc3_trb {
490 __le32 bpl; 472 u32 bpl;
491 __le32 bph; 473 u32 bph;
492 __le32 size; 474 u32 size;
493 __le32 ctrl; 475 u32 ctrl;
494} __packed; 476} __packed;
495 477
496static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw)
497{
498 hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh));
499 hw->bph = cpu_to_le32(upper_32_bits(nat->bplh));
500 hw->size = cpu_to_le32p(&nat->len_pcm);
501 /* HWO is written last */
502 hw->ctrl = cpu_to_le32p(&nat->control);
503}
504
505static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat)
506{
507 u64 bplh;
508
509 bplh = le32_to_cpup(&hw->bpl);
510 bplh |= (u64) le32_to_cpup(&hw->bph) << 32;
511 nat->bplh = bplh;
512
513 nat->len_pcm = le32_to_cpup(&hw->size);
514 nat->control = le32_to_cpup(&hw->ctrl);
515}
516
517/** 478/**
518 * dwc3_hwparams - copy of HWPARAMS registers 479 * dwc3_hwparams - copy of HWPARAMS registers
519 * @hwparams0 - GHWPARAMS0 480 * @hwparams0 - GHWPARAMS0
@@ -546,8 +507,13 @@ struct dwc3_hwparams {
546#define DWC3_MODE_DRD 2 507#define DWC3_MODE_DRD 2
547#define DWC3_MODE_HUB 3 508#define DWC3_MODE_HUB 3
548 509
510#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
511
549/* HWPARAMS1 */ 512/* HWPARAMS1 */
550#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 513#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
514
515/* HWPARAMS7 */
516#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
551 517
552struct dwc3_request { 518struct dwc3_request {
553 struct usb_request request; 519 struct usb_request request;
@@ -555,7 +521,7 @@ struct dwc3_request {
555 struct dwc3_ep *dep; 521 struct dwc3_ep *dep;
556 522
557 u8 epnum; 523 u8 epnum;
558 struct dwc3_trb_hw *trb; 524 struct dwc3_trb *trb;
559 dma_addr_t trb_dma; 525 dma_addr_t trb_dma;
560 526
561 unsigned direction:1; 527 unsigned direction:1;
@@ -593,6 +559,8 @@ struct dwc3_request {
593 * @ep0_expect_in: true when we expect a DATA IN transfer 559 * @ep0_expect_in: true when we expect a DATA IN transfer
594 * @start_config_issued: true when StartConfig command has been issued 560 * @start_config_issued: true when StartConfig command has been issued
595 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 561 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
562 * @needs_fifo_resize: not all users might want fifo resizing, flag it
563 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
596 * @ep0_next_event: hold the next expected event 564 * @ep0_next_event: hold the next expected event
597 * @ep0state: state of endpoint zero 565 * @ep0state: state of endpoint zero
598 * @link_state: link state 566 * @link_state: link state
@@ -603,7 +571,7 @@ struct dwc3_request {
603 */ 571 */
604struct dwc3 { 572struct dwc3 {
605 struct usb_ctrlrequest *ctrl_req; 573 struct usb_ctrlrequest *ctrl_req;
606 struct dwc3_trb_hw *ep0_trb; 574 struct dwc3_trb *ep0_trb;
607 void *ep0_bounce; 575 void *ep0_bounce;
608 u8 *setup_buf; 576 u8 *setup_buf;
609 dma_addr_t ctrl_req_addr; 577 dma_addr_t ctrl_req_addr;
@@ -649,6 +617,8 @@ struct dwc3 {
649 unsigned start_config_issued:1; 617 unsigned start_config_issued:1;
650 unsigned setup_packet_pending:1; 618 unsigned setup_packet_pending:1;
651 unsigned delayed_status:1; 619 unsigned delayed_status:1;
620 unsigned needs_fifo_resize:1;
621 unsigned resize_fifos:1;
652 622
653 enum dwc3_ep0_next ep0_next_event; 623 enum dwc3_ep0_next ep0_next_event;
654 enum dwc3_ep0_state ep0state; 624 enum dwc3_ep0_state ep0state;
@@ -660,23 +630,13 @@ struct dwc3 {
660 630
661 struct dwc3_hwparams hwparams; 631 struct dwc3_hwparams hwparams;
662 struct dentry *root; 632 struct dentry *root;
633
634 u8 test_mode;
635 u8 test_mode_nr;
663}; 636};
664 637
665/* -------------------------------------------------------------------------- */ 638/* -------------------------------------------------------------------------- */
666 639
667#define DWC3_TRBSTS_OK 0
668#define DWC3_TRBSTS_MISSED_ISOC 1
669#define DWC3_TRBSTS_SETUP_PENDING 2
670
671#define DWC3_TRBCTL_NORMAL 1
672#define DWC3_TRBCTL_CONTROL_SETUP 2
673#define DWC3_TRBCTL_CONTROL_STATUS2 3
674#define DWC3_TRBCTL_CONTROL_STATUS3 4
675#define DWC3_TRBCTL_CONTROL_DATA 5
676#define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6
677#define DWC3_TRBCTL_ISOCHRONOUS 7
678#define DWC3_TRBCTL_LINK_TRB 8
679
680/* -------------------------------------------------------------------------- */ 640/* -------------------------------------------------------------------------- */
681 641
682struct dwc3_event_type { 642struct dwc3_event_type {
@@ -717,9 +677,14 @@ struct dwc3_event_depevt {
717 u32 endpoint_event:4; 677 u32 endpoint_event:4;
718 u32 reserved11_10:2; 678 u32 reserved11_10:2;
719 u32 status:4; 679 u32 status:4;
720#define DEPEVT_STATUS_BUSERR (1 << 0) 680
721#define DEPEVT_STATUS_SHORT (1 << 1) 681/* Within XferNotReady */
722#define DEPEVT_STATUS_IOC (1 << 2) 682#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
683
684/* Within XferComplete */
685#define DEPEVT_STATUS_BUSERR (1 << 0)
686#define DEPEVT_STATUS_SHORT (1 << 1)
687#define DEPEVT_STATUS_IOC (1 << 2)
723#define DEPEVT_STATUS_LST (1 << 3) 688#define DEPEVT_STATUS_LST (1 << 3)
724 689
725/* Stream event only */ 690/* Stream event only */
@@ -805,6 +770,7 @@ union dwc3_event {
805 770
806/* prototypes */ 771/* prototypes */
807void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 772void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
773int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
808 774
809int dwc3_host_init(struct dwc3 *dwc); 775int dwc3_host_init(struct dwc3 *dwc);
810void dwc3_host_exit(struct dwc3 *dwc); 776void dwc3_host_exit(struct dwc3 *dwc);
diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
index 433c97c15fc5..d4a30f118724 100644
--- a/drivers/usb/dwc3/debugfs.c
+++ b/drivers/usb/dwc3/debugfs.c
@@ -46,6 +46,8 @@
46#include <linux/delay.h> 46#include <linux/delay.h>
47#include <linux/uaccess.h> 47#include <linux/uaccess.h>
48 48
49#include <linux/usb/ch9.h>
50
49#include "core.h" 51#include "core.h"
50#include "gadget.h" 52#include "gadget.h"
51#include "io.h" 53#include "io.h"
@@ -464,6 +466,192 @@ static const struct file_operations dwc3_mode_fops = {
464 .release = single_release, 466 .release = single_release,
465}; 467};
466 468
469static int dwc3_testmode_show(struct seq_file *s, void *unused)
470{
471 struct dwc3 *dwc = s->private;
472 unsigned long flags;
473 u32 reg;
474
475 spin_lock_irqsave(&dwc->lock, flags);
476 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
477 reg &= DWC3_DCTL_TSTCTRL_MASK;
478 reg >>= 1;
479 spin_unlock_irqrestore(&dwc->lock, flags);
480
481 switch (reg) {
482 case 0:
483 seq_printf(s, "no test\n");
484 break;
485 case TEST_J:
486 seq_printf(s, "test_j\n");
487 break;
488 case TEST_K:
489 seq_printf(s, "test_k\n");
490 break;
491 case TEST_SE0_NAK:
492 seq_printf(s, "test_se0_nak\n");
493 break;
494 case TEST_PACKET:
495 seq_printf(s, "test_packet\n");
496 break;
497 case TEST_FORCE_EN:
498 seq_printf(s, "test_force_enable\n");
499 break;
500 default:
501 seq_printf(s, "UNKNOWN %d\n", reg);
502 }
503
504 return 0;
505}
506
507static int dwc3_testmode_open(struct inode *inode, struct file *file)
508{
509 return single_open(file, dwc3_testmode_show, inode->i_private);
510}
511
512static ssize_t dwc3_testmode_write(struct file *file,
513 const char __user *ubuf, size_t count, loff_t *ppos)
514{
515 struct seq_file *s = file->private_data;
516 struct dwc3 *dwc = s->private;
517 unsigned long flags;
518 u32 testmode = 0;
519 char buf[32];
520
521 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
522 return -EFAULT;
523
524 if (!strncmp(buf, "test_j", 6))
525 testmode = TEST_J;
526 else if (!strncmp(buf, "test_k", 6))
527 testmode = TEST_K;
528 else if (!strncmp(buf, "test_se0_nak", 12))
529 testmode = TEST_SE0_NAK;
530 else if (!strncmp(buf, "test_packet", 11))
531 testmode = TEST_PACKET;
532 else if (!strncmp(buf, "test_force_enable", 17))
533 testmode = TEST_FORCE_EN;
534 else
535 testmode = 0;
536
537 spin_lock_irqsave(&dwc->lock, flags);
538 dwc3_gadget_set_test_mode(dwc, testmode);
539 spin_unlock_irqrestore(&dwc->lock, flags);
540
541 return count;
542}
543
544static const struct file_operations dwc3_testmode_fops = {
545 .open = dwc3_testmode_open,
546 .write = dwc3_testmode_write,
547 .read = seq_read,
548 .llseek = seq_lseek,
549 .release = single_release,
550};
551
552static int dwc3_link_state_show(struct seq_file *s, void *unused)
553{
554 struct dwc3 *dwc = s->private;
555 unsigned long flags;
556 enum dwc3_link_state state;
557 u32 reg;
558
559 spin_lock_irqsave(&dwc->lock, flags);
560 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
561 state = DWC3_DSTS_USBLNKST(reg);
562 spin_unlock_irqrestore(&dwc->lock, flags);
563
564 switch (state) {
565 case DWC3_LINK_STATE_U0:
566 seq_printf(s, "U0\n");
567 break;
568 case DWC3_LINK_STATE_U1:
569 seq_printf(s, "U1\n");
570 break;
571 case DWC3_LINK_STATE_U2:
572 seq_printf(s, "U2\n");
573 break;
574 case DWC3_LINK_STATE_U3:
575 seq_printf(s, "U3\n");
576 break;
577 case DWC3_LINK_STATE_SS_DIS:
578 seq_printf(s, "SS.Disabled\n");
579 break;
580 case DWC3_LINK_STATE_RX_DET:
581 seq_printf(s, "Rx.Detect\n");
582 break;
583 case DWC3_LINK_STATE_SS_INACT:
584 seq_printf(s, "SS.Inactive\n");
585 break;
586 case DWC3_LINK_STATE_POLL:
587 seq_printf(s, "Poll\n");
588 break;
589 case DWC3_LINK_STATE_RECOV:
590 seq_printf(s, "Recovery\n");
591 break;
592 case DWC3_LINK_STATE_HRESET:
593 seq_printf(s, "HRESET\n");
594 break;
595 case DWC3_LINK_STATE_CMPLY:
596 seq_printf(s, "Compliance\n");
597 break;
598 case DWC3_LINK_STATE_LPBK:
599 seq_printf(s, "Loopback\n");
600 break;
601 default:
602 seq_printf(s, "UNKNOWN %d\n", reg);
603 }
604
605 return 0;
606}
607
608static int dwc3_link_state_open(struct inode *inode, struct file *file)
609{
610 return single_open(file, dwc3_link_state_show, inode->i_private);
611}
612
613static ssize_t dwc3_link_state_write(struct file *file,
614 const char __user *ubuf, size_t count, loff_t *ppos)
615{
616 struct seq_file *s = file->private_data;
617 struct dwc3 *dwc = s->private;
618 unsigned long flags;
619 enum dwc3_link_state state = 0;
620 char buf[32];
621
622 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
623 return -EFAULT;
624
625 if (!strncmp(buf, "SS.Disabled", 11))
626 state = DWC3_LINK_STATE_SS_DIS;
627 else if (!strncmp(buf, "Rx.Detect", 9))
628 state = DWC3_LINK_STATE_RX_DET;
629 else if (!strncmp(buf, "SS.Inactive", 11))
630 state = DWC3_LINK_STATE_SS_INACT;
631 else if (!strncmp(buf, "Recovery", 8))
632 state = DWC3_LINK_STATE_RECOV;
633 else if (!strncmp(buf, "Compliance", 10))
634 state = DWC3_LINK_STATE_CMPLY;
635 else if (!strncmp(buf, "Loopback", 8))
636 state = DWC3_LINK_STATE_LPBK;
637 else
638 return -EINVAL;
639
640 spin_lock_irqsave(&dwc->lock, flags);
641 dwc3_gadget_set_link_state(dwc, state);
642 spin_unlock_irqrestore(&dwc->lock, flags);
643
644 return count;
645}
646
647static const struct file_operations dwc3_link_state_fops = {
648 .open = dwc3_link_state_open,
649 .write = dwc3_link_state_write,
650 .read = seq_read,
651 .llseek = seq_lseek,
652 .release = single_release,
653};
654
467int __devinit dwc3_debugfs_init(struct dwc3 *dwc) 655int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
468{ 656{
469 struct dentry *root; 657 struct dentry *root;
@@ -471,8 +659,8 @@ int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
471 int ret; 659 int ret;
472 660
473 root = debugfs_create_dir(dev_name(dwc->dev), NULL); 661 root = debugfs_create_dir(dev_name(dwc->dev), NULL);
474 if (IS_ERR(root)) { 662 if (!root) {
475 ret = PTR_ERR(root); 663 ret = -ENOMEM;
476 goto err0; 664 goto err0;
477 } 665 }
478 666
@@ -480,15 +668,29 @@ int __devinit dwc3_debugfs_init(struct dwc3 *dwc)
480 668
481 file = debugfs_create_file("regdump", S_IRUGO, root, dwc, 669 file = debugfs_create_file("regdump", S_IRUGO, root, dwc,
482 &dwc3_regdump_fops); 670 &dwc3_regdump_fops);
483 if (IS_ERR(file)) { 671 if (!file) {
484 ret = PTR_ERR(file); 672 ret = -ENOMEM;
485 goto err1; 673 goto err1;
486 } 674 }
487 675
488 file = debugfs_create_file("mode", S_IRUGO | S_IWUSR, root, 676 file = debugfs_create_file("mode", S_IRUGO | S_IWUSR, root,
489 dwc, &dwc3_mode_fops); 677 dwc, &dwc3_mode_fops);
490 if (IS_ERR(file)) { 678 if (!file) {
491 ret = PTR_ERR(file); 679 ret = -ENOMEM;
680 goto err1;
681 }
682
683 file = debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root,
684 dwc, &dwc3_testmode_fops);
685 if (!file) {
686 ret = -ENOMEM;
687 goto err1;
688 }
689
690 file = debugfs_create_file("link_state", S_IRUGO | S_IWUSR, root,
691 dwc, &dwc3_link_state_fops);
692 if (!file) {
693 ret = -ENOMEM;
492 goto err1; 694 goto err1;
493 } 695 }
494 696
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
new file mode 100644
index 000000000000..d19030198086
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -0,0 +1,151 @@
1/**
2 * dwc3-exynos.c - Samsung EXYNOS DWC3 Specific Glue layer
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/platform_data/dwc3-exynos.h>
20#include <linux/dma-mapping.h>
21#include <linux/module.h>
22#include <linux/clk.h>
23
24#include "core.h"
25
26struct dwc3_exynos {
27 struct platform_device *dwc3;
28 struct device *dev;
29
30 struct clk *clk;
31};
32
33static int __devinit dwc3_exynos_probe(struct platform_device *pdev)
34{
35 struct dwc3_exynos_data *pdata = pdev->dev.platform_data;
36 struct platform_device *dwc3;
37 struct dwc3_exynos *exynos;
38 struct clk *clk;
39
40 int devid;
41 int ret = -ENOMEM;
42
43 exynos = kzalloc(sizeof(*exynos), GFP_KERNEL);
44 if (!exynos) {
45 dev_err(&pdev->dev, "not enough memory\n");
46 goto err0;
47 }
48
49 platform_set_drvdata(pdev, exynos);
50
51 devid = dwc3_get_device_id();
52 if (devid < 0)
53 goto err1;
54
55 dwc3 = platform_device_alloc("dwc3", devid);
56 if (!dwc3) {
57 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
58 goto err2;
59 }
60
61 clk = clk_get(&pdev->dev, "usbdrd30");
62 if (IS_ERR(clk)) {
63 dev_err(&pdev->dev, "couldn't get clock\n");
64 ret = -EINVAL;
65 goto err3;
66 }
67
68 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
69
70 dwc3->dev.parent = &pdev->dev;
71 dwc3->dev.dma_mask = pdev->dev.dma_mask;
72 dwc3->dev.dma_parms = pdev->dev.dma_parms;
73 exynos->dwc3 = dwc3;
74 exynos->dev = &pdev->dev;
75 exynos->clk = clk;
76
77 clk_enable(exynos->clk);
78
79 /* PHY initialization */
80 if (!pdata) {
81 dev_dbg(&pdev->dev, "missing platform data\n");
82 } else {
83 if (pdata->phy_init)
84 pdata->phy_init(pdev, pdata->phy_type);
85 }
86
87 ret = platform_device_add_resources(dwc3, pdev->resource,
88 pdev->num_resources);
89 if (ret) {
90 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
91 goto err4;
92 }
93
94 ret = platform_device_add(dwc3);
95 if (ret) {
96 dev_err(&pdev->dev, "failed to register dwc3 device\n");
97 goto err4;
98 }
99
100 return 0;
101
102err4:
103 if (pdata && pdata->phy_exit)
104 pdata->phy_exit(pdev, pdata->phy_type);
105
106 clk_disable(clk);
107 clk_put(clk);
108err3:
109 platform_device_put(dwc3);
110err2:
111 dwc3_put_device_id(devid);
112err1:
113 kfree(exynos);
114err0:
115 return ret;
116}
117
118static int __devexit dwc3_exynos_remove(struct platform_device *pdev)
119{
120 struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
121 struct dwc3_exynos_data *pdata = pdev->dev.platform_data;
122
123 platform_device_unregister(exynos->dwc3);
124
125 dwc3_put_device_id(exynos->dwc3->id);
126
127 if (pdata && pdata->phy_exit)
128 pdata->phy_exit(pdev, pdata->phy_type);
129
130 clk_disable(exynos->clk);
131 clk_put(exynos->clk);
132
133 kfree(exynos);
134
135 return 0;
136}
137
138static struct platform_driver dwc3_exynos_driver = {
139 .probe = dwc3_exynos_probe,
140 .remove = __devexit_p(dwc3_exynos_remove),
141 .driver = {
142 .name = "exynos-dwc3",
143 },
144};
145
146module_platform_driver(dwc3_exynos_driver);
147
148MODULE_ALIAS("platform:exynos-dwc3");
149MODULE_AUTHOR("Anton Tikhomirov <av.tikhomirov@samsung.com>");
150MODULE_LICENSE("GPL");
151MODULE_DESCRIPTION("DesignWare USB3 EXYNOS Glue Layer");
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 3274ac8f1200..d7d9c0ec9515 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -46,7 +46,7 @@
46#include <linux/dma-mapping.h> 46#include <linux/dma-mapping.h>
47#include <linux/ioport.h> 47#include <linux/ioport.h>
48#include <linux/io.h> 48#include <linux/io.h>
49#include <linux/module.h> 49#include <linux/of.h>
50 50
51#include "core.h" 51#include "core.h"
52#include "io.h" 52#include "io.h"
@@ -197,91 +197,99 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
197static int __devinit dwc3_omap_probe(struct platform_device *pdev) 197static int __devinit dwc3_omap_probe(struct platform_device *pdev)
198{ 198{
199 struct dwc3_omap_data *pdata = pdev->dev.platform_data; 199 struct dwc3_omap_data *pdata = pdev->dev.platform_data;
200 struct device_node *node = pdev->dev.of_node;
201
200 struct platform_device *dwc3; 202 struct platform_device *dwc3;
201 struct dwc3_omap *omap; 203 struct dwc3_omap *omap;
202 struct resource *res; 204 struct resource *res;
205 struct device *dev = &pdev->dev;
203 206
204 int devid; 207 int devid;
208 int size;
205 int ret = -ENOMEM; 209 int ret = -ENOMEM;
206 int irq; 210 int irq;
207 211
212 const u32 *utmi_mode;
208 u32 reg; 213 u32 reg;
209 214
210 void __iomem *base; 215 void __iomem *base;
211 void *context; 216 void *context;
212 217
213 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 218 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
214 if (!omap) { 219 if (!omap) {
215 dev_err(&pdev->dev, "not enough memory\n"); 220 dev_err(dev, "not enough memory\n");
216 goto err0; 221 return -ENOMEM;
217 } 222 }
218 223
219 platform_set_drvdata(pdev, omap); 224 platform_set_drvdata(pdev, omap);
220 225
221 irq = platform_get_irq(pdev, 1); 226 irq = platform_get_irq(pdev, 1);
222 if (irq < 0) { 227 if (irq < 0) {
223 dev_err(&pdev->dev, "missing IRQ resource\n"); 228 dev_err(dev, "missing IRQ resource\n");
224 ret = -EINVAL; 229 return -EINVAL;
225 goto err1;
226 } 230 }
227 231
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 232 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
229 if (!res) { 233 if (!res) {
230 dev_err(&pdev->dev, "missing memory base resource\n"); 234 dev_err(dev, "missing memory base resource\n");
231 ret = -EINVAL; 235 return -EINVAL;
232 goto err1;
233 } 236 }
234 237
235 base = ioremap_nocache(res->start, resource_size(res)); 238 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
236 if (!base) { 239 if (!base) {
237 dev_err(&pdev->dev, "ioremap failed\n"); 240 dev_err(dev, "ioremap failed\n");
238 goto err1; 241 return -ENOMEM;
239 } 242 }
240 243
241 devid = dwc3_get_device_id(); 244 devid = dwc3_get_device_id();
242 if (devid < 0) 245 if (devid < 0)
243 goto err2; 246 return -ENODEV;
244 247
245 dwc3 = platform_device_alloc("dwc3", devid); 248 dwc3 = platform_device_alloc("dwc3", devid);
246 if (!dwc3) { 249 if (!dwc3) {
247 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n"); 250 dev_err(dev, "couldn't allocate dwc3 device\n");
248 goto err3; 251 goto err1;
249 } 252 }
250 253
251 context = kzalloc(resource_size(res), GFP_KERNEL); 254 context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
252 if (!context) { 255 if (!context) {
253 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n"); 256 dev_err(dev, "couldn't allocate dwc3 context memory\n");
254 goto err4; 257 goto err2;
255 } 258 }
256 259
257 spin_lock_init(&omap->lock); 260 spin_lock_init(&omap->lock);
258 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask); 261 dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
259 262
260 dwc3->dev.parent = &pdev->dev; 263 dwc3->dev.parent = dev;
261 dwc3->dev.dma_mask = pdev->dev.dma_mask; 264 dwc3->dev.dma_mask = dev->dma_mask;
262 dwc3->dev.dma_parms = pdev->dev.dma_parms; 265 dwc3->dev.dma_parms = dev->dma_parms;
263 omap->resource_size = resource_size(res); 266 omap->resource_size = resource_size(res);
264 omap->context = context; 267 omap->context = context;
265 omap->dev = &pdev->dev; 268 omap->dev = dev;
266 omap->irq = irq; 269 omap->irq = irq;
267 omap->base = base; 270 omap->base = base;
268 omap->dwc3 = dwc3; 271 omap->dwc3 = dwc3;
269 272
270 reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); 273 reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
271 274
272 if (!pdata) { 275 utmi_mode = of_get_property(node, "utmi-mode", &size);
273 dev_dbg(&pdev->dev, "missing platform data\n"); 276 if (utmi_mode && size == sizeof(*utmi_mode)) {
277 reg |= *utmi_mode;
274 } else { 278 } else {
275 switch (pdata->utmi_mode) { 279 if (!pdata) {
276 case DWC3_OMAP_UTMI_MODE_SW: 280 dev_dbg(dev, "missing platform data\n");
277 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 281 } else {
278 break; 282 switch (pdata->utmi_mode) {
279 case DWC3_OMAP_UTMI_MODE_HW: 283 case DWC3_OMAP_UTMI_MODE_SW:
280 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 284 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
281 break; 285 break;
282 default: 286 case DWC3_OMAP_UTMI_MODE_HW:
283 dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n", 287 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
284 pdata->utmi_mode); 288 break;
289 default:
290 dev_dbg(dev, "UNKNOWN utmi mode %d\n",
291 pdata->utmi_mode);
292 }
285 } 293 }
286 } 294 }
287 295
@@ -300,12 +308,12 @@ static int __devinit dwc3_omap_probe(struct platform_device *pdev)
300 308
301 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg); 309 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
302 310
303 ret = request_irq(omap->irq, dwc3_omap_interrupt, 0, 311 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
304 "dwc3-omap", omap); 312 "dwc3-omap", omap);
305 if (ret) { 313 if (ret) {
306 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n", 314 dev_err(dev, "failed to request IRQ #%d --> %d\n",
307 omap->irq, ret); 315 omap->irq, ret);
308 goto err5; 316 goto err2;
309 } 317 }
310 318
311 /* enable all IRQs */ 319 /* enable all IRQs */
@@ -327,37 +335,24 @@ static int __devinit dwc3_omap_probe(struct platform_device *pdev)
327 ret = platform_device_add_resources(dwc3, pdev->resource, 335 ret = platform_device_add_resources(dwc3, pdev->resource,
328 pdev->num_resources); 336 pdev->num_resources);
329 if (ret) { 337 if (ret) {
330 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n"); 338 dev_err(dev, "couldn't add resources to dwc3 device\n");
331 goto err6; 339 goto err2;
332 } 340 }
333 341
334 ret = platform_device_add(dwc3); 342 ret = platform_device_add(dwc3);
335 if (ret) { 343 if (ret) {
336 dev_err(&pdev->dev, "failed to register dwc3 device\n"); 344 dev_err(dev, "failed to register dwc3 device\n");
337 goto err6; 345 goto err2;
338 } 346 }
339 347
340 return 0; 348 return 0;
341 349
342err6:
343 free_irq(omap->irq, omap);
344
345err5:
346 kfree(omap->context);
347
348err4:
349 platform_device_put(dwc3);
350
351err3:
352 dwc3_put_device_id(devid);
353
354err2: 350err2:
355 iounmap(base); 351 platform_device_put(dwc3);
356 352
357err1: 353err1:
358 kfree(omap); 354 dwc3_put_device_id(devid);
359 355
360err0:
361 return ret; 356 return ret;
362} 357}
363 358
@@ -368,11 +363,6 @@ static int __devexit dwc3_omap_remove(struct platform_device *pdev)
368 platform_device_unregister(omap->dwc3); 363 platform_device_unregister(omap->dwc3);
369 364
370 dwc3_put_device_id(omap->dwc3->id); 365 dwc3_put_device_id(omap->dwc3->id);
371 free_irq(omap->irq, omap);
372 iounmap(omap->base);
373
374 kfree(omap->context);
375 kfree(omap);
376 366
377 return 0; 367 return 0;
378} 368}
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 64e1f7c67b08..dcc64791b4e1 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -61,32 +61,35 @@ static int __devinit dwc3_pci_probe(struct pci_dev *pci,
61 struct dwc3_pci *glue; 61 struct dwc3_pci *glue;
62 int ret = -ENOMEM; 62 int ret = -ENOMEM;
63 int devid; 63 int devid;
64 struct device *dev = &pci->dev;
64 65
65 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 66 glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
66 if (!glue) { 67 if (!glue) {
67 dev_err(&pci->dev, "not enough memory\n"); 68 dev_err(dev, "not enough memory\n");
68 goto err0; 69 return -ENOMEM;
69 } 70 }
70 71
71 glue->dev = &pci->dev; 72 glue->dev = dev;
72 73
73 ret = pci_enable_device(pci); 74 ret = pci_enable_device(pci);
74 if (ret) { 75 if (ret) {
75 dev_err(&pci->dev, "failed to enable pci device\n"); 76 dev_err(dev, "failed to enable pci device\n");
76 goto err1; 77 return -ENODEV;
77 } 78 }
78 79
79 pci_set_power_state(pci, PCI_D0); 80 pci_set_power_state(pci, PCI_D0);
80 pci_set_master(pci); 81 pci_set_master(pci);
81 82
82 devid = dwc3_get_device_id(); 83 devid = dwc3_get_device_id();
83 if (devid < 0) 84 if (devid < 0) {
84 goto err2; 85 ret = -ENOMEM;
86 goto err1;
87 }
85 88
86 dwc3 = platform_device_alloc("dwc3", devid); 89 dwc3 = platform_device_alloc("dwc3", devid);
87 if (!dwc3) { 90 if (!dwc3) {
88 dev_err(&pci->dev, "couldn't allocate dwc3 device\n"); 91 dev_err(dev, "couldn't allocate dwc3 device\n");
89 goto err3; 92 goto err1;
90 } 93 }
91 94
92 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 95 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
@@ -102,41 +105,37 @@ static int __devinit dwc3_pci_probe(struct pci_dev *pci,
102 105
103 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res)); 106 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
104 if (ret) { 107 if (ret) {
105 dev_err(&pci->dev, "couldn't add resources to dwc3 device\n"); 108 dev_err(dev, "couldn't add resources to dwc3 device\n");
106 goto err4; 109 goto err2;
107 } 110 }
108 111
109 pci_set_drvdata(pci, glue); 112 pci_set_drvdata(pci, glue);
110 113
111 dma_set_coherent_mask(&dwc3->dev, pci->dev.coherent_dma_mask); 114 dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
112 115
113 dwc3->dev.dma_mask = pci->dev.dma_mask; 116 dwc3->dev.dma_mask = dev->dma_mask;
114 dwc3->dev.dma_parms = pci->dev.dma_parms; 117 dwc3->dev.dma_parms = dev->dma_parms;
115 dwc3->dev.parent = &pci->dev; 118 dwc3->dev.parent = dev;
116 glue->dwc3 = dwc3; 119 glue->dwc3 = dwc3;
117 120
118 ret = platform_device_add(dwc3); 121 ret = platform_device_add(dwc3);
119 if (ret) { 122 if (ret) {
120 dev_err(&pci->dev, "failed to register dwc3 device\n"); 123 dev_err(dev, "failed to register dwc3 device\n");
121 goto err4; 124 goto err3;
122 } 125 }
123 126
124 return 0; 127 return 0;
125 128
126err4: 129err3:
127 pci_set_drvdata(pci, NULL); 130 pci_set_drvdata(pci, NULL);
128 platform_device_put(dwc3); 131 platform_device_put(dwc3);
129 132
130err3:
131 dwc3_put_device_id(devid);
132
133err2: 133err2:
134 pci_disable_device(pci); 134 dwc3_put_device_id(devid);
135 135
136err1: 136err1:
137 kfree(glue); 137 pci_disable_device(pci);
138 138
139err0:
140 return ret; 139 return ret;
141} 140}
142 141
@@ -148,7 +147,6 @@ static void __devexit dwc3_pci_remove(struct pci_dev *pci)
148 platform_device_unregister(glue->dwc3); 147 platform_device_unregister(glue->dwc3);
149 pci_set_drvdata(pci, NULL); 148 pci_set_drvdata(pci, NULL);
150 pci_disable_device(pci); 149 pci_disable_device(pci);
151 kfree(glue);
152} 150}
153 151
154static DEFINE_PCI_DEVICE_TABLE(dwc3_pci_id_table) = { 152static DEFINE_PCI_DEVICE_TABLE(dwc3_pci_id_table) = {
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index d5c568e91874..25910e251c04 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -76,8 +76,7 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
76 u32 len, u32 type) 76 u32 len, u32 type)
77{ 77{
78 struct dwc3_gadget_ep_cmd_params params; 78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb_hw *trb_hw; 79 struct dwc3_trb *trb;
80 struct dwc3_trb trb;
81 struct dwc3_ep *dep; 80 struct dwc3_ep *dep;
82 81
83 int ret; 82 int ret;
@@ -88,19 +87,17 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
88 return 0; 87 return 0;
89 } 88 }
90 89
91 trb_hw = dwc->ep0_trb; 90 trb = dwc->ep0_trb;
92 memset(&trb, 0, sizeof(trb));
93 91
94 trb.trbctl = type; 92 trb->bpl = lower_32_bits(buf_dma);
95 trb.bplh = buf_dma; 93 trb->bph = upper_32_bits(buf_dma);
96 trb.length = len; 94 trb->size = len;
95 trb->ctrl = type;
97 96
98 trb.hwo = 1; 97 trb->ctrl |= (DWC3_TRB_CTRL_HWO
99 trb.lst = 1; 98 | DWC3_TRB_CTRL_LST
100 trb.ioc = 1; 99 | DWC3_TRB_CTRL_IOC
101 trb.isp_imi = 1; 100 | DWC3_TRB_CTRL_ISP_IMI);
102
103 dwc3_trb_to_hw(&trb, trb_hw);
104 101
105 memset(&params, 0, sizeof(params)); 102 memset(&params, 0, sizeof(params));
106 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 103 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
@@ -315,9 +312,7 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
315 u32 recip; 312 u32 recip;
316 u32 wValue; 313 u32 wValue;
317 u32 wIndex; 314 u32 wIndex;
318 u32 reg;
319 int ret; 315 int ret;
320 u32 mode;
321 316
322 wValue = le16_to_cpu(ctrl->wValue); 317 wValue = le16_to_cpu(ctrl->wValue);
323 wIndex = le16_to_cpu(ctrl->wIndex); 318 wIndex = le16_to_cpu(ctrl->wIndex);
@@ -356,25 +351,8 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
356 if (!set) 351 if (!set)
357 return -EINVAL; 352 return -EINVAL;
358 353
359 mode = wIndex >> 8; 354 dwc->test_mode_nr = wIndex >> 8;
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 355 dwc->test_mode = true;
361 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
362
363 switch (mode) {
364 case TEST_J:
365 case TEST_K:
366 case TEST_SE0_NAK:
367 case TEST_PACKET:
368 case TEST_FORCE_EN:
369 reg |= mode << 1;
370 break;
371 default:
372 return -EINVAL;
373 }
374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
375 break;
376 default:
377 return -EINVAL;
378 } 356 }
379 break; 357 break;
380 358
@@ -396,7 +374,7 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
396 case USB_RECIP_ENDPOINT: 374 case USB_RECIP_ENDPOINT:
397 switch (wValue) { 375 switch (wValue) {
398 case USB_ENDPOINT_HALT: 376 case USB_ENDPOINT_HALT:
399 dep = dwc3_wIndex_to_dep(dwc, wIndex); 377 dep = dwc3_wIndex_to_dep(dwc, wIndex);
400 if (!dep) 378 if (!dep)
401 return -EINVAL; 379 return -EINVAL;
402 ret = __dwc3_gadget_ep_set_halt(dep, set); 380 ret = __dwc3_gadget_ep_set_halt(dep, set);
@@ -470,8 +448,11 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
470 case DWC3_ADDRESS_STATE: 448 case DWC3_ADDRESS_STATE:
471 ret = dwc3_ep0_delegate_req(dwc, ctrl); 449 ret = dwc3_ep0_delegate_req(dwc, ctrl);
472 /* if the cfg matches and the cfg is non zero */ 450 /* if the cfg matches and the cfg is non zero */
473 if (!ret && cfg) 451 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
474 dwc->dev_state = DWC3_CONFIGURED_STATE; 452 dwc->dev_state = DWC3_CONFIGURED_STATE;
453 dwc->resize_fifos = true;
454 dev_dbg(dwc->dev, "resize fifos flag SET\n");
455 }
475 break; 456 break;
476 457
477 case DWC3_CONFIGURED_STATE: 458 case DWC3_CONFIGURED_STATE:
@@ -560,9 +541,10 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
560{ 541{
561 struct dwc3_request *r = NULL; 542 struct dwc3_request *r = NULL;
562 struct usb_request *ur; 543 struct usb_request *ur;
563 struct dwc3_trb trb; 544 struct dwc3_trb *trb;
564 struct dwc3_ep *ep0; 545 struct dwc3_ep *ep0;
565 u32 transferred; 546 u32 transferred;
547 u32 length;
566 u8 epnum; 548 u8 epnum;
567 549
568 epnum = event->endpoint_number; 550 epnum = event->endpoint_number;
@@ -573,16 +555,16 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
573 r = next_request(&ep0->request_list); 555 r = next_request(&ep0->request_list);
574 ur = &r->request; 556 ur = &r->request;
575 557
576 dwc3_trb_to_nat(dwc->ep0_trb, &trb); 558 trb = dwc->ep0_trb;
559 length = trb->size & DWC3_TRB_SIZE_MASK;
577 560
578 if (dwc->ep0_bounced) { 561 if (dwc->ep0_bounced) {
579
580 transferred = min_t(u32, ur->length, 562 transferred = min_t(u32, ur->length,
581 ep0->endpoint.maxpacket - trb.length); 563 ep0->endpoint.maxpacket - length);
582 memcpy(ur->buf, dwc->ep0_bounce, transferred); 564 memcpy(ur->buf, dwc->ep0_bounce, transferred);
583 dwc->ep0_bounced = false; 565 dwc->ep0_bounced = false;
584 } else { 566 } else {
585 transferred = ur->length - trb.length; 567 transferred = ur->length - length;
586 ur->actual += transferred; 568 ur->actual += transferred;
587 } 569 }
588 570
@@ -614,6 +596,17 @@ static void dwc3_ep0_complete_req(struct dwc3 *dwc,
614 dwc3_gadget_giveback(dep, r, 0); 596 dwc3_gadget_giveback(dep, r, 0);
615 } 597 }
616 598
599 if (dwc->test_mode) {
600 int ret;
601
602 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
603 if (ret < 0) {
604 dev_dbg(dwc->dev, "Invalid Test #%d\n",
605 dwc->test_mode_nr);
606 dwc3_ep0_stall_and_restart(dwc);
607 }
608 }
609
617 dwc->ep0state = EP0_SETUP_PHASE; 610 dwc->ep0state = EP0_SETUP_PHASE;
618 dwc3_ep0_out_start(dwc); 611 dwc3_ep0_out_start(dwc);
619} 612}
@@ -624,6 +617,7 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
624 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 617 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
625 618
626 dep->flags &= ~DWC3_EP_BUSY; 619 dep->flags &= ~DWC3_EP_BUSY;
620 dep->res_trans_idx = 0;
627 dwc->setup_packet_pending = false; 621 dwc->setup_packet_pending = false;
628 622
629 switch (dwc->ep0state) { 623 switch (dwc->ep0state) {
@@ -730,6 +724,12 @@ static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
730{ 724{
731 struct dwc3_ep *dep = dwc->eps[epnum]; 725 struct dwc3_ep *dep = dwc->eps[epnum];
732 726
727 if (dwc->resize_fifos) {
728 dev_dbg(dwc->dev, "starting to resize fifos\n");
729 dwc3_gadget_resize_tx_fifos(dwc);
730 dwc->resize_fifos = 0;
731 }
732
733 WARN_ON(dwc3_ep0_start_control_status(dep)); 733 WARN_ON(dwc3_ep0_start_control_status(dep));
734} 734}
735 735
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 1009e7e47a24..5255fe975ea1 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -54,6 +54,164 @@
54#include "gadget.h" 54#include "gadget.h"
55#include "io.h" 55#include "io.h"
56 56
57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
100 int retries = 10000;
101 u32 reg;
102
103 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
104 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
105
106 /* set requested state */
107 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
109
110 /* wait for a change in DSTS */
111 while (--retries) {
112 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
113
114 if (DWC3_DSTS_USBLNKST(reg) == state)
115 return 0;
116
117 udelay(5);
118 }
119
120 dev_vdbg(dwc->dev, "link state change request timed out\n");
121
122 return -ETIMEDOUT;
123}
124
125/**
126 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
127 * @dwc: pointer to our context structure
128 *
129 * This function will a best effort FIFO allocation in order
130 * to improve FIFO usage and throughput, while still allowing
131 * us to enable as many endpoints as possible.
132 *
133 * Keep in mind that this operation will be highly dependent
134 * on the configured size for RAM1 - which contains TxFifo -,
135 * the amount of endpoints enabled on coreConsultant tool, and
136 * the width of the Master Bus.
137 *
138 * In the ideal world, we would always be able to satisfy the
139 * following equation:
140 *
141 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
142 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
143 *
144 * Unfortunately, due to many variables that's not always the case.
145 */
146int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
147{
148 int last_fifo_depth = 0;
149 int ram1_depth;
150 int fifo_size;
151 int mdwidth;
152 int num;
153
154 if (!dwc->needs_fifo_resize)
155 return 0;
156
157 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
158 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
159
160 /* MDWIDTH is represented in bits, we need it in bytes */
161 mdwidth >>= 3;
162
163 /*
164 * FIXME For now we will only allocate 1 wMaxPacketSize space
165 * for each enabled endpoint, later patches will come to
166 * improve this algorithm so that we better use the internal
167 * FIFO space
168 */
169 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
170 struct dwc3_ep *dep = dwc->eps[num];
171 int fifo_number = dep->number >> 1;
172 int mult = 1;
173 int tmp;
174
175 if (!(dep->number & 1))
176 continue;
177
178 if (!(dep->flags & DWC3_EP_ENABLED))
179 continue;
180
181 if (usb_endpoint_xfer_bulk(dep->desc)
182 || usb_endpoint_xfer_isoc(dep->desc))
183 mult = 3;
184
185 /*
186 * REVISIT: the following assumes we will always have enough
187 * space available on the FIFO RAM for all possible use cases.
188 * Make sure that's true somehow and change FIFO allocation
189 * accordingly.
190 *
191 * If we have Bulk or Isochronous endpoints, we want
192 * them to be able to be very, very fast. So we're giving
193 * those endpoints a fifo_size which is enough for 3 full
194 * packets
195 */
196 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
197 tmp += mdwidth;
198
199 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
200
201 fifo_size |= (last_fifo_depth << 16);
202
203 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
204 dep->name, last_fifo_depth, fifo_size & 0xffff);
205
206 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
207 fifo_size);
208
209 last_fifo_depth += (fifo_size & 0xffff);
210 }
211
212 return 0;
213}
214
57void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 215void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
58 int status) 216 int status)
59{ 217{
@@ -156,7 +314,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
156} 314}
157 315
158static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 316static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
159 struct dwc3_trb_hw *trb) 317 struct dwc3_trb *trb)
160{ 318{
161 u32 offset = (char *) trb - (char *) dep->trb_pool; 319 u32 offset = (char *) trb - (char *) dep->trb_pool;
162 320
@@ -305,9 +463,8 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
305 return ret; 463 return ret;
306 464
307 if (!(dep->flags & DWC3_EP_ENABLED)) { 465 if (!(dep->flags & DWC3_EP_ENABLED)) {
308 struct dwc3_trb_hw *trb_st_hw; 466 struct dwc3_trb *trb_st_hw;
309 struct dwc3_trb_hw *trb_link_hw; 467 struct dwc3_trb *trb_link;
310 struct dwc3_trb trb_link;
311 468
312 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 469 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
313 if (ret) 470 if (ret)
@@ -327,15 +484,15 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
327 484
328 memset(&trb_link, 0, sizeof(trb_link)); 485 memset(&trb_link, 0, sizeof(trb_link));
329 486
330 /* Link TRB for ISOC. The HWO but is never reset */ 487 /* Link TRB for ISOC. The HWO bit is never reset */
331 trb_st_hw = &dep->trb_pool[0]; 488 trb_st_hw = &dep->trb_pool[0];
332 489
333 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw); 490 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
334 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
335 trb_link.hwo = true;
336 491
337 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1]; 492 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
338 dwc3_trb_to_hw(&trb_link, trb_link_hw); 493 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
494 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
495 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
339 } 496 }
340 497
341 return 0; 498 return 0;
@@ -423,16 +580,16 @@ static int dwc3_gadget_ep_enable(struct usb_ep *ep,
423 580
424 switch (usb_endpoint_type(desc)) { 581 switch (usb_endpoint_type(desc)) {
425 case USB_ENDPOINT_XFER_CONTROL: 582 case USB_ENDPOINT_XFER_CONTROL:
426 strncat(dep->name, "-control", sizeof(dep->name)); 583 strlcat(dep->name, "-control", sizeof(dep->name));
427 break; 584 break;
428 case USB_ENDPOINT_XFER_ISOC: 585 case USB_ENDPOINT_XFER_ISOC:
429 strncat(dep->name, "-isoc", sizeof(dep->name)); 586 strlcat(dep->name, "-isoc", sizeof(dep->name));
430 break; 587 break;
431 case USB_ENDPOINT_XFER_BULK: 588 case USB_ENDPOINT_XFER_BULK:
432 strncat(dep->name, "-bulk", sizeof(dep->name)); 589 strlcat(dep->name, "-bulk", sizeof(dep->name));
433 break; 590 break;
434 case USB_ENDPOINT_XFER_INT: 591 case USB_ENDPOINT_XFER_INT:
435 strncat(dep->name, "-int", sizeof(dep->name)); 592 strlcat(dep->name, "-int", sizeof(dep->name));
436 break; 593 break;
437 default: 594 default:
438 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 595 dev_err(dwc->dev, "invalid endpoint transfer type\n");
@@ -522,8 +679,7 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
522 unsigned length, unsigned last, unsigned chain) 679 unsigned length, unsigned last, unsigned chain)
523{ 680{
524 struct dwc3 *dwc = dep->dwc; 681 struct dwc3 *dwc = dep->dwc;
525 struct dwc3_trb_hw *trb_hw; 682 struct dwc3_trb *trb;
526 struct dwc3_trb trb;
527 683
528 unsigned int cur_slot; 684 unsigned int cur_slot;
529 685
@@ -532,7 +688,7 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
532 length, last ? " last" : "", 688 length, last ? " last" : "",
533 chain ? " chain" : ""); 689 chain ? " chain" : "");
534 690
535 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 691 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
536 cur_slot = dep->free_slot; 692 cur_slot = dep->free_slot;
537 dep->free_slot++; 693 dep->free_slot++;
538 694
@@ -541,40 +697,32 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
541 usb_endpoint_xfer_isoc(dep->desc)) 697 usb_endpoint_xfer_isoc(dep->desc))
542 return; 698 return;
543 699
544 memset(&trb, 0, sizeof(trb));
545 if (!req->trb) { 700 if (!req->trb) {
546 dwc3_gadget_move_request_queued(req); 701 dwc3_gadget_move_request_queued(req);
547 req->trb = trb_hw; 702 req->trb = trb;
548 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw); 703 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
549 } 704 }
550 705
551 if (usb_endpoint_xfer_isoc(dep->desc)) { 706 trb->size = DWC3_TRB_SIZE_LENGTH(length);
552 trb.isp_imi = true; 707 trb->bpl = lower_32_bits(dma);
553 trb.csp = true; 708 trb->bph = upper_32_bits(dma);
554 } else {
555 trb.chn = chain;
556 trb.lst = last;
557 }
558
559 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
560 trb.sid_sofn = req->request.stream_id;
561 709
562 switch (usb_endpoint_type(dep->desc)) { 710 switch (usb_endpoint_type(dep->desc)) {
563 case USB_ENDPOINT_XFER_CONTROL: 711 case USB_ENDPOINT_XFER_CONTROL:
564 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; 712 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
565 break; 713 break;
566 714
567 case USB_ENDPOINT_XFER_ISOC: 715 case USB_ENDPOINT_XFER_ISOC:
568 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 716 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
569 717
570 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 718 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
571 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 719 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
572 trb.ioc = last; 720 trb->ctrl |= DWC3_TRB_CTRL_IOC;
573 break; 721 break;
574 722
575 case USB_ENDPOINT_XFER_BULK: 723 case USB_ENDPOINT_XFER_BULK:
576 case USB_ENDPOINT_XFER_INT: 724 case USB_ENDPOINT_XFER_INT:
577 trb.trbctl = DWC3_TRBCTL_NORMAL; 725 trb->ctrl = DWC3_TRBCTL_NORMAL;
578 break; 726 break;
579 default: 727 default:
580 /* 728 /*
@@ -584,11 +732,21 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
584 BUG(); 732 BUG();
585 } 733 }
586 734
587 trb.length = length; 735 if (usb_endpoint_xfer_isoc(dep->desc)) {
588 trb.bplh = dma; 736 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
589 trb.hwo = true; 737 trb->ctrl |= DWC3_TRB_CTRL_CSP;
738 } else {
739 if (chain)
740 trb->ctrl |= DWC3_TRB_CTRL_CHN;
741
742 if (last)
743 trb->ctrl |= DWC3_TRB_CTRL_LST;
744 }
590 745
591 dwc3_trb_to_hw(&trb, trb_hw); 746 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
747 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
748
749 trb->ctrl |= DWC3_TRB_CTRL_HWO;
592} 750}
593 751
594/* 752/*
@@ -596,14 +754,15 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
596 * @dep: endpoint for which requests are being prepared 754 * @dep: endpoint for which requests are being prepared
597 * @starting: true if the endpoint is idle and no requests are queued. 755 * @starting: true if the endpoint is idle and no requests are queued.
598 * 756 *
599 * The functions goes through the requests list and setups TRBs for the 757 * The function goes through the requests list and sets up TRBs for the
600 * transfers. The functions returns once there are not more TRBs available or 758 * transfers. The function returns once there are no more TRBs available or
601 * it run out of requests. 759 * it runs out of requests.
602 */ 760 */
603static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 761static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
604{ 762{
605 struct dwc3_request *req, *n; 763 struct dwc3_request *req, *n;
606 u32 trbs_left; 764 u32 trbs_left;
765 u32 max;
607 unsigned int last_one = 0; 766 unsigned int last_one = 0;
608 767
609 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 768 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
@@ -611,9 +770,16 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
611 /* the first request must not be queued */ 770 /* the first request must not be queued */
612 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 771 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
613 772
773 /* Can't wrap around on a non-isoc EP since there's no link TRB */
774 if (!usb_endpoint_xfer_isoc(dep->desc)) {
775 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
776 if (trbs_left > max)
777 trbs_left = max;
778 }
779
614 /* 780 /*
615 * if busy & slot are equal than it is either full or empty. If we are 781 * If busy & slot are equal than it is either full or empty. If we are
616 * starting to proceed requests then we are empty. Otherwise we ar 782 * starting to process requests then we are empty. Otherwise we are
617 * full and don't do anything 783 * full and don't do anything
618 */ 784 */
619 if (!trbs_left) { 785 if (!trbs_left) {
@@ -624,7 +790,7 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
624 * In case we start from scratch, we queue the ISOC requests 790 * In case we start from scratch, we queue the ISOC requests
625 * starting from slot 1. This is done because we use ring 791 * starting from slot 1. This is done because we use ring
626 * buffer and have no LST bit to stop us. Instead, we place 792 * buffer and have no LST bit to stop us. Instead, we place
627 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt 793 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
628 * after the first request so we start at slot 1 and have 794 * after the first request so we start at slot 1 and have
629 * 7 requests proceed before we hit the first IOC. 795 * 7 requests proceed before we hit the first IOC.
630 * Other transfer types don't use the ring buffer and are 796 * Other transfer types don't use the ring buffer and are
@@ -660,8 +826,8 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
660 length = sg_dma_len(s); 826 length = sg_dma_len(s);
661 dma = sg_dma_address(s); 827 dma = sg_dma_address(s);
662 828
663 if (i == (request->num_mapped_sgs - 1) 829 if (i == (request->num_mapped_sgs - 1) ||
664 || sg_is_last(s)) { 830 sg_is_last(s)) {
665 last_one = true; 831 last_one = true;
666 chain = false; 832 chain = false;
667 } 833 }
@@ -729,8 +895,7 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
729 dwc3_prepare_trbs(dep, start_new); 895 dwc3_prepare_trbs(dep, start_new);
730 896
731 /* 897 /*
732 * req points to the first request where HWO changed 898 * req points to the first request where HWO changed from 0 to 1
733 * from 0 to 1
734 */ 899 */
735 req = next_request(&dep->req_queued); 900 req = next_request(&dep->req_queued);
736 } 901 }
@@ -756,7 +921,7 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
756 /* 921 /*
757 * FIXME we need to iterate over the list of requests 922 * FIXME we need to iterate over the list of requests
758 * here and stop, unmap, free and del each of the linked 923 * here and stop, unmap, free and del each of the linked
759 * requests instead of we do now. 924 * requests instead of what we do now.
760 */ 925 */
761 usb_gadget_unmap_request(&dwc->gadget, &req->request, 926 usb_gadget_unmap_request(&dwc->gadget, &req->request,
762 req->direction); 927 req->direction);
@@ -793,7 +958,7 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
793 * particular token from the Host side. 958 * particular token from the Host side.
794 * 959 *
795 * This will also avoid Host cancelling URBs due to too 960 * This will also avoid Host cancelling URBs due to too
796 * many NACKs. 961 * many NAKs.
797 */ 962 */
798 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 963 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
799 dep->direction); 964 dep->direction);
@@ -819,11 +984,11 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
819 int start_trans; 984 int start_trans;
820 985
821 start_trans = 1; 986 start_trans = 1;
822 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 987 if (usb_endpoint_xfer_isoc(dep->desc) &&
823 dep->flags & DWC3_EP_BUSY) 988 (dep->flags & DWC3_EP_BUSY))
824 start_trans = 0; 989 start_trans = 0;
825 990
826 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans); 991 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
827 if (ret && ret != -EBUSY) { 992 if (ret && ret != -EBUSY) {
828 struct dwc3 *dwc = dep->dwc; 993 struct dwc3 *dwc = dep->dwc;
829 994
@@ -976,8 +1141,12 @@ out:
976static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1141static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
977{ 1142{
978 struct dwc3_ep *dep = to_dwc3_ep(ep); 1143 struct dwc3_ep *dep = to_dwc3_ep(ep);
1144 struct dwc3 *dwc = dep->dwc;
1145 unsigned long flags;
979 1146
1147 spin_lock_irqsave(&dwc->lock, flags);
980 dep->flags |= DWC3_EP_WEDGE; 1148 dep->flags |= DWC3_EP_WEDGE;
1149 spin_unlock_irqrestore(&dwc->lock, flags);
981 1150
982 return dwc3_gadget_ep_set_halt(ep, 1); 1151 return dwc3_gadget_ep_set_halt(ep, 1);
983} 1152}
@@ -1067,26 +1236,20 @@ static int dwc3_gadget_wakeup(struct usb_gadget *g)
1067 goto out; 1236 goto out;
1068 } 1237 }
1069 1238
1070 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1239 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1071 1240 if (ret < 0) {
1072 /* 1241 dev_err(dwc->dev, "failed to put link in Recovery\n");
1073 * Switch link state to Recovery. In HS/FS/LS this means 1242 goto out;
1074 * RemoteWakeup Request 1243 }
1075 */
1076 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1077 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1078
1079 /* wait for at least 2000us */
1080 usleep_range(2000, 2500);
1081 1244
1082 /* write zeroes to Link Change Request */ 1245 /* write zeroes to Link Change Request */
1083 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1246 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1084 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1247 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1085 1248
1086 /* pool until Link State change to ON */ 1249 /* poll until Link State changes to ON */
1087 timeout = jiffies + msecs_to_jiffies(100); 1250 timeout = jiffies + msecs_to_jiffies(100);
1088 1251
1089 while (!(time_after(jiffies, timeout))) { 1252 while (!time_after(jiffies, timeout)) {
1090 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1253 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1091 1254
1092 /* in HS, means ON */ 1255 /* in HS, means ON */
@@ -1109,8 +1272,11 @@ static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1109 int is_selfpowered) 1272 int is_selfpowered)
1110{ 1273{
1111 struct dwc3 *dwc = gadget_to_dwc(g); 1274 struct dwc3 *dwc = gadget_to_dwc(g);
1275 unsigned long flags;
1112 1276
1277 spin_lock_irqsave(&dwc->lock, flags);
1113 dwc->is_selfpowered = !!is_selfpowered; 1278 dwc->is_selfpowered = !!is_selfpowered;
1279 spin_unlock_irqrestore(&dwc->lock, flags);
1114 1280
1115 return 0; 1281 return 0;
1116} 1282}
@@ -1121,10 +1287,13 @@ static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1121 u32 timeout = 500; 1287 u32 timeout = 500;
1122 1288
1123 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1289 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1124 if (is_on) 1290 if (is_on) {
1125 reg |= DWC3_DCTL_RUN_STOP; 1291 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1126 else 1292 reg |= (DWC3_DCTL_RUN_STOP
1293 | DWC3_DCTL_TRGTULST_RX_DET);
1294 } else {
1127 reg &= ~DWC3_DCTL_RUN_STOP; 1295 reg &= ~DWC3_DCTL_RUN_STOP;
1296 }
1128 1297
1129 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1298 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1130 1299
@@ -1331,7 +1500,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1331 const struct dwc3_event_depevt *event, int status) 1500 const struct dwc3_event_depevt *event, int status)
1332{ 1501{
1333 struct dwc3_request *req; 1502 struct dwc3_request *req;
1334 struct dwc3_trb trb; 1503 struct dwc3_trb *trb;
1335 unsigned int count; 1504 unsigned int count;
1336 unsigned int s_pkt = 0; 1505 unsigned int s_pkt = 0;
1337 1506
@@ -1342,20 +1511,20 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1342 return 1; 1511 return 1;
1343 } 1512 }
1344 1513
1345 dwc3_trb_to_nat(req->trb, &trb); 1514 trb = req->trb;
1346 1515
1347 if (trb.hwo && status != -ESHUTDOWN) 1516 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1348 /* 1517 /*
1349 * We continue despite the error. There is not much we 1518 * We continue despite the error. There is not much we
1350 * can do. If we don't clean in up we loop for ever. If 1519 * can do. If we don't clean it up we loop forever. If
1351 * we skip the TRB than it gets overwritten reused after 1520 * we skip the TRB then it gets overwritten after a
1352 * a while since we use them in a ring buffer. a BUG() 1521 * while since we use them in a ring buffer. A BUG()
1353 * would help. Lets hope that if this occures, someone 1522 * would help. Lets hope that if this occurs, someone
1354 * fixes the root cause instead of looking away :) 1523 * fixes the root cause instead of looking away :)
1355 */ 1524 */
1356 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1525 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1357 dep->name, req->trb); 1526 dep->name, req->trb);
1358 count = trb.length; 1527 count = trb->size & DWC3_TRB_SIZE_MASK;
1359 1528
1360 if (dep->direction) { 1529 if (dep->direction) {
1361 if (count) { 1530 if (count) {
@@ -1379,13 +1548,16 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1379 dwc3_gadget_giveback(dep, req, status); 1548 dwc3_gadget_giveback(dep, req, status);
1380 if (s_pkt) 1549 if (s_pkt)
1381 break; 1550 break;
1382 if ((event->status & DEPEVT_STATUS_LST) && trb.lst) 1551 if ((event->status & DEPEVT_STATUS_LST) &&
1552 (trb->ctrl & DWC3_TRB_CTRL_LST))
1383 break; 1553 break;
1384 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1554 if ((event->status & DEPEVT_STATUS_IOC) &&
1555 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1385 break; 1556 break;
1386 } while (1); 1557 } while (1);
1387 1558
1388 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1559 if ((event->status & DEPEVT_STATUS_IOC) &&
1560 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1389 return 0; 1561 return 0;
1390 return 1; 1562 return 1;
1391} 1563}
@@ -1400,11 +1572,9 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1400 if (event->status & DEPEVT_STATUS_BUSERR) 1572 if (event->status & DEPEVT_STATUS_BUSERR)
1401 status = -ECONNRESET; 1573 status = -ECONNRESET;
1402 1574
1403 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1575 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1404 if (clean_busy) { 1576 if (clean_busy)
1405 dep->flags &= ~DWC3_EP_BUSY; 1577 dep->flags &= ~DWC3_EP_BUSY;
1406 dep->res_trans_idx = 0;
1407 }
1408 1578
1409 /* 1579 /*
1410 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1580 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
@@ -1435,7 +1605,7 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1435static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1605static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1436 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1606 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1437{ 1607{
1438 u32 uf; 1608 u32 uf, mask;
1439 1609
1440 if (list_empty(&dep->request_list)) { 1610 if (list_empty(&dep->request_list)) {
1441 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1611 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
@@ -1443,16 +1613,10 @@ static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1443 return; 1613 return;
1444 } 1614 }
1445 1615
1446 if (event->parameters) { 1616 mask = ~(dep->interval - 1);
1447 u32 mask; 1617 uf = event->parameters & mask;
1448 1618 /* 4 micro frames in the future */
1449 mask = ~(dep->interval - 1); 1619 uf += dep->interval * 4;
1450 uf = event->parameters & mask;
1451 /* 4 micro frames in the future */
1452 uf += dep->interval * 4;
1453 } else {
1454 uf = 0;
1455 }
1456 1620
1457 __dwc3_gadget_kick_transfer(dep, uf, 1); 1621 __dwc3_gadget_kick_transfer(dep, uf, 1);
1458} 1622}
@@ -1464,8 +1628,8 @@ static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1464 struct dwc3_event_depevt mod_ev = *event; 1628 struct dwc3_event_depevt mod_ev = *event;
1465 1629
1466 /* 1630 /*
1467 * We were asked to remove one requests. It is possible that this 1631 * We were asked to remove one request. It is possible that this
1468 * request and a few other were started together and have the same 1632 * request and a few others were started together and have the same
1469 * transfer index. Since we stopped the complete endpoint we don't 1633 * transfer index. Since we stopped the complete endpoint we don't
1470 * know how many requests were already completed (and not yet) 1634 * know how many requests were already completed (and not yet)
1471 * reported and how could be done (later). We purge them all until 1635 * reported and how could be done (later). We purge them all until
@@ -1474,7 +1638,7 @@ static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1474 mod_ev.status = DEPEVT_STATUS_LST; 1638 mod_ev.status = DEPEVT_STATUS_LST;
1475 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1639 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1476 dep->flags &= ~DWC3_EP_BUSY; 1640 dep->flags &= ~DWC3_EP_BUSY;
1477 /* pending requets are ignored and are queued on XferNotReady */ 1641 /* pending requests are ignored and are queued on XferNotReady */
1478} 1642}
1479 1643
1480static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1644static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
@@ -1515,6 +1679,8 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1515 1679
1516 switch (event->endpoint_event) { 1680 switch (event->endpoint_event) {
1517 case DWC3_DEPEVT_XFERCOMPLETE: 1681 case DWC3_DEPEVT_XFERCOMPLETE:
1682 dep->res_trans_idx = 0;
1683
1518 if (usb_endpoint_xfer_isoc(dep->desc)) { 1684 if (usb_endpoint_xfer_isoc(dep->desc)) {
1519 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1685 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1520 dep->name); 1686 dep->name);
@@ -1539,7 +1705,8 @@ static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1539 int ret; 1705 int ret;
1540 1706
1541 dev_vdbg(dwc->dev, "%s: reason %s\n", 1707 dev_vdbg(dwc->dev, "%s: reason %s\n",
1542 dep->name, event->status 1708 dep->name, event->status &
1709 DEPEVT_STATUS_TRANSFER_ACTIVE
1543 ? "Transfer Active" 1710 ? "Transfer Active"
1544 : "Transfer Not Active"); 1711 : "Transfer Not Active");
1545 1712
@@ -1750,6 +1917,7 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1750 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1917 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1751 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 1918 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1752 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1919 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1920 dwc->test_mode = false;
1753 1921
1754 dwc3_stop_active_transfers(dwc); 1922 dwc3_stop_active_transfers(dwc);
1755 dwc3_clear_stall_all_ep(dwc); 1923 dwc3_clear_stall_all_ep(dwc);
@@ -2027,7 +2195,8 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2027 while (left > 0) { 2195 while (left > 0) {
2028 union dwc3_event event; 2196 union dwc3_event event;
2029 2197
2030 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw)); 2198 event.raw = *(u32 *) (evt->buf + evt->lpos);
2199
2031 dwc3_process_event_entry(dwc, &event); 2200 dwc3_process_event_entry(dwc, &event);
2032 /* 2201 /*
2033 * XXX we wrap around correctly to the next entry as almost all 2202 * XXX we wrap around correctly to the next entry as almost all
@@ -2068,7 +2237,7 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2068 2237
2069/** 2238/**
2070 * dwc3_gadget_init - Initializes gadget related registers 2239 * dwc3_gadget_init - Initializes gadget related registers
2071 * @dwc: Pointer to out controller context structure 2240 * @dwc: pointer to our controller context structure
2072 * 2241 *
2073 * Returns 0 on success otherwise negative errno. 2242 * Returns 0 on success otherwise negative errno.
2074 */ 2243 */
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
index 12f1e104977f..a8600084348c 100644
--- a/drivers/usb/dwc3/gadget.h
+++ b/drivers/usb/dwc3/gadget.h
@@ -100,6 +100,9 @@ static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
100void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 100void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
101 int status); 101 int status);
102 102
103int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
104int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
105
103void dwc3_ep0_interrupt(struct dwc3 *dwc, 106void dwc3_ep0_interrupt(struct dwc3 *dwc,
104 const struct dwc3_event_depevt *event); 107 const struct dwc3_event_depevt *event);
105void dwc3_ep0_out_start(struct dwc3 *dwc); 108void dwc3_ep0_out_start(struct dwc3 *dwc);
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index 7cfe211b6c37..b108d18fd40d 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -53,7 +53,7 @@ int dwc3_host_init(struct dwc3 *dwc)
53 struct platform_device *xhci; 53 struct platform_device *xhci;
54 int ret; 54 int ret;
55 55
56 xhci = platform_device_alloc("xhci", -1); 56 xhci = platform_device_alloc("xhci-hcd", -1);
57 if (!xhci) { 57 if (!xhci) {
58 dev_err(dwc->dev, "couldn't allocate xHCI device\n"); 58 dev_err(dwc->dev, "couldn't allocate xHCI device\n");
59 ret = -ENOMEM; 59 ret = -ENOMEM;
diff --git a/include/linux/platform_data/dwc3-exynos.h b/include/linux/platform_data/dwc3-exynos.h
new file mode 100644
index 000000000000..5eb7da9b3772
--- /dev/null
+++ b/include/linux/platform_data/dwc3-exynos.h
@@ -0,0 +1,24 @@
1/**
2 * dwc3-exynos.h - Samsung EXYNOS DWC3 Specific Glue layer, header.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef _DWC3_EXYNOS_H_
16#define _DWC3_EXYNOS_H_
17
18struct dwc3_exynos_data {
19 int phy_type;
20 int (*phy_init)(struct platform_device *pdev, int type);
21 int (*phy_exit)(struct platform_device *pdev, int type);
22};
23
24#endif /* _DWC3_EXYNOS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 09:28:13 -0500