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authorStephane Viau <sviau@codeaurora.org>2014-07-07 10:34:01 -0400
committerRob Clark <robdclark@gmail.com>2014-08-04 11:55:30 -0400
commit3d47fd47f28903f5a9167e95f32a906bd53e13e6 (patch)
tree973c6d9045c8bc267f3bcb1de235e5cb67521384
parenta1ad35233345e7ddd9ea3ea7b841432f4723d743 (diff)
drm/msm/mdp5: add support for MDP5 v1.3
MDP5 has several functional blocks (ie: VIG/RGB pipes, LMs, ...). From one revision to another, these blocks' base addresses might change due to the number of instances present in the MDP5 hw. A way of dealing with these offset changes is to introduce dynamic offsets 'per block'. This change adds support for the new revision of MDP5: v1.3. The idea is to define one hw config per MDP version and select either one of them at runtime, after reading the MDP5 version. Once the MDP version is known, 'per block' dynamic offsets are initialized through a global pointer, which is then used for read/write register access. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h425
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c151
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h25
3 files changed, 421 insertions, 180 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index d501bacda4b6..67f4f896ba8c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -68,6 +68,8 @@ enum mdp5_pipe {
68 SSPP_RGB2 = 5, 68 SSPP_RGB2 = 5,
69 SSPP_DMA0 = 6, 69 SSPP_DMA0 = 6,
70 SSPP_DMA1 = 7, 70 SSPP_DMA1 = 7,
71 SSPP_VIG3 = 8,
72 SSPP_RGB3 = 9,
71}; 73};
72 74
73enum mdp5_ctl_mode { 75enum mdp5_ctl_mode {
@@ -126,7 +128,11 @@ enum mdp5_client_id {
126 CID_RGB0 = 16, 128 CID_RGB0 = 16,
127 CID_RGB1 = 17, 129 CID_RGB1 = 17,
128 CID_RGB2 = 18, 130 CID_RGB2 = 18,
129 CID_MAX = 19, 131 CID_VIG3_Y = 19,
132 CID_VIG3_CR = 20,
133 CID_VIG3_CB = 21,
134 CID_RGB3 = 22,
135 CID_MAX = 23,
130}; 136};
131 137
132enum mdp5_igc_type { 138enum mdp5_igc_type {
@@ -299,11 +305,34 @@ static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
299#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 305#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
300#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 306#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
301 307
302static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000600 + 0x100*i0; } 308static inline uint32_t __offset_CTL(uint32_t idx)
309{
310 switch (idx) {
311 case 0: return (mdp5_cfg->ctl.base[0]);
312 case 1: return (mdp5_cfg->ctl.base[1]);
313 case 2: return (mdp5_cfg->ctl.base[2]);
314 case 3: return (mdp5_cfg->ctl.base[3]);
315 case 4: return (mdp5_cfg->ctl.base[4]);
316 default: return INVALID_IDX(idx);
317 }
318}
319static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
303 320
304static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; } 321static inline uint32_t __offset_LAYER(uint32_t idx)
322{
323 switch (idx) {
324 case 0: return 0x00000000;
325 case 1: return 0x00000004;
326 case 2: return 0x00000008;
327 case 3: return 0x0000000c;
328 case 4: return 0x00000010;
329 case 5: return 0x00000024;
330 default: return INVALID_IDX(idx);
331 }
332}
333static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
305 334
306static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; } 335static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
307#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007 336#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
308#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0 337#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
309static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val) 338static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
@@ -354,8 +383,20 @@ static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
354} 383}
355#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000 384#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
356#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000 385#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
386#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
387#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
388static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
389{
390 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
391}
392#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
393#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
394static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
395{
396 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
397}
357 398
358static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000614 + 0x100*i0; } 399static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
359#define MDP5_CTL_OP_MODE__MASK 0x0000000f 400#define MDP5_CTL_OP_MODE__MASK 0x0000000f
360#define MDP5_CTL_OP_MODE__SHIFT 0 401#define MDP5_CTL_OP_MODE__SHIFT 0
361static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) 402static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
@@ -377,7 +418,7 @@ static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
377 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK; 418 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
378} 419}
379 420
380static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000618 + 0x100*i0; } 421static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
381#define MDP5_CTL_FLUSH_VIG0 0x00000001 422#define MDP5_CTL_FLUSH_VIG0 0x00000001
382#define MDP5_CTL_FLUSH_VIG1 0x00000002 423#define MDP5_CTL_FLUSH_VIG1 0x00000002
383#define MDP5_CTL_FLUSH_VIG2 0x00000004 424#define MDP5_CTL_FLUSH_VIG2 0x00000004
@@ -387,26 +428,48 @@ static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000618 + 0x1
387#define MDP5_CTL_FLUSH_LM0 0x00000040 428#define MDP5_CTL_FLUSH_LM0 0x00000040
388#define MDP5_CTL_FLUSH_LM1 0x00000080 429#define MDP5_CTL_FLUSH_LM1 0x00000080
389#define MDP5_CTL_FLUSH_LM2 0x00000100 430#define MDP5_CTL_FLUSH_LM2 0x00000100
431#define MDP5_CTL_FLUSH_LM3 0x00000200
432#define MDP5_CTL_FLUSH_LM4 0x00000400
390#define MDP5_CTL_FLUSH_DMA0 0x00000800 433#define MDP5_CTL_FLUSH_DMA0 0x00000800
391#define MDP5_CTL_FLUSH_DMA1 0x00001000 434#define MDP5_CTL_FLUSH_DMA1 0x00001000
392#define MDP5_CTL_FLUSH_DSPP0 0x00002000 435#define MDP5_CTL_FLUSH_DSPP0 0x00002000
393#define MDP5_CTL_FLUSH_DSPP1 0x00004000 436#define MDP5_CTL_FLUSH_DSPP1 0x00004000
394#define MDP5_CTL_FLUSH_DSPP2 0x00008000 437#define MDP5_CTL_FLUSH_DSPP2 0x00008000
395#define MDP5_CTL_FLUSH_CTL 0x00020000 438#define MDP5_CTL_FLUSH_CTL 0x00020000
439#define MDP5_CTL_FLUSH_VIG3 0x00040000
440#define MDP5_CTL_FLUSH_RGB3 0x00080000
441#define MDP5_CTL_FLUSH_LM5 0x00100000
442#define MDP5_CTL_FLUSH_DSPP3 0x00200000
396 443
397static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000061c + 0x100*i0; } 444static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
398 445
399static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000620 + 0x100*i0; } 446static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
400 447
401static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; } 448static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
449{
450 switch (idx) {
451 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
452 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
453 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
454 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
455 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
456 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
457 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
458 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
459 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
460 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
461 default: return INVALID_IDX(idx);
462 }
463}
464static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
402 465
403static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000014c4 + 0x400*i0; } 466static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
404 467
405static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000014f0 + 0x400*i0; } 468static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
406 469
407static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00001500 + 0x400*i0; } 470static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
408 471
409static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; } 472static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
410#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 473#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
411#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 474#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
412static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) 475static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
@@ -420,7 +483,7 @@ static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
420 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK; 483 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
421} 484}
422 485
423static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00001204 + 0x400*i0; } 486static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
424#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000 487#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
425#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16 488#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
426static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) 489static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
@@ -434,7 +497,7 @@ static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
434 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK; 497 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
435} 498}
436 499
437static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00001208 + 0x400*i0; } 500static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
438#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000 501#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
439#define MDP5_PIPE_SRC_XY_Y__SHIFT 16 502#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
440static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) 503static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
@@ -448,7 +511,7 @@ static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
448 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK; 511 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
449} 512}
450 513
451static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000120c + 0x400*i0; } 514static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
452#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000 515#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
453#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16 516#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
454static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) 517static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
@@ -462,7 +525,7 @@ static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
462 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK; 525 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
463} 526}
464 527
465static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00001210 + 0x400*i0; } 528static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
466#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000 529#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
467#define MDP5_PIPE_OUT_XY_Y__SHIFT 16 530#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
468static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) 531static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
@@ -476,15 +539,15 @@ static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
476 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK; 539 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
477} 540}
478 541
479static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00001214 + 0x400*i0; } 542static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
480 543
481static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00001218 + 0x400*i0; } 544static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
482 545
483static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000121c + 0x400*i0; } 546static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
484 547
485static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00001220 + 0x400*i0; } 548static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
486 549
487static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00001224 + 0x400*i0; } 550static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
488#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 551#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
489#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0 552#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
490static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) 553static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
@@ -498,7 +561,7 @@ static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
498 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK; 561 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
499} 562}
500 563
501static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00001228 + 0x400*i0; } 564static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
502#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 565#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
503#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0 566#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
504static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) 567static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
@@ -512,9 +575,9 @@ static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
512 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK; 575 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
513} 576}
514 577
515static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000122c + 0x400*i0; } 578static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
516 579
517static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00001230 + 0x400*i0; } 580static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
518#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 581#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
519#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 582#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
520static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) 583static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
@@ -568,7 +631,7 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_ty
568 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; 631 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
569} 632}
570 633
571static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00001234 + 0x400*i0; } 634static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
572#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 635#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
573#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 636#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
574static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) 637static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
@@ -594,7 +657,7 @@ static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
594 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK; 657 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
595} 658}
596 659
597static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00001238 + 0x400*i0; } 660static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
598#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001 661#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
599#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006 662#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
600#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1 663#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
@@ -610,29 +673,29 @@ static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
610#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000 673#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
611#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000 674#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
612 675
613static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000123c + 0x400*i0; } 676static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
614 677
615static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00001248 + 0x400*i0; } 678static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
616 679
617static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000124c + 0x400*i0; } 680static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
618 681
619static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00001250 + 0x400*i0; } 682static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
620 683
621static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00001254 + 0x400*i0; } 684static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
622 685
623static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00001258 + 0x400*i0; } 686static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
624 687
625static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00001270 + 0x400*i0; } 688static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
626 689
627static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000012a4 + 0x400*i0; } 690static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
628 691
629static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000012a8 + 0x400*i0; } 692static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
630 693
631static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000012ac + 0x400*i0; } 694static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
632 695
633static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000012b0 + 0x400*i0; } 696static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
634 697
635static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000012b4 + 0x400*i0; } 698static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
636#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff 699#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
637#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0 700#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
638static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) 701static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
@@ -646,7 +709,7 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
646 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; 709 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
647} 710}
648 711
649static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00001404 + 0x400*i0; } 712static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
650#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001 713#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
651#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002 714#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
652#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300 715#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
@@ -686,23 +749,34 @@ static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_
686 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK; 749 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
687} 750}
688 751
689static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00001410 + 0x400*i0; } 752static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
690 753
691static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00001414 + 0x400*i0; } 754static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
692 755
693static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00001420 + 0x400*i0; } 756static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
694 757
695static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00001424 + 0x400*i0; } 758static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
696 759
697static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00003200 + 0x400*i0; } 760static inline uint32_t __offset_LM(uint32_t idx)
761{
762 switch (idx) {
763 case 0: return (mdp5_cfg->lm.base[0]);
764 case 1: return (mdp5_cfg->lm.base[1]);
765 case 2: return (mdp5_cfg->lm.base[2]);
766 case 3: return (mdp5_cfg->lm.base[3]);
767 case 4: return (mdp5_cfg->lm.base[4]);
768 default: return INVALID_IDX(idx);
769 }
770}
771static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
698 772
699static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00003200 + 0x400*i0; } 773static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
700#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002 774#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
701#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004 775#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
702#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008 776#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
703#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010 777#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
704 778
705static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00003204 + 0x400*i0; } 779static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
706#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000 780#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
707#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16 781#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
708static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) 782static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
@@ -716,13 +790,13 @@ static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
716 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK; 790 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
717} 791}
718 792
719static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00003208 + 0x400*i0; } 793static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
720 794
721static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00003210 + 0x400*i0; } 795static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
722 796
723static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; } 797static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
724 798
725static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; } 799static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
726#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003 800#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
727#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0 801#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
728static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) 802static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
@@ -744,57 +818,67 @@ static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
744#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000 818#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
745#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000 819#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
746 820
747static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003224 + 0x400*i0 + 0x30*i1; } 821static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
748 822
749static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003228 + 0x400*i0 + 0x30*i1; } 823static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
750 824
751static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000322c + 0x400*i0 + 0x30*i1; } 825static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
752 826
753static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003230 + 0x400*i0 + 0x30*i1; } 827static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
754 828
755static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003234 + 0x400*i0 + 0x30*i1; } 829static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
756 830
757static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003238 + 0x400*i0 + 0x30*i1; } 831static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
758 832
759static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000323c + 0x400*i0 + 0x30*i1; } 833static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
760 834
761static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003240 + 0x400*i0 + 0x30*i1; } 835static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
762 836
763static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003244 + 0x400*i0 + 0x30*i1; } 837static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
764 838
765static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003248 + 0x400*i0 + 0x30*i1; } 839static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
766 840
767static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000032e0 + 0x400*i0; } 841static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
768 842
769static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000032e4 + 0x400*i0; } 843static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
770 844
771static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000032e8 + 0x400*i0; } 845static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
772 846
773static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000032dc + 0x400*i0; } 847static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
774 848
775static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000032ec + 0x400*i0; } 849static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
776 850
777static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000032f0 + 0x400*i0; } 851static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
778 852
779static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000032f4 + 0x400*i0; } 853static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
780 854
781static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000032f8 + 0x400*i0; } 855static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
782 856
783static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000032fc + 0x400*i0; } 857static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
784 858
785static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00003300 + 0x400*i0; } 859static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
786 860
787static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00003304 + 0x400*i0; } 861static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
788 862
789static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00003308 + 0x400*i0; } 863static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
790 864
791static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000330c + 0x400*i0; } 865static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
792 866
793static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00003310 + 0x400*i0; } 867static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
794 868
795static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00004600 + 0x400*i0; } 869static inline uint32_t __offset_DSPP(uint32_t idx)
870{
871 switch (idx) {
872 case 0: return (mdp5_cfg->dspp.base[0]);
873 case 1: return (mdp5_cfg->dspp.base[1]);
874 case 2: return (mdp5_cfg->dspp.base[2]);
875 case 3: return (mdp5_cfg->dspp.base[3]);
876 default: return INVALID_IDX(idx);
877 }
878}
879static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
796 880
797static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00004600 + 0x400*i0; } 881static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
798#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001 882#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
799#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e 883#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
800#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1 884#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
@@ -811,29 +895,40 @@ static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
811#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000 895#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
812#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000 896#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
813 897
814static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00004630 + 0x400*i0; } 898static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
815 899
816static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00004750 + 0x400*i0; } 900static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
817 901
818static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00004810 + 0x400*i0; } 902static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
819 903
820static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00004830 + 0x400*i0; } 904static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
821 905
822static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00004834 + 0x400*i0; } 906static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
823 907
824static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00004838 + 0x400*i0; } 908static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
825 909
826static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000048dc + 0x400*i0; } 910static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
827 911
828static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000048b0 + 0x400*i0; } 912static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
829 913
830static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00012500 + 0x200*i0; } 914static inline uint32_t __offset_INTF(uint32_t idx)
915{
916 switch (idx) {
917 case 0: return (mdp5_cfg->intf.base[0]);
918 case 1: return (mdp5_cfg->intf.base[1]);
919 case 2: return (mdp5_cfg->intf.base[2]);
920 case 3: return (mdp5_cfg->intf.base[3]);
921 case 4: return (mdp5_cfg->intf.base[4]);
922 default: return INVALID_IDX(idx);
923 }
924}
925static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
831 926
832static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00012500 + 0x200*i0; } 927static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
833 928
834static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00012504 + 0x200*i0; } 929static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
835 930
836static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00012508 + 0x200*i0; } 931static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
837#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff 932#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
838#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0 933#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
839static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) 934static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
@@ -847,23 +942,23 @@ static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
847 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK; 942 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
848} 943}
849 944
850static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0001250c + 0x200*i0; } 945static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
851 946
852static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00012510 + 0x200*i0; } 947static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
853 948
854static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00012514 + 0x200*i0; } 949static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
855 950
856static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00012518 + 0x200*i0; } 951static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
857 952
858static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0001251c + 0x200*i0; } 953static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
859 954
860static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00012520 + 0x200*i0; } 955static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
861 956
862static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00012524 + 0x200*i0; } 957static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
863 958
864static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00012528 + 0x200*i0; } 959static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
865 960
866static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0001252c + 0x200*i0; } 961static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
867#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff 962#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
868#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0 963#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
869static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) 964static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
@@ -872,7 +967,7 @@ static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
872} 967}
873#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000 968#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
874 969
875static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00012530 + 0x200*i0; } 970static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
876#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff 971#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
877#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0 972#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
878static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) 973static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
@@ -880,11 +975,11 @@ static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
880 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK; 975 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
881} 976}
882 977
883static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00012534 + 0x200*i0; } 978static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
884 979
885static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00012538 + 0x200*i0; } 980static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
886 981
887static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0001253c + 0x200*i0; } 982static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
888#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff 983#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
889#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0 984#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
890static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) 985static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
@@ -898,7 +993,7 @@ static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
898 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK; 993 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
899} 994}
900 995
901static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00012540 + 0x200*i0; } 996static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
902#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff 997#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
903#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0 998#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
904static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) 999static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
@@ -913,124 +1008,132 @@ static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
913} 1008}
914#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000 1009#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
915 1010
916static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00012544 + 0x200*i0; } 1011static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
917 1012
918static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00012548 + 0x200*i0; } 1013static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
919 1014
920static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0001254c + 0x200*i0; } 1015static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
921 1016
922static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00012550 + 0x200*i0; } 1017static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
923#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001 1018#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
924#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002 1019#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
925#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004 1020#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
926 1021
927static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00012554 + 0x200*i0; } 1022static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
928 1023
929static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00012558 + 0x200*i0; } 1024static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
930 1025
931static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0001255c + 0x200*i0; } 1026static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
932 1027
933static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00012584 + 0x200*i0; } 1028static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
934 1029
935static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00012590 + 0x200*i0; } 1030static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
936 1031
937static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000125a8 + 0x200*i0; } 1032static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
938 1033
939static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000125ac + 0x200*i0; } 1034static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
940 1035
941static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000125b0 + 0x200*i0; } 1036static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
942 1037
943static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000125f0 + 0x200*i0; } 1038static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
944 1039
945static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000125f4 + 0x200*i0; } 1040static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
946 1041
947static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000125f8 + 0x200*i0; } 1042static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
948 1043
949static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00012600 + 0x200*i0; } 1044static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
950 1045
951static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00012604 + 0x200*i0; } 1046static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
952 1047
953static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00012608 + 0x200*i0; } 1048static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
954 1049
955static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0001260c + 0x200*i0; } 1050static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
956 1051
957static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00012610 + 0x200*i0; } 1052static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
958 1053
959static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00012614 + 0x200*i0; } 1054static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
960 1055
961static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00012618 + 0x200*i0; } 1056static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
962 1057
963static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0001261c + 0x200*i0; } 1058static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
964 1059
965static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00013100 + 0x200*i0; } 1060static inline uint32_t __offset_AD(uint32_t idx)
1061{
1062 switch (idx) {
1063 case 0: return (mdp5_cfg->ad.base[0]);
1064 case 1: return (mdp5_cfg->ad.base[1]);
1065 default: return INVALID_IDX(idx);
1066 }
1067}
1068static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
966 1069
967static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00013100 + 0x200*i0; } 1070static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
968 1071
969static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00013104 + 0x200*i0; } 1072static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
970 1073
971static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00013108 + 0x200*i0; } 1074static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
972 1075
973static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0001310c + 0x200*i0; } 1076static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
974 1077
975static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00013110 + 0x200*i0; } 1078static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
976 1079
977static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00013114 + 0x200*i0; } 1080static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
978 1081
979static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00013118 + 0x200*i0; } 1082static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
980 1083
981static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0001311c + 0x200*i0; } 1084static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
982 1085
983static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00013120 + 0x200*i0; } 1086static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
984 1087
985static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00013124 + 0x200*i0; } 1088static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
986 1089
987static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00013128 + 0x200*i0; } 1090static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
988 1091
989static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0001312c + 0x200*i0; } 1092static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
990 1093
991static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00013130 + 0x200*i0; } 1094static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
992 1095
993static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00013134 + 0x200*i0; } 1096static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
994 1097
995static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00013138 + 0x200*i0; } 1098static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
996 1099
997static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0001317c + 0x200*i0; } 1100static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
998 1101
999static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000131c8 + 0x200*i0; } 1102static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1000 1103
1001static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000131cc + 0x200*i0; } 1104static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1002 1105
1003static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000131d0 + 0x200*i0; } 1106static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1004 1107
1005static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000131d4 + 0x200*i0; } 1108static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1006 1109
1007static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000131d8 + 0x200*i0; } 1110static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1008 1111
1009static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000131dc + 0x200*i0; } 1112static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1010 1113
1011static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000131e0 + 0x200*i0; } 1114static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1012 1115
1013static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000131e8 + 0x200*i0; } 1116static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1014 1117
1015static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000131ec + 0x200*i0; } 1118static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1016 1119
1017static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000131f0 + 0x200*i0; } 1120static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1018 1121
1019static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000131f4 + 0x200*i0; } 1122static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1020 1123
1021static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000131f8 + 0x200*i0; } 1124static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1022 1125
1023static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00013200 + 0x200*i0; } 1126static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1024 1127
1025static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00013244 + 0x200*i0; } 1128static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1026 1129
1027static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00013248 + 0x200*i0; } 1130static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1028 1131
1029static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0001324c + 0x200*i0; } 1132static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1030 1133
1031static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00013254 + 0x200*i0; } 1134static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1032 1135
1033static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00013258 + 0x200*i0; } 1136static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1034 1137
1035 1138
1036#endif /* MDP5_XML */ 1139#endif /* MDP5_XML */
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 17175b5035b3..31a2c6331a1d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -26,14 +26,98 @@ static const char *iommu_ports[] = {
26 26
27static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev); 27static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);
28 28
29static int mdp5_hw_init(struct msm_kms *kms) 29const struct mdp5_config *mdp5_cfg;
30
31static const struct mdp5_config msm8x74_config = {
32 .name = "msm8x74",
33 .ctl = {
34 .count = 5,
35 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
36 },
37 .pipe_vig = {
38 .count = 3,
39 .base = { 0x01200, 0x01600, 0x01a00 },
40 },
41 .pipe_rgb = {
42 .count = 3,
43 .base = { 0x01e00, 0x02200, 0x02600 },
44 },
45 .pipe_dma = {
46 .count = 2,
47 .base = { 0x02a00, 0x02e00 },
48 },
49 .lm = {
50 .count = 5,
51 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
52 },
53 .dspp = {
54 .count = 3,
55 .base = { 0x04600, 0x04a00, 0x04e00 },
56 },
57 .ad = {
58 .count = 2,
59 .base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */
60 },
61 .intf = {
62 .count = 4,
63 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
64 },
65};
66
67static const struct mdp5_config apq8084_config = {
68 .name = "apq8084",
69 .ctl = {
70 .count = 5,
71 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
72 },
73 .pipe_vig = {
74 .count = 4,
75 .base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
76 },
77 .pipe_rgb = {
78 .count = 4,
79 .base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
80 },
81 .pipe_dma = {
82 .count = 2,
83 .base = { 0x03200, 0x03600 },
84 },
85 .lm = {
86 .count = 6,
87 .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
88 },
89 .dspp = {
90 .count = 4,
91 .base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
92
93 },
94 .ad = {
95 .count = 3,
96 .base = { 0x13500, 0x13700, 0x13900 },
97 },
98 .intf = {
99 .count = 5,
100 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
101 },
102};
103
104struct mdp5_config_entry {
105 int revision;
106 const struct mdp5_config *config;
107};
108
109static const struct mdp5_config_entry mdp5_configs[] = {
110 { .revision = 0, .config = &msm8x74_config },
111 { .revision = 2, .config = &msm8x74_config },
112 { .revision = 3, .config = &apq8084_config },
113};
114
115static int mdp5_select_hw_cfg(struct msm_kms *kms)
30{ 116{
31 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 117 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
32 struct drm_device *dev = mdp5_kms->dev; 118 struct drm_device *dev = mdp5_kms->dev;
33 uint32_t version, major, minor; 119 uint32_t version, major, minor;
34 int ret = 0; 120 int i, ret = 0;
35
36 pm_runtime_get_sync(dev->dev);
37 121
38 mdp5_enable(mdp5_kms); 122 mdp5_enable(mdp5_kms);
39 version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION); 123 version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
@@ -44,8 +128,8 @@ static int mdp5_hw_init(struct msm_kms *kms)
44 128
45 DBG("found MDP5 version v%d.%d", major, minor); 129 DBG("found MDP5 version v%d.%d", major, minor);
46 130
47 if ((major != 1) || ((minor != 0) && (minor != 2))) { 131 if (major != 1) {
48 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n", 132 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
49 major, minor); 133 major, minor);
50 ret = -ENXIO; 134 ret = -ENXIO;
51 goto out; 135 goto out;
@@ -53,6 +137,35 @@ static int mdp5_hw_init(struct msm_kms *kms)
53 137
54 mdp5_kms->rev = minor; 138 mdp5_kms->rev = minor;
55 139
140 /* only after mdp5_cfg global pointer's init can we access the hw */
141 for (i = 0; i < ARRAY_SIZE(mdp5_configs); i++) {
142 if (mdp5_configs[i].revision != minor)
143 continue;
144 mdp5_kms->hw_cfg = mdp5_cfg = mdp5_configs[i].config;
145 break;
146 }
147 if (unlikely(!mdp5_kms->hw_cfg)) {
148 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
149 major, minor);
150 ret = -ENXIO;
151 goto out;
152 }
153
154 DBG("MDP5: %s config selected", mdp5_kms->hw_cfg->name);
155
156 return 0;
157out:
158 return ret;
159}
160
161static int mdp5_hw_init(struct msm_kms *kms)
162{
163 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
164 struct drm_device *dev = mdp5_kms->dev;
165 int i;
166
167 pm_runtime_get_sync(dev->dev);
168
56 /* Magic unknown register writes: 169 /* Magic unknown register writes:
57 * 170 *
58 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 171 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
@@ -78,15 +191,13 @@ static int mdp5_hw_init(struct msm_kms *kms)
78 */ 191 */
79 192
80 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 193 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
81 mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(0), 0);
82 mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(1), 0);
83 mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(2), 0);
84 mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(3), 0);
85 194
86out: 195 for (i = 0; i < mdp5_kms->hw_cfg->ctl.count; i++)
196 mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(i), 0);
197
87 pm_runtime_put_sync(dev->dev); 198 pm_runtime_put_sync(dev->dev);
88 199
89 return ret; 200 return 0;
90} 201}
91 202
92static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, 203static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
@@ -161,7 +272,7 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
161static int modeset_init(struct mdp5_kms *mdp5_kms) 272static int modeset_init(struct mdp5_kms *mdp5_kms)
162{ 273{
163 static const enum mdp5_pipe crtcs[] = { 274 static const enum mdp5_pipe crtcs[] = {
164 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, 275 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
165 }; 276 };
166 struct drm_device *dev = mdp5_kms->dev; 277 struct drm_device *dev = mdp5_kms->dev;
167 struct msm_drm_private *priv = dev->dev_private; 278 struct msm_drm_private *priv = dev->dev_private;
@@ -169,7 +280,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
169 int i, ret; 280 int i, ret;
170 281
171 /* construct CRTCs: */ 282 /* construct CRTCs: */
172 for (i = 0; i < ARRAY_SIZE(crtcs); i++) { 283 for (i = 0; i < mdp5_kms->hw_cfg->pipe_rgb.count; i++) {
173 struct drm_plane *plane; 284 struct drm_plane *plane;
174 struct drm_crtc *crtc; 285 struct drm_crtc *crtc;
175 286
@@ -246,7 +357,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
246 struct mdp5_kms *mdp5_kms; 357 struct mdp5_kms *mdp5_kms;
247 struct msm_kms *kms = NULL; 358 struct msm_kms *kms = NULL;
248 struct msm_mmu *mmu; 359 struct msm_mmu *mmu;
249 int ret; 360 int i, ret;
250 361
251 mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); 362 mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
252 if (!mdp5_kms) { 363 if (!mdp5_kms) {
@@ -307,15 +418,17 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
307 418
308 ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk); 419 ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk);
309 420
421 ret = mdp5_select_hw_cfg(kms);
422 if (ret)
423 goto fail;
424
310 /* make sure things are off before attaching iommu (bootloader could 425 /* make sure things are off before attaching iommu (bootloader could
311 * have left things on, in which case we'll start getting faults if 426 * have left things on, in which case we'll start getting faults if
312 * we don't disable): 427 * we don't disable):
313 */ 428 */
314 mdp5_enable(mdp5_kms); 429 mdp5_enable(mdp5_kms);
315 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(0), 0); 430 for (i = 0; i < mdp5_kms->hw_cfg->intf.count; i++)
316 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(1), 0); 431 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
317 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(2), 0);
318 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(3), 0);
319 mdp5_disable(mdp5_kms); 432 mdp5_disable(mdp5_kms);
320 mdelay(16); 433 mdelay(16);
321 434
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 6e981b692d1d..5bf340dd0f00 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -21,6 +21,24 @@
21#include "msm_drv.h" 21#include "msm_drv.h"
22#include "msm_kms.h" 22#include "msm_kms.h"
23#include "mdp/mdp_kms.h" 23#include "mdp/mdp_kms.h"
24/* dynamic offsets used by mdp5.xml.h (initialized in mdp5_kms.c) */
25#define MDP5_MAX_BASES 8
26struct mdp5_sub_block {
27 int count;
28 uint32_t base[MDP5_MAX_BASES];
29};
30struct mdp5_config {
31 char *name;
32 struct mdp5_sub_block ctl;
33 struct mdp5_sub_block pipe_vig;
34 struct mdp5_sub_block pipe_rgb;
35 struct mdp5_sub_block pipe_dma;
36 struct mdp5_sub_block lm;
37 struct mdp5_sub_block dspp;
38 struct mdp5_sub_block ad;
39 struct mdp5_sub_block intf;
40};
41extern const struct mdp5_config *mdp5_cfg;
24#include "mdp5.xml.h" 42#include "mdp5.xml.h"
25#include "mdp5_smp.h" 43#include "mdp5_smp.h"
26 44
@@ -30,6 +48,7 @@ struct mdp5_kms {
30 struct drm_device *dev; 48 struct drm_device *dev;
31 49
32 int rev; 50 int rev;
51 const struct mdp5_config *hw_cfg;
33 52
34 /* mapper-id used to request GEM buffer mapped for scanout: */ 53 /* mapper-id used to request GEM buffer mapped for scanout: */
35 int id; 54 int id;
@@ -82,6 +101,7 @@ static inline const char *pipe2name(enum mdp5_pipe pipe)
82 NAME(VIG0), NAME(VIG1), NAME(VIG2), 101 NAME(VIG0), NAME(VIG1), NAME(VIG2),
83 NAME(RGB0), NAME(RGB1), NAME(RGB2), 102 NAME(RGB0), NAME(RGB1), NAME(RGB2),
84 NAME(DMA0), NAME(DMA1), 103 NAME(DMA0), NAME(DMA1),
104 NAME(VIG3), NAME(RGB3),
85#undef NAME 105#undef NAME
86 }; 106 };
87 return names[pipe]; 107 return names[pipe];
@@ -98,6 +118,8 @@ static inline uint32_t pipe2flush(enum mdp5_pipe pipe)
98 case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2; 118 case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;
99 case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0; 119 case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;
100 case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1; 120 case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;
121 case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3;
122 case SSPP_RGB3: return MDP5_CTL_FLUSH_RGB3;
101 default: return 0; 123 default: return 0;
102 } 124 }
103} 125}
@@ -108,6 +130,7 @@ static inline int pipe2nclients(enum mdp5_pipe pipe)
108 case SSPP_RGB0: 130 case SSPP_RGB0:
109 case SSPP_RGB1: 131 case SSPP_RGB1:
110 case SSPP_RGB2: 132 case SSPP_RGB2:
133 case SSPP_RGB3:
111 return 1; 134 return 1;
112 default: 135 default:
113 return 3; 136 return 3;
@@ -126,6 +149,8 @@ static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane)
126 case SSPP_RGB2: return CID_RGB2; 149 case SSPP_RGB2: return CID_RGB2;
127 case SSPP_DMA0: return CID_DMA0_Y + plane; 150 case SSPP_DMA0: return CID_DMA0_Y + plane;
128 case SSPP_DMA1: return CID_DMA1_Y + plane; 151 case SSPP_DMA1: return CID_DMA1_Y + plane;
152 case SSPP_VIG3: return CID_VIG3_Y + plane;
153 case SSPP_RGB3: return CID_RGB3;
129 default: return CID_UNUSED; 154 default: return CID_UNUSED;
130 } 155 }
131} 156}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 02:07:31 -0400