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author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-08-13 05:09:03 -0400 |
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committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-09-19 03:30:37 -0400 |
commit | 3c7c5dab44d6c8861bc86dab924353d8d40344f8 (patch) | |
tree | 43925a23bdd177836d4428710c4cb8b05af7009c | |
parent | fa6d79d27614223d82418023b7f5300f1a1530d3 (diff) |
ARM: OMAP5: Enable arch timer support
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/mach-omap2/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/timer.c | 7 |
3 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e527083746..7b986eddd0b9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
@@ -33,9 +33,21 @@ | |||
33 | cpus { | 33 | cpus { |
34 | cpu@0 { | 34 | cpu@0 { |
35 | compatible = "arm,cortex-a15"; | 35 | compatible = "arm,cortex-a15"; |
36 | timer { | ||
37 | compatible = "arm,armv7-timer"; | ||
38 | /* 14th PPI IRQ, active low level-sensitive */ | ||
39 | interrupts = <1 14 0x308>; | ||
40 | clock-frequency = <6144000>; | ||
41 | }; | ||
36 | }; | 42 | }; |
37 | cpu@1 { | 43 | cpu@1 { |
38 | compatible = "arm,cortex-a15"; | 44 | compatible = "arm,cortex-a15"; |
45 | timer { | ||
46 | compatible = "arm,armv7-timer"; | ||
47 | /* 14th PPI IRQ, active low level-sensitive */ | ||
48 | interrupts = <1 14 0x308>; | ||
49 | clock-frequency = <6144000>; | ||
50 | }; | ||
39 | }; | 51 | }; |
40 | }; | 52 | }; |
41 | 53 | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4b773fd56978..4609163b0395 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -74,6 +74,7 @@ config SOC_OMAP5 | |||
74 | select HAVE_SMP | 74 | select HAVE_SMP |
75 | select ARM_CPU_SUSPEND if PM | 75 | select ARM_CPU_SUSPEND if PM |
76 | select SOC_HAS_REALTIME_COUNTER | 76 | select SOC_HAS_REALTIME_COUNTER |
77 | select ARM_ARCH_TIMER | ||
77 | 78 | ||
78 | comment "OMAP Core Type" | 79 | comment "OMAP Core Type" |
79 | depends on ARCH_OMAP2 | 80 | depends on ARCH_OMAP2 |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 026fcfff6698..2c5a45d8ca8c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include <plat/dmtimer.h> | 41 | #include <plat/dmtimer.h> |
42 | #include <asm/smp_twd.h> | 42 | #include <asm/smp_twd.h> |
43 | #include <asm/sched_clock.h> | 43 | #include <asm/sched_clock.h> |
44 | #include <asm/arch_timer.h> | ||
44 | #include "common.h" | 45 | #include "common.h" |
45 | #include <plat/omap_hwmod.h> | 46 | #include <plat/omap_hwmod.h> |
46 | #include <plat/omap_device.h> | 47 | #include <plat/omap_device.h> |
@@ -488,9 +489,15 @@ OMAP_SYS_TIMER(4) | |||
488 | #ifdef CONFIG_SOC_OMAP5 | 489 | #ifdef CONFIG_SOC_OMAP5 |
489 | static void __init omap5_timer_init(void) | 490 | static void __init omap5_timer_init(void) |
490 | { | 491 | { |
492 | int err; | ||
493 | |||
491 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); | 494 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); |
492 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); | 495 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
493 | realtime_counter_init(); | 496 | realtime_counter_init(); |
497 | |||
498 | err = arch_timer_of_register(); | ||
499 | if (err) | ||
500 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | ||
494 | } | 501 | } |
495 | OMAP_SYS_TIMER(5) | 502 | OMAP_SYS_TIMER(5) |
496 | #endif | 503 | #endif |