diff options
author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2014-04-04 07:31:47 -0400 |
---|---|---|
committer | Mark Brown <broonie@linaro.org> | 2014-04-14 12:24:24 -0400 |
commit | 3c25f916d378da6f06874abfc5c18e5a40e2d8c0 (patch) | |
tree | 0aa24f6037ed1c211f3c5e3ff25528faad3d7a33 | |
parent | 423761e0cab39c98f0fd9387ea44b98c2a4ca6fa (diff) |
ASoC: davinci-mcasp: Remove excess empty lines from davinci_mcasp_set_dai_fmt()
To make the code look uniform.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r-- | sound/soc/davinci/davinci-mcasp.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 2b6722024fbd..8007fcf428d9 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c | |||
@@ -280,7 +280,6 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
280 | case SND_SOC_DAIFMT_DSP_A: | 280 | case SND_SOC_DAIFMT_DSP_A: |
281 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | 281 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
282 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | 282 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
283 | |||
284 | /* 1st data bit occur one ACLK cycle after the frame sync */ | 283 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
285 | data_delay = 1; | 284 | data_delay = 1; |
286 | break; | 285 | break; |
@@ -288,7 +287,6 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
288 | case SND_SOC_DAIFMT_AC97: | 287 | case SND_SOC_DAIFMT_AC97: |
289 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | 288 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
290 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | 289 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
291 | |||
292 | /* No delay after FS */ | 290 | /* No delay after FS */ |
293 | data_delay = 0; | 291 | data_delay = 0; |
294 | break; | 292 | break; |
@@ -296,7 +294,6 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
296 | /* configure a full-word SYNC pulse (LRCLK) */ | 294 | /* configure a full-word SYNC pulse (LRCLK) */ |
297 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | 295 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
298 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | 296 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); |
299 | |||
300 | /* 1st data bit occur one ACLK cycle after the frame sync */ | 297 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
301 | data_delay = 1; | 298 | data_delay = 1; |
302 | /* FS need to be inverted */ | 299 | /* FS need to be inverted */ |
@@ -356,7 +353,6 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
356 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | 353 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); |
357 | mcasp->bclk_master = 0; | 354 | mcasp->bclk_master = 0; |
358 | break; | 355 | break; |
359 | |||
360 | default: | 356 | default: |
361 | ret = -EINVAL; | 357 | ret = -EINVAL; |
362 | goto out; | 358 | goto out; |
@@ -368,25 +364,21 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
368 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | 364 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
369 | fs_pol_rising = true; | 365 | fs_pol_rising = true; |
370 | break; | 366 | break; |
371 | |||
372 | case SND_SOC_DAIFMT_NB_IF: | 367 | case SND_SOC_DAIFMT_NB_IF: |
373 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | 368 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
374 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | 369 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
375 | fs_pol_rising = false; | 370 | fs_pol_rising = false; |
376 | break; | 371 | break; |
377 | |||
378 | case SND_SOC_DAIFMT_IB_IF: | 372 | case SND_SOC_DAIFMT_IB_IF: |
379 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | 373 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
380 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | 374 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
381 | fs_pol_rising = false; | 375 | fs_pol_rising = false; |
382 | break; | 376 | break; |
383 | |||
384 | case SND_SOC_DAIFMT_NB_NF: | 377 | case SND_SOC_DAIFMT_NB_NF: |
385 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); | 378 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
386 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); | 379 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
387 | fs_pol_rising = true; | 380 | fs_pol_rising = true; |
388 | break; | 381 | break; |
389 | |||
390 | default: | 382 | default: |
391 | ret = -EINVAL; | 383 | ret = -EINVAL; |
392 | goto out; | 384 | goto out; |