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authorArnd Bergmann <arnd@arndb.de>2014-05-23 15:33:48 -0400
committerArnd Bergmann <arnd@arndb.de>2014-05-23 15:57:23 -0400
commit3c2580173e3bc820a8f8c0db968f757b8eca7fe5 (patch)
tree153ecf3842bcaf36ecac4f0c2b008fa3b7485488
parent8ad0bbd8696904c34a1fb266a25efe2be818c0c7 (diff)
parent5e669ec583e2687d3512d965cf2e209095f70c62 (diff)
Merge tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux into next/soc
Merge "Allwinner Core additions for 3.16, take 2" from Maxime Ripard: - Convert the A31 SMP operations to the CPU_METHOD_OF_DECLARE mechanism - Remove the reset code from the machine definition, that removes pretty much all the code left in mach-sunxi * tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux: ARM: sunxi: Remove init_machine callback ARM: sunxi: Remove reset code from the platform ARM: sun6i: Retire the smp field in A31 machine Documentation: dt: bindings: Document Allwinner A31 enable method ARM: sun6i: Use CPU_METHOD_OF_DECLARE Documentation: dt: bindings: Document ARM PSCI enable method Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt2
-rw-r--r--arch/arm/mach-sunxi/common.h19
-rw-r--r--arch/arm/mach-sunxi/platsmp.c3
-rw-r--r--arch/arm/mach-sunxi/sunxi.c110
4 files changed, 3 insertions, 131 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 4bbcf4fb7583..e4b6dafbcfc4 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -182,6 +182,8 @@ nodes to be present and contain the properties described below.
182 "psci" 182 "psci"
183 # On ARM 32-bit systems this property is optional and 183 # On ARM 32-bit systems this property is optional and
184 can be one of: 184 can be one of:
185 "arm,psci"
186 "allwinner,sun6i-a31"
185 "qcom,gcc-msm8660" 187 "qcom,gcc-msm8660"
186 "qcom,kpss-acc-v1" 188 "qcom,kpss-acc-v1"
187 "qcom,kpss-acc-v2" 189 "qcom,kpss-acc-v2"
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
deleted file mode 100644
index 9e5ac4756cbb..000000000000
--- a/arch/arm/mach-sunxi/common.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Core functions for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ARCH_SUNXI_COMMON_H_
14#define __ARCH_SUNXI_COMMON_H_
15
16void sun6i_secondary_startup(void);
17extern struct smp_operations sun6i_smp_ops;
18
19#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 0c7dbce033cc..c53077bb8c3f 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -21,8 +21,6 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23 23
24#include "common.h"
25
26#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) 24#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
27#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) 25#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
28#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) 26#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
@@ -122,3 +120,4 @@ struct smp_operations sun6i_smp_ops __initdata = {
122 .smp_prepare_cpus = sun6i_smp_prepare_cpus, 120 .smp_prepare_cpus = sun6i_smp_prepare_cpus,
123 .smp_boot_secondary = sun6i_smp_boot_secondary, 121 .smp_boot_secondary = sun6i_smp_boot_secondary,
124}; 122};
123CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 460b5a4962ef..ff2e6a404dab 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,111 +12,8 @@
12 12
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
23 15
24#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#include "common.h"
29
30#define SUN4I_WATCHDOG_CTRL_REG 0x00
31#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
32#define SUN4I_WATCHDOG_MODE_REG 0x04
33#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
34#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
35
36#define SUN6I_WATCHDOG1_IRQ_REG 0x00
37#define SUN6I_WATCHDOG1_CTRL_REG 0x10
38#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
40#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
41#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
42#define SUN6I_WATCHDOG1_MODE_REG 0x18
43#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
44
45static void __iomem *wdt_base;
46
47static void sun4i_restart(enum reboot_mode mode, const char *cmd)
48{
49 if (!wdt_base)
50 return;
51
52 /* Enable timer and set reset bit in the watchdog */
53 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
54 wdt_base + SUN4I_WATCHDOG_MODE_REG);
55
56 /*
57 * Restart the watchdog. The default (and lowest) interval
58 * value for the watchdog is 0.5s.
59 */
60 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
61
62 while (1) {
63 mdelay(5);
64 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
65 wdt_base + SUN4I_WATCHDOG_MODE_REG);
66 }
67}
68
69static void sun6i_restart(enum reboot_mode mode, const char *cmd)
70{
71 if (!wdt_base)
72 return;
73
74 /* Disable interrupts */
75 writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
76
77 /* We want to disable the IRQ and just reset the whole system */
78 writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
79 wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
80
81 /* Enable timer. The default and lowest interval value is 0.5s */
82 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
83 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
84
85 /* Restart the watchdog. */
86 writel(SUN6I_WATCHDOG1_CTRL_RESTART,
87 wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
88
89 while (1) {
90 mdelay(5);
91 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
92 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
93 }
94}
95
96static struct of_device_id sunxi_restart_ids[] = {
97 { .compatible = "allwinner,sun4i-a10-wdt" },
98 { .compatible = "allwinner,sun6i-a31-wdt" },
99 { /*sentinel*/ }
100};
101
102static void sunxi_setup_restart(void)
103{
104 struct device_node *np;
105
106 np = of_find_matching_node(NULL, sunxi_restart_ids);
107 if (WARN(!np, "unable to setup watchdog restart"))
108 return;
109
110 wdt_base = of_iomap(np, 0);
111 WARN(!wdt_base, "failed to map watchdog base address");
112}
113
114static void __init sunxi_dt_init(void)
115{
116 sunxi_setup_restart();
117
118 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
119}
120 17
121static const char * const sunxi_board_dt_compat[] = { 18static const char * const sunxi_board_dt_compat[] = {
122 "allwinner,sun4i-a10", 19 "allwinner,sun4i-a10",
@@ -126,9 +23,7 @@ static const char * const sunxi_board_dt_compat[] = {
126}; 23};
127 24
128DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 25DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
129 .init_machine = sunxi_dt_init,
130 .dt_compat = sunxi_board_dt_compat, 26 .dt_compat = sunxi_board_dt_compat,
131 .restart = sun4i_restart,
132MACHINE_END 27MACHINE_END
133 28
134static const char * const sun6i_board_dt_compat[] = { 29static const char * const sun6i_board_dt_compat[] = {
@@ -145,11 +40,8 @@ static void __init sun6i_timer_init(void)
145} 40}
146 41
147DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") 42DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
148 .init_machine = sunxi_dt_init,
149 .init_time = sun6i_timer_init, 43 .init_time = sun6i_timer_init,
150 .dt_compat = sun6i_board_dt_compat, 44 .dt_compat = sun6i_board_dt_compat,
151 .restart = sun6i_restart,
152 .smp = smp_ops(sun6i_smp_ops),
153MACHINE_END 45MACHINE_END
154 46
155static const char * const sun7i_board_dt_compat[] = { 47static const char * const sun7i_board_dt_compat[] = {
@@ -158,7 +50,5 @@ static const char * const sun7i_board_dt_compat[] = {
158}; 50};
159 51
160DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 52DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
161 .init_machine = sunxi_dt_init,
162 .dt_compat = sun7i_board_dt_compat, 53 .dt_compat = sun7i_board_dt_compat,
163 .restart = sun4i_restart,
164MACHINE_END 54MACHINE_END