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authorJesse Barnes <jbarnes@virtuousgeek.org>2011-07-27 14:51:40 -0400
committerKeith Packard <keithp@keithp.com>2011-07-28 19:28:21 -0400
commit3bcf603f6d5d18bd9d076dc280de71f48add4101 (patch)
tree6d1ed198fd759d3e7aeccd32bc8b5059785da26a
parent120eced9efe7fdb5123db4ea47e9adee9b66284e (diff)
drm/i915: apply timing generator bug workaround on CPT and PPT
On CougarPoint and PantherPoint PCH chips, the timing generator may fail to start after DP training completes. This is due to a bug in the FDI autotraining detect logic (which will stall the timing generator and re-enable it once training completes), so disable it to avoid silent DP mode setting failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7315653a842..00bd51070314 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3072,6 +3072,11 @@
3072#define TRANS_6BPC (2<<5) 3072#define TRANS_6BPC (2<<5)
3073#define TRANS_12BPC (3<<5) 3073#define TRANS_12BPC (3<<5)
3074 3074
3075#define _TRANSA_CHICKEN2 0xf0064
3076#define _TRANSB_CHICKEN2 0xf1064
3077#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3078#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3079
3075#define SOUTH_CHICKEN2 0xc2004 3080#define SOUTH_CHICKEN2 0xc2004
3076#define DPLS_EDP_PPS_FIX_DIS (1<<0) 3081#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3077 3082
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d9b8c15998d9..502efc37b074 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7524,6 +7524,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
7524static void cpt_init_clock_gating(struct drm_device *dev) 7524static void cpt_init_clock_gating(struct drm_device *dev)
7525{ 7525{
7526 struct drm_i915_private *dev_priv = dev->dev_private; 7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 int pipe;
7527 7528
7528 /* 7529 /*
7529 * On Ibex Peak and Cougar Point, we need to disable clock 7530 * On Ibex Peak and Cougar Point, we need to disable clock
@@ -7533,6 +7534,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
7533 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 7534 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7534 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 7535 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7535 DPLS_EDP_PPS_FIX_DIS); 7536 DPLS_EDP_PPS_FIX_DIS);
7537 /* Without this, mode sets may fail silently on FDI */
7538 for_each_pipe(pipe)
7539 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7536} 7540}
7537 7541
7538static void ironlake_teardown_rc6(struct drm_device *dev) 7542static void ironlake_teardown_rc6(struct drm_device *dev)